JPH0318052A - Formation of semiconductor resistance - Google Patents
Formation of semiconductor resistanceInfo
- Publication number
- JPH0318052A JPH0318052A JP1151910A JP15191089A JPH0318052A JP H0318052 A JPH0318052 A JP H0318052A JP 1151910 A JP1151910 A JP 1151910A JP 15191089 A JP15191089 A JP 15191089A JP H0318052 A JPH0318052 A JP H0318052A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- basic
- mask pattern
- resistance
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000000034 method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000005452 bending Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、コンピュータを用いてマスクレイアウト設計
を行う半導体抵抗形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming a semiconductor resistor in which a mask layout is designed using a computer.
従来の技術
近年、半導体集積回路は大規模化の一途をたどりコンピ
ュータを用いた自動設計の要求が高まっている。以下に
従来のコンピュータを用いた抵抗体のマスクレイアウト
自動設計手法について説明する。2. Description of the Related Art In recent years, the scale of semiconductor integrated circuits has continued to increase, and there has been an increasing demand for automatic design using computers. A conventional automatic mask layout design method for a resistor using a computer will be described below.
従来の手法では、抵抗のマスクパターンを自動生成する
際は、その抵抗に関する情報（たとえば、抵抗値，抵抗
拡散層の単位抵抗値，抵抗幅，４直列・並列区分など）
を回路図からコンピュータに抽出し、それに基づいて抵
抗のマスクパターンを生成していた。In conventional methods, when automatically generating a resistor mask pattern, information about the resistor (for example, resistance value, unit resistance value of the resistor diffusion layer, resistance width, 4 series/parallel divisions, etc.) is required.
was extracted from the circuit diagram into a computer, and a resistor mask pattern was generated based on it.
発明が解決しようとする課題
しかしながら、上記従来の抵抗マスクパターンの生成手
法では、その要求の多種多様さから、現実的な処理時間
内に最適な抵抗パターンを生成することは困難であった
。Problems to be Solved by the Invention However, with the conventional resistance mask pattern generation method described above, it has been difficult to generate an optimal resistance pattern within a realistic processing time due to the wide variety of requirements.
本発明は、上記従来の課題を解決するもので、コンピュ
ータによるマスクレイアウト自動設計において短時間の
うちに最適な抵抗マスクパターンを自動生威することを
目的とする。The present invention solves the above-mentioned conventional problems, and aims to automatically generate an optimal resistor mask pattern in a short time in automatic mask layout design using a computer.
課題を解決するための手段
この問題を解決するために、本発明は、抵抗マスクパタ
ーンに、複数の基本パターンを用意し、これらの中から
レイアウト上の最適パターンを１つ選び出し、これを修
正することにより求める抵゛抗マスクパターンを得る構
成を有している。Means for Solving the Problem In order to solve this problem, the present invention prepares a plurality of basic patterns for the resistor mask pattern, selects one optimal pattern on the layout from these, and corrects it. The structure is such that a desired resistance mask pattern can be obtained by doing this.
作用
この構成により、抵抗マスクパターンの多様な要求に対
して、適切なマスクパターンを高速に形成することが可
能となる。また、基本パターンの追加・修正により、複
雑な形状の抵抗マスクパターンの形成も可能となる。Function: With this configuration, it is possible to form appropriate mask patterns at high speed in response to various requirements for resistive mask patterns. Further, by adding or modifying the basic pattern, it is also possible to form a resistive mask pattern with a complicated shape.
実施例
本発明の一実施例を第１図の基本マスク平面パターン図
、第２図（ａ）〜（ｅ）のプロセス例図を用いて説明す
る。第１図、第２図で同一のものには同一番号を付して
いる。抵抗設定の条件として、「抵抗折り曲げ不可」が
あるとする。Embodiment An embodiment of the present invention will be described with reference to the basic mask plane pattern diagram in FIG. 1 and the process example diagrams in FIGS. 2(a) to 2(e). Components that are the same in FIG. 1 and FIG. 2 are given the same numbers. Assume that the resistance setting condition is "resistance cannot be bent."
まず、第１図に平面パターン図で示したように、抵抗の
基本マスクパターンを多数用意する。First, as shown in the plane pattern diagram in FIG. 1, a large number of basic resistor mask patterns are prepared.
第１図でパターン１は基本形、パターン２．３は並列分
割形、パターン４，５は直列分割形、パターン６．７は
折り曲げ形である。In FIG. 1, pattern 1 is a basic type, pattern 2.3 is a parallel divided type, patterns 4 and 5 are a series divided type, and pattern 6.7 is a folded type.
次に、コンピュータを用い、回路図のマスクパターンを
形成しようとする抵抗に関する情報から、形状に関する
条件を抽出し、第２図（ａ）， （ｂ）のように類形に
応じて群分けした基本パターンの中で、この条件を満た
さないものを除外する。本例では「抵抗の折り曲げは不
可」の条件があるので、第２図（ａ）の中のグループ８
に含まれる基本パターンが除外される。Next, using a computer, conditions regarding the shape were extracted from the information regarding the resistors that were to form the mask pattern of the circuit diagram, and the conditions were grouped according to the type as shown in Figure 2 (a) and (b). Among the basic patterns, those that do not satisfy this condition are excluded. In this example, there is a condition that "resistance cannot be bent", so group 8 in Figure 2 (a)
Basic patterns included in are excluded.
また、半導体基板上で、第２図（ｂ）のような配置する
領域１１が設定されると、この領域に納まる形で目標抵
抗値を実現することが不可能な基本パターンを除外する
。目標抵抗値は、基本パターン１で抵抗パターンを作る
と、抵抗１２の形になり、これでは配置する領域１１を
はみ出すことになるので、第２図（ａ）中のグループ９
に含まれる基本パターンが除去される。Furthermore, once the region 11 for arrangement as shown in FIG. 2(b) is set on the semiconductor substrate, basic patterns that cannot achieve the target resistance value within this region are excluded. If the resistance pattern is made using basic pattern 1, the target resistance value will be in the form of resistor 12, which will extend beyond the area 11 where it is placed, so group 9 in FIG. 2(a) will be used.
The basic patterns contained in are removed.
そして、第２図（ａ）で残った基本パターンの中で生成
されるマスクパターンが最小になる基本パターンを選び
、生成する抵抗マスクパターンの概形をこの基本パター
ンに設定する。これにより、基本パターン４が選ばれる
。Then, from among the basic patterns remaining in FIG. 2(a), a basic pattern with which the mask pattern to be generated is the smallest is selected, and the outline of the resistive mask pattern to be generated is set to this basic pattern. As a result, basic pattern 4 is selected.
基本パターン４の形状を、ｆｉＩ域１１の形状に応して
その抵抗幅、長さを修正し、第２図（Ｃ）のように、最
終的な抵抗マスクパターン１３を得る。The shape of the basic pattern 4 is modified in its resistance width and length according to the shape of the fiI region 11 to obtain a final resistance mask pattern 13 as shown in FIG. 2(C).
基本パターンの選出の手順が上の例で示した手順と異な
っていても、最終的な抵抗マスクのパターンが得られる
ことは言うまでもない。It goes without saying that even if the procedure for selecting the basic pattern is different from the procedure shown in the above example, the final resistor mask pattern can be obtained.
発明の効果
本発明により、個々の抵抗のマスクパターンの形成を高
速かつ効率的に行うことができる。Effects of the Invention According to the present invention, mask patterns for individual resistors can be formed quickly and efficiently.
第１図はコンピュータ内に用意された抵抗の基本マスク
の平面パターン図、第２図（ａ）〜■は本発明の一実施
例を示す各平面パターン図である。
■・・・・・・基本パターン（基本形）２．３・・・・
・・基本パターン（並列分割形）、４．５・・・・・・
基本パターン〈直列分割形）、６．７・・・・・・基本
パターン（折り曲げ形〉、８・・・・・・抵抗折り曲げ
のある基本パターンのグループ、９・・・・・・領域１
１の中には目標抵抗値のマスクパターンの生成可能な嘩
本パターンのグループ、１０・・・・・・領・域ｌ１の
中に目標抵抗値のマスクパターン生成が可能な基本パタ
ーンのグループ、１ｌ・・・・・・抵抗を配置する領域
、１２・・・・・・領域１１と同一尺度で基本パターン
１の形状で示した、目標抵抗の形状、ｌ３・・・・・・
決定された抵抗のマスクパターン。FIG. 1 is a planar pattern diagram of a basic resistor mask prepared in a computer, and FIGS. 2(a) to (2) are planar pattern diagrams showing an embodiment of the present invention. ■・・・・・・Basic pattern (basic form) 2.3・・・・
...Basic pattern (parallel split type), 4.5...
Basic pattern (serial division type), 6.7...Basic pattern (folded type), 8...Group of basic patterns with resistance bending, 9...Area 1
1 is a group of basic patterns that can generate a mask pattern of the target resistance value, 10...A group of basic patterns that can generate a mask pattern of the target resistance value is in the region 11, 1l...Region where the resistor is placed, 12...Shape of the target resistor shown in the shape of basic pattern 1 on the same scale as area 11, l3...
Determined resistor mask pattern.
Claims (1)
ターンを、前もって基本パターンを複数個用意し、マス
クレイアウト上の要求に最も近い基本パターンを選び、
それを修正することで抵抗パターンを構成することを特
徴とする半導体抵抗形成方法。For the resistor pattern in the mask layout of a semiconductor integrated circuit device, prepare multiple basic patterns in advance, select the basic pattern that most closely matches the requirements on the mask layout,
A semiconductor resistor forming method characterized by configuring a resistor pattern by modifying the resistor pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1151910A JP2678064B2 (en) | 1989-06-14 | 1989-06-14 | Semiconductor resistance forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1151910A JP2678064B2 (en) | 1989-06-14 | 1989-06-14 | Semiconductor resistance forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0318052A true JPH0318052A (en) | 1991-01-25 |
| JP2678064B2 JP2678064B2 (en) | 1997-11-17 |
Family
ID=15528868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1151910A Expired - Lifetime JP2678064B2 (en) | 1989-06-14 | 1989-06-14 | Semiconductor resistance forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2678064B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007020439A1 (en) * | 2005-08-16 | 2007-02-22 | Pulsic Limited | Pattern matching and pattern replacement |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56158465A (en) * | 1980-05-09 | 1981-12-07 | Hitachi Ltd | Formation of resistance for integrated circuit |
| JPS61131068A (en) * | 1984-08-08 | 1986-06-18 | Hitachi Ltd | Forming method of layout of electronic circuit |
-
1989
- 1989-06-14 JP JP1151910A patent/JP2678064B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56158465A (en) * | 1980-05-09 | 1981-12-07 | Hitachi Ltd | Formation of resistance for integrated circuit |
| JPS61131068A (en) * | 1984-08-08 | 1986-06-18 | Hitachi Ltd | Forming method of layout of electronic circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007020439A1 (en) * | 2005-08-16 | 2007-02-22 | Pulsic Limited | Pattern matching and pattern replacement |
| US7657852B2 (en) | 2005-08-16 | 2010-02-02 | Pulsic Limited | System and technique of pattern matching and pattern replacement |
| US8490036B2 (en) | 2005-08-16 | 2013-07-16 | Pulsic Limited | System and technique of pattern matching and pattern replacement |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2678064B2 (en) | 1997-11-17 |
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