JP2677565B2 - Nonvolatile semiconductor memory device and control method thereof - Google Patents

Description

The present invention relates to a non-volatile semiconductor memory device using a rewritable memory cell having a floating gate and a control gate. (Prior Art) In the field of EPROM, an ultraviolet erasing nonvolatile memory device using a memory cell having a MOSFET structure having a floating gate is widely known. This EPROM memory array is configured by arranging memory cells at respective intersections of row lines and column lines intersecting with each other. On the actual pattern, the drains of the two memory cells are made common, and the cell line occupied area is made as small as possible by contacting the column lines. However, even in this case, a contact portion with the column line is required for each common drain of the two memory cells, and this contact portion occupies a large area of the cell. On the other hand, recently, EPROM, which enables NAND cells to be configured by connecting memory cells in series and greatly reducing the contact portion, was announced by R. Stewart of RCA (1984, VSLI Symposium Proceedings p.89-90
reference). In this EPROM memory cell, the coupling capacitance between the floating gate and the substrate is set to be larger than that between the floating gate and the control gate. If the charge injection into the floating gate is defined as “erasing” and the charge discharge from the floating is defined as “writing”,
This memory cell is erased by ultraviolet rays, and writing is performed by discharging the charge of the floating gate to the control gate side. An EPROM using such a NAND type cell has a smaller cell occupation area than a conventional general EPROM because a plurality of NAND memory cells need only be provided with one contact portion with a column line. Yes, but there is a problem in reliability.
That is, the floating gate and the control gate are formed as a laminated structure of a two-layer polycrystalline silicon film, and a thermal oxide film of a polycrystalline silicon film is used as an insulating film between them. Since the thermal oxide film of the polycrystalline silicon film is inferior in quality to the thermal oxide film of single crystal silicon, it is important to apply a large electric field between the floating gate and the control gate to exchange charges here. It causes characteristic deterioration. (Problems to be Solved by the Invention) As described above, the EPROM using the NAND type cell block proposed hitherto has a problem that it is not sufficiently reliable against electrical stress. An object of the present invention is to provide a nonvolatile semiconductor memory device which solves such a problem. [Structure of the Invention] (Means for Solving Problems) A nonvolatile semiconductor memory device of the present invention has a floating gate and a control gate stacked on a semiconductor substrate, and the coupling capacitance between the floating gate and the substrate is controlled by the floating gate. A plurality of rewritable memory cells connected in series set to be smaller than the coupling capacitance between the gates, one end of which is connected to one end of the plurality of memory cells connected in series and a bit line contact to the other end. It is characterized in that a NAND type cell block is constituted by a selection transistor to which a bit line is connected. (Operation) In the memory cell of the present invention, a large electric field is not applied between the control gate and the floating gate due to the coupling capacitance relationship of the gate portion. Therefore, the deterioration of the characteristics of the oxide film on the floating gate, which is inferior in film quality, is controlled, and the reliability of the EPROM is improved. Further, according to the present invention, a plurality of memory cells connected in series and a selection transistor having one end connected to one end of the plurality of memory cells connected in series and a bit line connected to the other end via a bit line contact are provided. By by NAND
Since the mold cell block is configured, the number of bit line contacts can be reduced, and the occupied area of the device as a whole can be reduced. Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing a NAND cell block according to one embodiment. FIGS. 2 (a) and 2 (b) show A-
FIG. 3 is a sectional view taken along line A 'and BB', and FIG. 3 is an equivalent circuit.
In one embodiment, four memory cells M _{1 to} M ₄ and one selection transistor Q are formed in one region of the silicon substrate 1 surrounded by the element isolation insulating film 2. Each memory cell has a floating gate 4 (41) formed of a first-layer polycrystalline silicon film via a first gate insulating film 3 made of a thermal oxide film on a substrate _1.
To 4 ₄₎ is formed through this second gate insulating film 5 made of thermally oxidized film on the control by the second-layer polycrystalline silicon film gate 6 ₍₆₁ through ₄₎ is formed, it is configured ing. Each memory cell control gate 6 is connected to the word lines WL _{1 to} WL ₄ , respectively. The n ⁺ -type layer 9 serving as the source and drain of each memory cell is adjacent to each other and shared by the two, and four memory cells M _{1 to} M ₄ are connected in series. The selection transistor Q is connected in series to this to constitute one NAND cell block. Gate electrode of select transistor Q
6 ₅ is patterned simultaneously with the control gate ₆₁ through ₄ by the second-layer polycrystalline silicon film. The whole is covered with a CVDS insulating film 7, and an Al wiring 8 which is in contact with the ⁺ type layer which is the drain n of the selection transistor Q is provided for the cell block. This Al wiring 8 is selectively connected to the input / output data line. As described above, the data line is connected via the select transistor Q to a plurality of memory cells, for example, a memory cell block having ^four memory cells M ^{1 to} M ⁴ as one unit. There is. In this configuration, the coupling capacitor C ₁ between the floating gate 4 and the substrate 1 in each memory cell is set smaller than the coupling capacitance C ₂ between the floating gate 4 control gate 6.
This will be described with reference to specific cell parameter examples. As shown in FIG. 1, the pattern size is 1 μm in width for both the floating gate and the control gate according to the 1 μm rule, and the channel width is 1 μm. Floating gate 4
Extend 1 μm each on both sides of the field region.
The first gate insulating film 3 is, for example, a thermal oxide film of 200 °,
The second gate insulating film 5 is a 350 ° thermal oxide film. If the dielectric constant of the thermal oxide film is ε, C ₁ = ε / 0.02 and C ₂ = 3ε / 0.035. That is, C ₁ <C ₂ . FIGS. 4 (a) to 4 (c) are waveform charts for explaining the operation of the NAND type cell block configured as described above. FIG. 4A shows a data write operation to the memory cells M ₂ and M ₃ . First, when writing to the memory cell M ₂ , Vp = "H" level is applied to the drain of the selection transistor Q and Data = to the gate.
The "H" level is applied to the word lines WL ₁ and WL ₂ .
The “H” level is, for example, 20V. At this time, Vp is transmitted to the drain region of the memory cell M ₃ through the select transistor Q and the channels of the memory cells M ₁ and M ₂ . Since the word line WL ₃ connected to the gate of the memory cell M ₃ has “L” level = 0V, a large electric field is applied between the control gate and the substrate in the memory M ₃ at this time. Since the coupling amount is C ₂ > C ₁ as described above, the electrons in the floating gate 4 are emitted to the substrate 1 by the tunnel effect. In the memory cells M ₁ and M ₂ , such a high voltage is applied to the control gate and the substrate, so that such electron emission does not occur. In memory cell M ₄ , both control gate and substrate are “L”
Since it is at the level, electron emission does not occur. Thus, the threshold voltage of the memory cell M ₃ is negative, the data is written. Then, as shown in Fig. 4 (a), Data
And when the "L" level WL ₂ keeping the WL ₁ to the "H" level, data writing in the memory cell M ₂ is performed on the same principle. FIG. 4B shows the waveform of the read operation. Data is "1", and (= 5V), the word lines WL ₁ to WL ₄ are the ones selected "0" = (0V). That is, when only WL ₁ is “0”, the memory cell M ₁ is selected, and when only WL ₄ is “0”, the memory cell M ₁ is selected.
₄ is selected. For example, when WL ₁ is “0” and the memory cell M ₁ is selected, since WL ₂ = WL ₃ = WL ₄ = “1”, the memory cells M _{2 to} M ₄ are in the ON state. Memory cells M ₁ is a threshold positive state off, the negative state is on. Therefore, whether or not a current flows in the cell block depends on the write state. As a result, "1" or "0" is obtained at the Vp terminal. As shown in FIG. 4 (b), WL _{1 to} W
If sequentially "0" to L _4, the information of the memory cell M ₁ ~M ₄ are sequentially read. FIG. 4 (c) shows a waveform at the time of batch erasing. The Data and WL ₁ to WL ₄ and the "H" level, Vp is the "L" level.
As a result, the channels become conductive in all the memory cells M _{1 to} M ₄ , and an electric field is applied between the substrate 1 and the floating gate 4, so that the substrate 1
From this, electrons are injected into the floating gate 4, and the threshold value moves in the positive direction. FIG. 5 shows the overall structure of the EPROM of the embodiment in which a plurality of NAND type cell blocks as described above are arranged to form a plurality of output bits. As shown in the figure, it is composed of a cell array unit 11 in which cell blocks Bij are arranged, an address buffer 12, a column decoder 13, and a row decoder 14. Word line W ₁₁
When erasing the memory cells of the cell blocks B ₁₁ , B ₁₂ , ... connected to W _1N to W _1N , set W ₁ , W _{11 to} W _1N to “H” level (= 2
0V) and then, a C ₁ to -C _M "H" level, the node N ₂ "H" level. As a result, electrons are injected into the floating gate by the above-described operation in all the memory cells connected to these word lines. Node N ₁ becomes to 0V, and when the next writing in the memory cell M _N of the cell block B _11, "H" level to C _1, C ₂ and -C _M "L" level, the W ₁ " H "level, W
Of _{11 to} W _1N , only W _1N is set to “L” level and the other is set to “H” level. As a result, only the memory cell _M1N emits electrons from the floating gate to the substrate, and the threshold value moves in the negative direction. To write to memory cell M ₁ , set C ₁ to “H” level, C ₂
The -C _M and "L" level, the W ₁ and W ₁₁ "H" level, W ₁₂
~ W _{1N is set} to "L" level. As a result, the memory cell M _1N
Only the electrons in the floating gate are emitted to the substrate, and the threshold value moves in the negative direction. As described above, according to this embodiment, the NAND cell
By using a block to write and erase information only by exchanging electrons between the floating gate and the substrate, a highly reliable high-density EPROM can be obtained. FIG. 6 shows a memory cell structure according to another embodiment of the present invention. Parts corresponding to those in the previous embodiment are denoted by the same reference numerals as in the previous embodiment, and detailed description is omitted. The second gate insulating film 5 on the floating gate 4 in this embodiment, the thermal oxide film 5 _1, the silicon nitride film 5 _2, and the composite structure of the thermal oxide film 5 _3. At this time, the first gate insulating film 3 is a thermal oxide film of, for example, 200 °, and the second gate insulating film 5 of the composite structure has a thickness of 200
Å. As a result, the coupling capacitance relationship satisfies C ₁ <C ₂ as in the previous embodiment. According to this embodiment, the same effect as that of the previous embodiment can be obtained. In the case of this embodiment, since the second gate insulating film has a composite structure, resistance of this portion to electric stress is improved, and high reliability is obtained. The present invention is not limited to the above embodiment, but can be implemented with various modifications without departing from the spirit thereof. [Effect of the Invention] As described above, according to the present invention, in a nonvolatile semiconductor memory device in which a rewritable memory cell having a floating gate is configured as a cell block having a NAND structure, a floating gate, a substrate, and a control gate are provided. The reliability of the non-volatile semiconductor memory device is improved by setting the coupling capacitance relationship between the two to be different from the conventional state and performing the writing and erasing only by exchanging charges between the floating gate and the substrate. . Further, according to the present invention, a plurality of memory cells connected in series and one end of the plurality of memory cells connected in series are connected to one end and a bit line is connected to the other end via a bit line contact. NA with transistor
Since the ND type cell block is configured, the number of hit line contacts can be reduced, and the occupied area of the entire device can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing a NAND type cell block according to an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are cross sections AA 'and BB' thereof. FIGS. 3 and 4 are equivalent circuit diagrams, FIGS. 4 (a) to 4 (c) are waveform diagrams for explaining the operation, and FIG. 5 shows an example of the overall configuration of an EPROM in which cell blocks are arranged. FIG. 6 and FIG. 6 are sectional views showing a memory cell of another embodiment. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation insulating film, 3 ... First gate insulating film, 4 ... Floating gate, 5 ... Second gate insulating film, 6 ... Control gate, 7 ... CVD insulating film , 8 ...
Output wiring, 9... N ⁺ type layer.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H01L 29/792 (72) Inventor Riichiro Shirata 1 Komukai Toshiba-cho, Kawasaki City, Kanagawa Prefecture Inside Toshiba Research Laboratory (72) Inventor Yoshihisa Iwata 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside Toshiba Research Laboratory (56) Reference JP 59-154067 (JP, A) JP 57- 180179 (JP, A) JP-A-57-39583 (JP, A)

Claims (1)

(57) [Claims] A plurality of rewritable memory cells connected in series in which a floating gate and a control gate are stacked on a semiconductor substrate and a coupling capacitance between the floating gate and the substrate is set smaller than a coupling capacitance between the floating gate and the control gate; A non-volatile semiconductor block characterized in that a NAND type cell block is constituted by a selection transistor having one end connected to one end of a plurality of memory cells connected in series and the other end connected to a bit line through a bit line contact. Memory device. 2. 2. The non-volatile semiconductor memory device according to claim 1, wherein writing / erasing is performed by injecting charges from the substrate into the floating gate or discharging charges from the floating gate to the substrate. . 3. The nonvolatile semiconductor memory according to claim 1, wherein an insulating film having a stacked structure of an oxide film / nitride film / oxide film is provided between the floating gate and the control gate. apparatus. 4. A plurality of rewritable memory cells connected in series in which a floating gate and a control gate are stacked on a semiconductor substrate and a coupling capacitance between the floating gate and the substrate is set smaller than a coupling capacitance between the floating gate and the control gate; A cell array section in which a plurality of NAND type cell blocks, each of which is configured by a select transistor having one end connected to one end of a plurality of memory cells connected in series and a bit line contact provided at the other end, and a cell array section arranged in the cell array section A plurality of bit lines connecting the other ends of the selected plurality of selected transistors in the column direction via the bit line contacts, and gates of the plurality of selected transistors arranged in the cell array portion. Connect in the row direction and connect the control gates of the plurality of memory cells arranged in the cell array section in the row direction. A plurality of word lines, a column decoder for selecting a desired bit line among the plurality of bit lines, and a row decoder for selecting a desired word line among the plurality of word lines. A non-volatile semiconductor memory device characterized by the above. 5. A plurality of rewritable memory cells connected in series in which a floating gate and a control gate are stacked on a semiconductor substrate and a coupling capacitance between the floating gate and the substrate is set smaller than a coupling capacitance between the floating gate and the control gate; A NAND-type cell block is configured by a select transistor having one end connected to one end of a plurality of memory cells connected in series and the other end connected to a bit line via a bit line contact,
The select transistor is turned on, and a signal of a voltage level at which the desired memory cell is turned off is supplied to the control gate of the desired memory cell among the plurality of directly connected memory cells, and By supplying the control gates of all the memory cells closer to the selection transistor than the memory cell with a signal of a voltage level at which all the memory cells closer to the selection transistor become conductive, the desired memory cell A method of controlling a non-volatile semiconductor memory device, which comprises selectively discharging charges from a floating gate to a substrate. 6. A plurality of rewritable memory cells connected in series in which a floating gate and a control gate are stacked on a semiconductor substrate and a coupling capacitance between the floating gate and the substrate is set smaller than a coupling capacitance between the floating gate and the control gate; A NAND-type cell block is configured by a select transistor having one end connected to one end of a plurality of memory cells connected in series and the other end connected to a bit line via a bit line contact,
The selection transistor is made conductive, and a signal of a predetermined voltage level is supplied to a control gate of a desired memory cell among the plurality of memory cells connected in series, and a control gate of a memory cell other than the desired memory cell. Is supplied with a signal of a voltage level at which a memory cell other than the desired memory cell becomes conductive, and the presence / absence of a current flowing through the plurality of memory cells connected in series based on the threshold value of the desired memory cell A method for controlling a non-volatile semiconductor memory device, comprising reading information stored in a desired memory cell. 7. A plurality of rewritable memory cells connected in series in which a floating gate and a control gate are stacked on a semiconductor substrate and a coupling capacitance between the floating gate and the substrate is set smaller than a coupling capacitance between the floating gate and the control gate; A NAND-type cell block is configured by a select transistor having one end connected to one end of a plurality of memory cells connected in series and the other end connected to a bit line via a bit line contact,
The selection transistor is made conductive, and a signal of a voltage level at which the plurality of memory cells connected in series is made conductive is supplied to each control gate of the plurality of memory cells connected in series, whereby the series connection is performed. A method of controlling a non-volatile semiconductor memory device, comprising injecting charges from a substrate into each floating gate of a plurality of stored memory cells.