JP2677562B2 - Multi-chip memory module - Google Patents

Description

The present invention relates to a multi-chip memory module in which a plurality of memory chips are mounted and sealed on a mounting board, and further to a defect relief technique for the memory chips therein, for example, The present invention relates to a technology effectively applied to a memory board or a memory card. [Prior Art] For a relatively small mounting board such as a printed wiring board,
COB consisting of multiple memory chips or memory pellets fixed, wire-bonded or wireless-bonded to a specified wiring pattern, and sealed with resin
In a multi-chip memory module such as a (chip-on-board) memory module, the individual memory chips included in the multi-chip memory module are simple and have not undergone a final screening test such as aging or burn-in. The yield of the entire module is significantly lower than the yield of each memory chip in proportion to the number of memory chips. That is, even if it is found later by a screening test that the memory chips included in the multi-chip memory module have a defect, the defective memory chips already sealed cannot be individually replaced. Therefore, conventionally, in order to improve the yield of the multi-chip memory module, it has been clarified that it is not defective after a screening test such as an electrical characteristic test and aging, and already individually packaged memory devices, for example, A method of mounting a memory element wirelessly bonded by PLCC (Plastic Leaded Chip Carrier) or tape carrier method on a mounting board was adopted. [Problems to be Solved by the Invention] In a characteristic test such as aging, an operation test is performed under conditions severer than rated operation in terms of voltage and atmosphere. It cannot be efficiently carried out in the state of various chips, so that the memory element which has undergone the characteristic test such as screening becomes large by the size of the package or tape carrier. In addition, a memory device that has undergone such a characteristic test becomes expensive due to the labor and package involved in the characteristic test. Therefore, when a multi-chip memory module is configured by mounting a plurality of memory elements that have been individually subjected to a characteristic test such as screening, the yield is relatively high, but the packaging density decreases due to the increase in the size of each memory element,
Further, the present inventors have clarified the problem that such a memory element itself is expensive, so that the cost is increased as a whole. An object of the present invention is to improve the yield and packaging density in a multi-chip memory module of the type that directly mounts a memory chip or memory pellet that has not undergone a characteristic test such as a screening test. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. [Means for Solving the Problems] The outline of typical inventions among the inventions disclosed in the present application will be briefly described as follows. That is, a mounting substrate for mounting a plurality of memory chips and encapsulating a multi-chip memory module is provided with mounting electrodes capable of mounting a defect relief memory element that can replace the memory chips, and the mounting electrodes are mounted on the mounting substrate. The defect relief memory element is connected to a wiring capable of performing selective trimming or selective connection, which can be selectively replaced with any of the memory chips. [Operation] According to the above means, when the memory chip has a defect by the screening test, the defect relief memory element is connected and arranged to the mounting electrode, and the wiring is trimmed or selectively connected. Functionally, by replacing defective memory chips with defect relief memory elements, the yield and packaging density are improved in a multi-chip memory module that directly mounts memory chips or memory pellets that have not undergone characteristic tests such as screening tests. Is achieved. [Embodiment] FIG. 1 is a circuit diagram showing a COB memory module which is an embodiment of a multi-chip memory module of the present invention. The COB memory module shown in FIG. 1 includes, but is not particularly limited to, eight pellet-shaped memory chips MC1 to MC8 that have not been subjected to screening. Although not particularly limited, each of the memory chips MC1 to MC8 is adhesively fixed to a mounting board ASSB such as a printed wiring board on which a predetermined pattern wiring such as a copper foil is formed in advance. The memory chips MC1 to MC8 are not particularly limited,
It is composed of a DRAM (dynamic random access memory) capable of inputting / outputting data bit by bit based on an i-bit address signal. The memory chips MC1 to MC8M are not limited to DRAM, and can be changed to various other memories such as SRAM (static random access memory) and ROM (read only memory). The data input / output electrodes of each of the memory chips MC1 to MC88 are not particularly limited, but have predetermined pattern wirings DL1 to D8.
The L8 is individually wire-bonded or wireless-bonded and individually connected to the external data input / output terminals D1 to D8. In addition, each memory chip MC1 to M
The address signal input electrode of C8 is not particularly limited,
The predetermined pattern wirings AL1 to ALi are commonly wire-bonded or wireless-bonded and commonly connected to the external address signal input terminals A1 to Ai. Further, the power supply electrodes of the memory chips MC1 to MC8 are wire-bonded or wireless-bonded to predetermined pattern wirings VDL and VSL and commonly connected to the external power supply terminals Vdd and Vss. Although not shown, each memory chip
The external control signal input electrodes in MC1 to MC8 are not particularly limited, but are wire-bonded or wireless-bonded to a predetermined pattern wiring and commonly connected to external terminals to which a chip enable signal, a write enable signal, etc. are supplied. . When the electrodes of the memory chips MC1 to MC8 are wirelessly bonded to a predetermined pattern wiring, a method of connecting the pads of the memory chip and the pattern wiring with bumps can be adopted. Each of the memory chips MC1 to MC8 is sealed with a resin or the like as shown by a chain double-dashed line after being connected to a predetermined pattern wiring. Although not particularly limited, the COB memory module of the present embodiment has a redundant configuration for relieving the defect if any one of the memory chips MC1 to MC8 has a defect. That is, the mounting substrate ASSB is provided with a set of mounting electrodes RDP capable of mounting one defect relief memory element that can replace the memory chips MC1 to MC8. This mounted electrode R
The DP is formed of, for example, a copper foil pattern according to the arrangement configuration of the external terminals of the relief memory element. As a memory element for relief, a memory element already packaged individually, such as a PLCC (Plastic Leaded Chip Carrier) memory, which has been found to be non-defective after undergoing a screening test such as an electrical characteristic test and aging The device may be a memory device wirelessly bonded by a device or a tape carrier method, a memory device having a flat package, or the like. These mounting electrodes RDP are connected to a predetermined pattern wiring so that the defect relief memory element can be selectively replaced with any of the memory chips MC1 to MC8. For example, according to the present embodiment, the mounting electrodes RDA1 to RDAi for address signal input are connected to the wiring patterns AL1 to ALi, and the mounting electrodes RDVD and RDVS for power supply input are the pattern wirings VDL, VS.
Connected to L. Data input / output electrodes RDDI, RDDO
Are connected to the redundant pattern wiring RDDL which is made non-conductive with the pattern wirings DL1 to DL8 and extends in the vicinity of the external data input / output terminals D1 to D8. Although not shown, various mounting electrodes for inputting control signals are also connected to predetermined pattern wirings on the mounting board ASSB. The pair of mounting electrodes RDP and redundant pattern wiring RDDL are mounted on the mounting board ASS.
It is formed in advance at the same time as the other pattern wiring of B. In the COB memory module of this embodiment, a screening test is performed after the memory chip mounted on the mounting substrate ASSB is electrically connected to a predetermined pattern wiring and sealed. As a result, when all of the memory chips MC1 to MC8 are not defective, they are finished as they are. For example, when a predetermined address signal is supplied to the external address signal input terminals A1 to Ai to access the COB memory module, 8-bit data can be input / output from the memory chips CM1 to CM8 according to the address signal. It If one of the memory chips MC1 to MC8 is defective as a result of the screening test, a PLCC memory element or the like for defect relief is mounted on the mounting electrode RDP, and the defective memory chip uses the defect relief memory element. Replace the function of. For example, if the memory chip MC8 is defective, first, a PLCC memory element or the like for defect relief is mounted and connected to the mounting electrode RDP. In that case, cream solder can be applied to each of the mounting electrodes RDP, the electrodes of the PLCC memory element can be placed on the cream solder, and melting connection can be performed by soldering by local heating. Then, the redundant pattern wiring
RDDL is connected to the pattern wiring DL8 by a jumper wire JL or the like, and the connection state between the defective memory chip CM8 and the external data input / output terminal D8 is cut at the position of X shown by C1 in FIG. For cutting the pattern wiring DL8, mechanical trimming or laser trimming can be adopted. Further, in order to reduce power consumption by cutting wasteful power supply to the defective memory chip MC8, in FIG.
The pattern wiring can be cut at the positions indicated by the crosses indicated by C2 and C3. Further, in order to reduce the undesired capacitance component in the pattern wiring for the address signal and the external control signal, the pattern wiring can be cut at the positions of x shown by C4, C5, C6 in FIG. 1, for example. . As a result, when one of the memory chips MC1 to MC8 is defective as a result of the screening test, the defective memory chip is replaced with the relief memory element, and the COB memory module itself does not become defective. According to the above embodiment, the following operation and effect can be obtained. (1) Memory chips that have not been individually screened
The mounting substrate ASSB on which MC1 to MC8 are mounted and sealed is provided with a set of mounting electrodes RDP capable of mounting a defect relief memory element that can substitute for the memory chip, and these mounting electrodes RDP are defect repaired. When the memory element for use has a defect in one of the memory chips by the screening test, the memory element for use in the memory is selectively and alternately connected to a predetermined pattern wiring.
A defect relief memory element can be mounted on the mounting electrode RDP, and the defect memory element can be replaced with the defect relief memory element. Therefore, it is possible to remarkably improve the yield in the multi-chip memory module of the type in which the memory chips or the memory pellets which are not subjected to the characteristic test such as the screening test are directly mounted. For example, if the yield of one memory chip is 92%, the yield of the COB memory module of this embodiment can be maintained at about 92%. On the other hand, in the case of not having the redundant configuration as in the present embodiment, the yield of the COB memory module including eight memory chips is extremely low as about 47% [(0.92) ⁸ ]. (2) From the above-described effects, since the majority of memory chips in a pellet state occupy all of them through a screening test such as an electrical characteristic test and an aging, it is clarified that the memory chips are already individually packaged. The packaging density can be improved as compared with a memory module including an element, for example, a PLCC (Plastic Leaded Chip Carrier) memory element or a memory element wirelessly bonded by a tape carrier method. As in this embodiment, the redundant configuration is set to 1
The yield is about 1 if only one memory chip is provided.
Since the yield can be made equal to that of the individual pieces, the packaging density can be maximized in the case of such a configuration. The invention made by the present inventor has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. . For example, in the above-described embodiment, the redundancy configuration for one memory chip is provided and the improvement of the mounting density is relatively emphasized.
If the highest priority is to improve the yield, a plurality of redundant configurations may be provided. Further, the defect relief memory element may be a pellet-shaped memory chip that is screened by a special device. Further, the cutting or connecting work of the predetermined pattern wiring for substituting the function of the defective memory chip with the defective relief memory element is not limited to the trimming or the connection by the jumper line as in the above-mentioned embodiment, and various methods are adopted. can do. Further, in the above embodiment, the COB memory module of the type in which the address signal and the external control signal are commonly supplied to the respective memory chips and the respective memory chips are simultaneously accessed has been described, but the present invention is not limited thereto. Instead, it is possible to have a format in which an address decoder is provided inside and a predetermined memory chip is selectively operated based on the decoding result by the decoder. In the above description, the case where the invention made by the present inventor is mainly applied to the COB memory module which is the field of application which is the background has been described, but the present invention is not limited thereto, and a memory card or a memory board is used. Further, it can be applied to various multi-chip memory modules such as a system board including a plurality of memory chips. The present invention can be applied to a condition including at least a plurality of memory chips. [Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a multi-chip memory module of a type in which a memory chip or a memory pellet that is not subjected to a characteristic test such as a screening test is directly mounted by having a redundant configuration for substituting the function of the defective memory chip with a relief memory element. The yield and the packaging density can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a COB memory module which is an embodiment of a multi-chip memory module of the present invention. ASSB ... Mounting board, MC1 to MC8 ... Memory chips, D1 to D8
External data input / output terminals, A1 to Ai ... External address signal input terminals, Vdd and Vss ... External power supply terminals, AK1 to ALi, DL1
To DL8, VDL, VSL, RDDL ... pattern wiring, RDP ... mounting electrode, JL ... jumper wire, C1 to C6 ... trimming position.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Masayuki Watanabe               3681 Hayano, Mobara-shi, Chiba Hitachi, Ltd.               Su Engineering Co., Ltd.                (56) References JP-A-61-288244 (JP, A)

Claims (1)

(57) [Claims] A plurality of memory chips are mounted on the mounting board, and the plurality of memory chips are common to each memory chip through the wiring formed on the mounting board, the external data input / output terminals unique to each memory chip. A multi-chip memory module that is connected to other external terminals of the multi-chip memory module so that the plurality of memory chips can be accessed in parallel through the external data input / output terminals and the external terminals. When a part of the chip has a defect, a mounting electrode on which a memory element having the same function as that of the memory chip and for replacing the defective memory chip is mounted, and data input / output of the memory element mounted on the mounting electrode A redundant pad that extends the mounting electrodes corresponding to the electrodes to the vicinity of the external data input / output terminals in a state of being electrically non-conducting with the external data input / output terminals. Turn wirings are provided in advance on the mounting substrate, and mounting electrodes corresponding to other electrodes of the memory element are pre-connected to the corresponding external terminals, and the mounting electrodes correspond to the memory element. When mounting the defective memory chip, the wiring connecting the defective memory chip to its own external data input / output terminal is cut, and the external data input / output terminal specific to the defective memory chip is jumpered with the redundant pattern. A multi-chip memory module in which a defective memory chip is replaced with a memory element by connecting to a wiring.