JPH10116958A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mount memory chips on a printed circuit board with a high mounting density. SOLUTION: A plurality of bare chips 1 for memory are cut out from continuous regions of a semiconductor wafer, and then closely contacted with a printed circuit board 2 without being packaged. When the chips 1 are cut out from the semiconductor wafer, preliminary bare chips 1 are also cut out together with primary bare chips 1, so that, even if one of the chip 1 is faulty, the entire system of such memory chips 1 can normally operate. Thereby, the chips can be mounted at a high density and a percent defective at the time of manufacturing the memory system can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory system in which a plurality of memory chips are mounted on a printed wiring board.

[0002]

2. Description of the Related Art In portable devices such as cellular phones and electronic organizers, miniaturization of products and reduction of power consumption are important factors influencing product sales. For this reason, conventionally, the number of components to be mounted has been reduced by using a multifunctional LSI, and the size has been reduced by mounting both sides on a multilayer printed wiring board. It has also been generalized to improve the mounting density by so-called flip-chip mounting in which a bare chip from which an LSI package is removed is directly mounted on a printed wiring board.

By the way, most electronic devices such as portable devices include a CPU therein, and the performance of a product is often determined by a failure of a program for operating the CPU. In addition, the amount of programs has become enormous along with the diversification of functions, and a desired processing speed cannot be obtained unless a large amount of memory is mounted.

[0004]

However, when a large amount of memory is mounted on a printed wiring board, there is a problem that the printed wiring board becomes large. For this reason, in electronic devices such as computers that require a large amount of memory, it is necessary to mount a SIMM (Single In-line Memory Module) in which multiple memory chips are mounted on a small printed circuit board vertically or diagonally to the main board. General. However, since the SIMM uses a commercially available memory chip as a component, there is a limit in reducing the outer dimensions of the SIMM, and the main substrate must be increased according to the outer dimensions of the SIMM and the number of SIMMs to be mounted.

The present invention has been made in view of the above points, and an object of the present invention is to provide a memory system capable of mounting a memory chip on a printed wiring board at a high density.

[0006]

According to a first aspect of the present invention, there is provided a memory system comprising: a plurality of memory chips formed in a continuous area on a semiconductor wafer; Is mounted on a printed wiring board in a state of being closely adhered without being divided one by one.
As a result, the mounting area on the printed wiring board can be reduced, and high-density mounting becomes possible.

According to a second aspect of the present invention, the input / output pads of the memory chip and the pads of the printed wiring board are connected by bonding wires.

According to a third aspect of the present invention, the memory chip has a rectangular shape, and input / output pads of the memory chip are formed along two of the four sides constituting the rectangle. By making the shape rectangular, more memory chips can be formed on the semiconductor wafer, and by forming the input / output pads along two sides, it becomes easier to connect by bonding wires.

According to the present invention, since an extra memory chip is mounted on the printed wiring board, even if some of the memory chips become defective, the entire memory system does not have to be treated as defective. In addition, the defective rate at the time of manufacturing the memory system is reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory system to which the present invention is applied will be specifically described with reference to the drawings.

FIG. 1 is a plan view schematically showing a memory system according to this embodiment, and FIG. 2 is an enlarged view showing a part of the memory system. As shown in FIG. 1, the memory system according to the present embodiment mounts a memory bare chip 1 formed on a semiconductor wafer on a printed wiring board 2 without packaging. One end side P of the printed wiring board 2 is processed into a shape attachable to a connector on a main board (not shown), and a plurality of patterns 3 for conducting with the connector on the main board are formed in this portion. I have. As shown in FIG. 2, each of these patterns 3 is connected to a pad 4 on the printed wiring board 2 and an input / output pad 6 of the memory bare chip 1 through a bonding wire 5.
Is connected to

FIG. 3 is a plan view schematically showing the memory bare chip 1 formed on the semiconductor wafer 7. As shown in the figure, each of the memory bare chips 1 is formed in a substantially rectangular shape, and input / output pads 6 for external connection are formed along two opposing outer edges. Normally, each of the rectangular memory bare chips 1 is individually packaged, but in the present embodiment, these memory bare chips 1 are mounted on the printed wiring board 2 without packaging. I do.

FIG. 4 is a diagram for explaining the signal content of the input / output pad 6 of the memory bare chip 1, and shows an example of a 1M × 4 bit DRAM. In the figure, A0 to A9
Is an address terminal, I / O1 to I / O4 are data terminals, W
E indicates a write enable terminal, and OE indicates an output enable terminal.

FIG. 5 is a diagram showing a block configuration inside the memory bare chip 1. As shown in FIG. As shown in FIG. 1, a memory bare chip 1 includes an address buffer 11 to which address terminals A0 to A9 are connected, a decoder 12 for decoding an input address, and a clock generator 13 for controlling the address buffer 11 and the decoder 12. , A RAM cell 14, a gate 15, and an I / O buffer 16.

A memory bare chip 2 having a structure shown in detail in FIGS. 4 and 5 is formed on a semiconductor wafer 7 in close contact therewith. When the memory bare chip 1 is cut from the semiconductor wafer 7, the semiconductor wafer 7 A plurality of memory bare chips 1 formed in the upper continuous area are cut out. The input / output pads 6 of the memory bare chip 1 are cut out so as to be arranged in two rows as shown in FIG. When cut out in this manner, the mounting direction and the mounting interval of the bonding wires 5 when mounted on the printed wiring board 2 become constant, so that the connection of the bonding wires 5 becomes easy. However, the vicinity of the outer periphery of the semiconductor wafer 7 may not be cut out in the direction shown in FIG. 3, and in such a case, it may be cut out as shown in FIG.

A plurality of memory bare chips 1 cut out from a semiconductor wafer 7 are printed on a printed wiring board 2 by COB (Chip).
On Board) Implemented. That is, each of the input / output pads 6 of each memory bare chip 1 is connected to the pads 4 on the printed wiring board 2 by bonding wires 5 as shown in FIG.

FIG. 1 shows an example in which nine memory bare chips 1 formed on a semiconductor wafer 7 are mounted on a printed wiring board 2. One of the nine bare chips 1 (FIG. The hatched portion) is used as a spare. Thereby, even if one of the eight memory bare chips 1 except the spare memory bare chip 1 is defective, the memory system operates normally by using the spare memory bare chip 1 instead. . That is, even if some of the memory bare chips 1 are defective, it is not necessary to treat the entire memory system as defective, so that the defective rate at the time of manufacturing the memory system can be reduced.

If any of the memory bare chips 1 other than the spare memory bare chip 1 is defective, for example, the connection of a jumper wire (not shown) on the printed wiring board 2 is switched so that the memory bare chip 1 is not used. The bare chip 1 may be switched. If the memory bare chips 1 located near the center of the nine memory bare chips 1 arranged in a line are used as spares, the switching of the memory bare chips 1 is facilitated, which is convenient.

In the example of FIG. 1, nine memory bare chips 1 are mounted on a printed wiring board 2, and eight of the memory bare chips 1 are substantially used. In the case of a × 4 bit DRAM, the memory capacity of the entire memory system is 4 Mbytes in a 32-bit configuration.

As described above, in the memory system according to the present embodiment, the memory bare chips 1 formed on the semiconductor wafer 7 are cut out into a plurality of sets without being individually separated and mounted on the printed wiring board 1 as they are. Therefore, it is possible to mount the memory at a much higher density than when mounting a packaged memory. This is particularly effective when a large amount of memory is consumed, such as in computer equipment. Also, since it is not necessary to package each memory bare chip 1, the cost of parts can be reduced. In addition, since the spare memory bare chip 1 is provided in the memory system, even if some of the memory bare chips are defective, the entire memory system does not need to be treated as defective, and the defective rate at the time of manufacturing the memory system is reduced.

In FIGS. 1 to 5, an example in which a 4-bit memory bare chip is used has been described. However, the bit configuration of the memory bare chip used is not limited to 4 bits and may be 1 bit or 8 bits. Further, the bit configuration of the memory system is not limited to the 32-bit configuration, but may be, for example, an 8-bit configuration or a 16-bit configuration.

FIG. 1 shows an example in which only one set of nine memory bare chips is mounted on the printed wiring board 2, but a plurality of sets of memory bare chips 1 are mounted on the printed wiring board 2. May be. For example, FIG. 7 shows a memory bare chip 1 having five chips (one of the five chips is a spare).
Is shown on the printed wiring board 2 as a set, and also in this case, as in FIG.
A memory system having a memory capacity of bytes can be obtained.

Further, instead of mounting a plurality of memory bare chips 1 cut out from the semiconductor wafer 7 in close contact with each other and mounting them on the printed wiring board 2, each memory bare chip 1 is individually cut out and mounted as shown in FIG. May be. In this manner, the memory bare chips 1 individually cut out are
Even in the case of B mounting, the process can be simplified and the mounting area can be reduced as compared with the case where a packaged memory chip is mounted.

FIGS. 1 to 8 show an example in which the memory bare chip 1 cut out from the semiconductor wafer 7 and the pads 4 on the printed wiring board 2 are COB-mounted by the bonding wires 5. Flip chip mounting for directly attaching the output pad 6 to the printed wiring board 2 may be performed. When flip-chip mounting is performed, higher-density mounting becomes possible than COB mounting using the bonding wires 5.

FIGS. 1 to 8 show an example of a memory system having a SIMM structure.
A structure that can be attached to an expansion slot such as a personal computer) may be used. For example, FIG. 9 is a diagram showing an example of a memory system having the same outer shape as a memory board that can be attached to an expansion slot of a personal computer. As shown in FIG.
Are mounted on the printed circuit board 2 by COB mounting or flip chip mounting. A connector 21 for exchanging signals with a personal computer is mounted on the printed wiring board 2, and each terminal in the connector 21 is electrically connected to the corresponding input / output pad 6 of the memory bare chip 1.

As described above, when the memory bare chip is mounted on the memory board 20, the memory capacity can be remarkably increased as compared with the conventional memory board.

In the above-described embodiment, an example has been described in which one spare memory bear chip 1 is provided in a plurality of memory bear chips 1 forming a set. However, two or more spare memory bear chips 1 are provided. You may. Further, the spare memory bare chip 1 may not be provided at all. Further, the spare memory bare chip 1 may not be provided at all.

Further, in the above-described embodiment, after a plurality of memory bare chips 1 are mounted on the printed wiring board 2 by COB mounting or flip chip mounting, the memory bare chips 1 may be covered with a protective member such as epoxy. Thereby, the occurrence of defects such as disconnection of the bonding wire 5 and solder cracks can be prevented.

[0029]

As described in detail above, according to the present invention, a plurality of sets of memory chips formed on a semiconductor wafer 7 are cut out and printed in a state of being closely attached without packaging. Since it is mounted on a board, high-density mounting is possible as compared with a conventional case of mounting a packaged memory.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a memory system.

FIG. 2 is an enlarged view of a part of the memory system.

FIG. 3 is a view schematically showing a memory bare chip formed on a semiconductor wafer.

FIG. 4 is a diagram illustrating signal contents of input / output pads of a memory bare chip.

FIG. 5 is a diagram showing a block configuration inside a memory bare chip.

FIG. 6 is a view schematically showing a memory bare chip formed on a semiconductor wafer.

FIG. 7 is a diagram showing an example in which five sets of memory bare chips are mounted on a printed wiring board by COB.

FIG. 8 is a diagram showing an example in which each bare chip for memory is individually cut out and mounted.

FIG. 9 is a diagram showing a memory system applied to a memory board that can be attached to an expansion slot of a personal computer.

[Explanation of symbols]

 Reference Signs List 1 bare chip for memory 2 printed wiring board 3 pattern 4 pad 5 bonding wire 6 input / output pad 7 semiconductor wafer

Claims (4)

[Claims] 1. A memory system wherein a plurality of memory chips formed in a continuous area on a semiconductor wafer are mounted on a printed wiring board in close contact with each other. 2. The memory chip according to claim 1, wherein each of the memory chips includes a plurality of input / output pads, and a plurality of pads is formed on the printed wiring board, and the pads correspond to the input / output pads corresponding to the memory chips. A memory system, wherein an output pad is connected with a bonding wire. 3. The memory chip according to claim 1, wherein the memory chip is formed in a rectangular shape on the semiconductor wafer, and the input / output pad is formed along two of four sides constituting the rectangle. A memory system characterized by the above-mentioned. 4. The memory chip according to claim 1, wherein a part of the plurality of memory chips mounted on the printed wiring board is usable only when another memory chip is defective. A memory system, characterized in that: