JP2006332360A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method wherein it is attempted to simplify a process to reliably exclude a malfunction with a wafer process. <P>SOLUTION: An insulating board 5 is mounted on a base plate 3 made of metal by soldering, and a semiconductor chip 7 containing a plurality of diode chips 7a and transistor chips 7b is mounted on the insulating board 5. The semiconductor chip 7 is extracted by dividing a plurality of diodes formed as elements as a matrix-like element group of 1 row × 4 columns. Of the elements formed on the semiconductor chip 7, the elements which are determined as acceptable products are electrically connected to each other by a bonding wire 13. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a power semiconductor device to which a SiC wafer is applied and a manufacturing method thereof.

  In recent years, semiconductor devices have become increasingly sophisticated and diversified, and products using the semiconductor devices have been put into practical use in various fields. The function of a semiconductor chip, which is the main part of a semiconductor device, is realized by performing fine processing on a semiconductor material such as Si or GaAs. In order to achieve high performance of the semiconductor device, advanced processing technology is increasingly required.

  Under such circumstances, a new power semiconductor material made of SiC has recently been developed as one of the materials for semiconductor devices, and it has been used for power with unprecedented high breakdown voltage, high heat resistance, and low loss. Realization of a semiconductor device is expected.

  The advanced processing technology required for the production of semiconductor chips makes the production of semiconductor chips more difficult, and is accompanied by a deterioration in yield in which good chips can be obtained from a wafer. Furthermore, since materials such as SiC applied as a wafer have a high defect density, they already contain potentially defective portions before being put into processing. Therefore, in such materials as SiC, the yield of the semiconductor chip is further deteriorated due to the difficulty of processing in addition to potentially having a defective portion, and the cost of the semiconductor chip is reduced. There was a problem of rising.

  As one of techniques for solving such problems, there is a semiconductor device described in Patent Document 1, for example. In this semiconductor device, a plurality of power units are formed on a wafer, and an electrode layer of a predetermined element such as a diode is formed in each of the units. Further, the electrode layer is connected to the outside. An aluminum wiring layer is formed.

  Among the plurality of units, in the electrode layer located in the defective unit, an insulating layer is formed on the electrode layer so as not to be electrically connected to the aluminum wiring layer. This insulating layer is formed as follows. First, a resist is applied on a wafer on which the wafer process of the power unit has been completed. Next, exposure processing is performed by the exposure apparatus based on the data of the defective unit stored in advance, so that the resist portion located in the defective unit is left as an insulating layer.

In this manner, in this semiconductor device, the resist mask for originally forming the through hole of the electrode layer is used as the insulating layer, so that the electrical connection between the electrode layer of the defective unit and the aluminum wiring layer can be performed without forming the insulating layer separately. Insulative insulation.
JP 2004-111759 A

  However, the conventional semiconductor device has the following problems. That is, in order to cover the electrode layer located in the defective unit with the insulating layer, a series of wafer processes such as applying a resist on the wafer, performing an exposure process, and performing a development process must be performed. There was a problem that became complicated.

  A wafer process for forming an aluminum wiring layer is also required, and a unit that was initially determined to be a good product due to such a wafer process for forming an insulating layer or an aluminum wiring layer becomes a defective unit. As a result, there was a risk that the number of non-defective semiconductor chips could be reduced.

  The present invention has been made to solve the above-mentioned problems, and its object is to provide a semiconductor device that simplifies the process and reliably eliminates defects associated with the wafer process. Is to provide a method of manufacturing such a semiconductor device.

  The semiconductor device according to the present invention includes a plurality of semiconductor chips and a conductive member. The plurality of semiconductor chips are disposed on the main surface of the insulating substrate. The conductive member electrically connects the plurality of semiconductor chips to each other. Each of the plurality of semiconductor chips includes an element group including a plurality of elements having the same function on a predetermined predetermined substrate portion and formed in a matrix. The conductive member is a conductive wire that electrically connects elements determined to be non-defective in the element group.

  A manufacturing method of a semiconductor device according to the present invention includes the following steps. A plurality of elements having the same function are formed on a wafer containing silicon carbide as a main component. The function of each of a plurality of elements is tested to select a non-defective element and a defective element. The wafer is divided into semiconductor chips each including a group of elements each having a predetermined number of elements. Each of the divided semiconductor chips is disposed on the surface of a predetermined insulating substrate. Non-defective elements in the semiconductor chip are electrically connected by a conductive wire.

  According to the semiconductor device of the present invention, a plurality of elements having the same function formed on a predetermined substrate are taken out from the substrate as an element group including a predetermined number of elements including elements determined to be defective. A semiconductor chip is disposed on the insulating substrate. As a result, compared with the case where only the semiconductor chips determined as non-defective products are individually taken out from the plurality of elements and disposed on the insulating substrate, the positional deviation between the semiconductor chips during assembly occurs. It is difficult to reduce problems associated with the positional deviation between the semiconductor chips. Further, as compared with the conventional semiconductor device, the defects determined in the wafer process can be eliminated by electrically connecting the elements determined to be non-defective products by wire bonding. As a result, it is possible to reliably prevent an element determined as a non-defective element from becoming a defective product due to such a defect caused by the wafer process.

  According to the method of manufacturing a semiconductor device according to the present invention, a plurality of elements having the same function formed on a predetermined substrate, as an element group including a predetermined number of elements including elements determined to be defective. The semiconductor chip is disposed on an insulating substrate as a semiconductor chip. Thereby, compared with the conventional case, it is hard to produce the position shift of semiconductor chips at the time of an assembly, and the malfunction accompanying the position shift of semiconductor chips can be reduced. In addition, by electrically connecting elements determined to be non-defective by wire bonding, defects associated with the wafer process can be eliminated as compared with the case of electrically connecting by a wafer process. It is possible to prevent the element determined to be a defective product due to a defect caused by such a wafer process.

Embodiment 1
A power semiconductor device for power conversion will be described as the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, an insulating substrate 5 is mounted on a base plate 3 made of metal by soldering, and a semiconductor including a plurality of diode chips 7a and transistor chips 7b by soldering on the insulating substrate 5. Chip 7 is mounted. As will be described later, among the elements formed on the semiconductor chip 7, elements determined to be non-defective are electrically connected to each other by bonding wires 13.

  A metal bus bar 9 is disposed on the base plate 3, and a part of the metal bus bar 9 is connected to the semiconductor chip 7 and the insulating substrate 5 by bonding wires 13. The semiconductor chip 7 and the metal bus bar 9 mounted on the insulating substrate 5 are accommodated in a resin case 11. The resin case 11 is filled with a gel 15 and a lid 17 is attached so as to cover the gel 15.

  Next, the semiconductor chip 7 applied to the semiconductor device 1 will be described in detail. Generally, in order to control a large current in a power semiconductor device, a semiconductor chip having a relatively large occupied area is required as a semiconductor chip. However, as described above, since the SiC wafer includes a potential defective portion, as shown in FIG. 2, the size per semiconductor chip formed on the SiC wafer, that is, the larger the occupied area, The probability that a defective part exists in the region of one semiconductor chip increases, and the yield as a semiconductor chip decreases.

  On the other hand, by reducing the area per semiconductor chip, the probability that a defective portion exists in the region of one semiconductor chip is reduced, and the yield as a semiconductor chip is improved. That is, assuming that the number of defective portions included in the SiC wafer is the same, the smaller the area of one semiconductor chip, the higher the yield as a semiconductor chip.

  If such a semiconductor chip with a relatively small area is applied to control a large current, the number of semiconductor chips determined to be non-defective products by the number corresponding to a predetermined area sufficient to control the large current. Must be disposed on the insulating substrate.

  However, in order to dispose many semiconductor chips on one insulating substrate, it is difficult to individually secure the positional accuracy of the semiconductor chips. In addition, if soldering is performed while ensuring the positional accuracy of individual semiconductor chips, it is necessary to maintain the interval between adjacent semiconductor chips at a predetermined interval, which increases the area of the region where the semiconductor chips are disposed. become. Furthermore, if many semiconductor chips are individually arranged on the insulating substrate, the number of steps increases and the assembly cost increases.

  Therefore, in order to solve such a problem, this semiconductor device 1 is not a method of individually taking out only semiconductor chips determined to be non-defective from a plurality of elements having the same function formed on the SiC wafer. A semiconductor chip taken out as an element group consisting of a predetermined number of elements including elements determined to be defective is applied. More specifically, as shown in FIG. 3 and FIG. 4, a semiconductor chip 7 in which a plurality of diodes formed as elements are divided and taken out as a matrix element group 8 of 1 row × 4 columns is applied. ing.

  When the number of defective elements among the four elements constituting one semiconductor chip 7 is 1, the mode (pattern) in which the defective element 88b is located in the element group 8 is shown in FIGS. As indicated by the crosses in 4, there are two ways. On the other hand, in the semiconductor device in which the number of defective elements among the four elements is 2 or more, the probability of occurrence is very low and the combination with other semiconductor chips becomes complicated. Not applied.

  Whether each element in the semiconductor chip is good or bad is determined at the time of a wafer test or a chip test, and a predetermined bad mark (x mark) is given to the element 88b that is determined as a defective product. The element 88a is not marked. Moreover, if a bad mark can be recognized, it will not be restricted to x mark.

  In the present semiconductor device 1, as shown in FIGS. 5 and 6, an element group 8 in which one of the four elements is determined as a defective product is defined as one semiconductor chip 7, and such semiconductor chip 7 Are provided on the insulating substrate 5 so as to secure a predetermined area required for controlling a large current. At this time, as the semiconductor chip, as shown in FIG. 3, the semiconductor chip 7 in which the defective element 88b is located at the left end as shown in FIG. 3, and the semiconductor in which the defective element is inverted by 180 ° and the defective element is located in the right end. As shown in FIG. 4, the semiconductor chip 7 in which the defective element 88b is located second from the left end as shown in FIG. 4, and the semiconductor in which the defective element is located second from the right end by reversing the semiconductor chip by 180 ° The chip is disposed on the insulating substrate 5.

  That is, as shown in FIG. 5, the semiconductor chip 7 is disposed on the insulating substrate 5 in the state shown in FIG. 3 and FIG. 4, and the state shown in FIG. 3 and FIG. It is arranged in the state. In particular, in this case, the defective element 88b is arranged on a diagonal line.

  As described above, in the semiconductor device 1, based on the positions of the elements determined to be defective in the element group, the semiconductor chip is formed on the insulating substrate 5 so that the positional relationship of the elements determined as non-defective is the same for each semiconductor device. 7 is disposed.

  In the semiconductor chip 7, a diode is formed as an element. Structurally, as shown in FIG. 6, an epitaxial layer 22 is formed on a SiC substrate (n-type semiconductor). A p-type layer 23 is formed on the surface of the epitaxial layer 22, and adjacent elements are electrically insulated. An electrode layer 25 is formed on the epitaxial layer 22 with a barrier metal 24 interposed. A protective film 26 is formed so as to expose the surface of the electrode layer 25. The bonding wire 13 is bonded to the element 88a determined to be non-defective among the element group constituting each semiconductor chip 7 provided.

  At this time, as shown in FIG. 5, the elements 88a determined to be non-defective products positioned in the first row are bonded to each other by the bonding wires 13a, and the elements 88a determined to be non-defective products positioned to the second row are bonded to the bonding wires 13b. Therefore, the elements 88a determined to be non-defective products located in the third row are electrically connected to each other by the bonding wire 13c, and the elements 88a determined to be non-defective products located in the fourth row are electrically connected to each other by the bonding wire 13d. Is done.

  In this way, in the semiconductor device 1, the element 88b determined to be defective in each semiconductor chip 7 is removed, and the element 88a determined to be non-defective is electrically connected in parallel to be predetermined as an element for controlling a large current. Area is secured.

  In the semiconductor device described above, in a plurality of elements having the same function formed on the SiC wafer, a semiconductor chip taken out from the SiC wafer as an element group including a predetermined number of elements including elements determined to be defective is included. It is disposed on an insulating substrate. Thereby, only the semiconductor chips determined to be non-defective from the plurality of elements formed on the SiC wafer are individually taken out, and compared with the case where these are arranged on the insulating substrate, the semiconductor chip at the time of assembly Misalignment between each other is unlikely to occur, and problems associated with misalignment between semiconductor chips can be reduced.

  Further, a general wire bonding apparatus is provided by disposing individual semiconductor chips so that the positions of elements determined as non-defective elements among the element groups constituting the semiconductor chips are predetermined positions for each semiconductor device. It is possible to easily electrically connect elements determined to be non-defective using

  Then, an insulating film is formed on the element determined to be defective by the wafer process, and compared to a conventional semiconductor device in which elements determined to be non-defective are electrically connected to each other by aluminum wiring, it is determined to be non-defective. By electrically connecting the elements to each other by wire bonding, it is possible to eliminate problems associated with the wafer process. As a result, it is possible to reliably prevent an element determined as a non-defective element from becoming a defective product due to such a defect caused by the wafer process.

  In particular, in a diode as an element to which an SiC wafer is applied, a higher withstand voltage is obtained and a loss is higher and higher heat resistance is obtained as compared with a diode to which an Si wafer is applied.

  In the semiconductor device described above, a 1 × 4 matrix element group has been described as an example of an element group constituting a semiconductor chip. However, the number of rows and the number of columns are not limited thereto. . In addition, as an example of the element group, the case where one element determined to be defective is included has been described as an example. You may apply the semiconductor chip which consists of an element group containing a good product. Even in this case, by arranging the semiconductor chips so that the positions of the elements determined to be non-defective are the same for each semiconductor device, the elements determined to be non-defective are easily electrically connected by wire bonding. can do.

Embodiment 2
In the above-described semiconductor device, the element group constituting the semiconductor chip has been described by taking a matrix element group of 1 row × 4 columns as an example. Here, a description will be given by taking a matrix element group of 4 rows × 4 columns as an example.

  In this semiconductor device, as shown in FIG. 7 and FIG. 8, a semiconductor chip 7 is used in which the elements formed on the SiC wafer are divided and taken out as a matrix element group 8 of 4 rows × 4 columns. . In the semiconductor chip 7, the element 88b determined to be defective is randomly located in the element group. Elements 88a determined to be non-defective products are electrically connected to each column by bonding wires 13 (13a, 13b, 13c, 13d). In particular, in this semiconductor chip 7, it is preferable that a bad mark (x mark) is attached to the element 88b determined to be defective. Since the structure other than this is the same as the structure of the semiconductor device described above, the same members are denoted by the same reference numerals and the description thereof is omitted.

  When bonding wires, information on the position of the element determined to be defective in the semiconductor chip and information on the position of the semiconductor chip on the insulating substrate are removed and the non-defective element is removed. A wire can be bonded only to the determined element.

  Further, when wire bonding is performed, a bad mark attached to an element is recognized as an image, so that an element determined to be defective can be removed and a wire can be bonded only to an element determined to be good.

  In the semiconductor device described above, the following effects can be obtained in addition to the effects of the semiconductor device described above. That is, by increasing the number of elements (the number of rows and columns of the matrix) constituting the element group of the semiconductor chip, it is possible to further suppress the positional deviation when the semiconductor chip is disposed on the insulating substrate. In addition, the number of semiconductor chips provided on the insulating substrate can be reduced, and the number of assembly steps can be reduced.

  In addition, since the semiconductor chip is hardly discarded, the substantial yield is improved. In addition, depending on the use of a semiconductor device such as a control current amount in power applications, a plurality of semiconductor chips may be disposed and wires may be bonded. In this case, the elements determined as non-defective products in the semiconductor chip may be used. The position is allowed to be different.

Embodiment 3
Here, an example of a method for manufacturing a semiconductor device will be described. First, a plurality of elements such as diodes having the same function are formed on the SiC wafer. As shown in FIG. 9, a wafer test is performed on the plurality of elements to determine whether the elements are non-defective (step S1). Next, the semiconductor chip is taken out by dicing the SiC wafer so as to form an element group including a predetermined number of elements (step S2). Thereafter, whether the element in the semiconductor chip is good or bad is determined as necessary (step S3). Thus, information regarding the position of the element determined to be defective is acquired as electronic data (step S5).

  Next, the semiconductor chip is disposed (die-bonded) on the insulating substrate (step S4). Next, the position of the element determined to be non-defective is determined based on the electronic data regarding the position of the element determined to be defective (step S6), and the elements determined to be non-defective based on the determined position are determined. Electrical connection is made by wire bonding (step S7). Thereafter, an insulating substrate on which wire-bonded semiconductor chips are disposed is disposed on a base plate and a predetermined package is formed, whereby the semiconductor device shown in FIG. 1 is completed.

  According to the semiconductor device manufacturing method described above, a plurality of elements having the same function formed on a SiC wafer are taken out from the SiC wafer as an element group including a predetermined number of elements including elements determined to be defective. This is disposed on an insulating substrate as a semiconductor chip. Thereby, only the semiconductor chips determined to be non-defective from the plurality of elements formed on the SiC wafer are individually taken out, and compared with the case where these are arranged on the insulating substrate, the semiconductor chip at the time of assembly Misalignment between each other is unlikely to occur, and problems associated with misalignment between semiconductor chips can be reduced.

  Also, wire bonding can be easily performed by grasping the position of an element determined to be a non-defective product based on electronic data. Furthermore, by electrically connecting elements determined to be non-defective by wire bonding, defects associated with the wafer process can be eliminated compared to the case of electrically connecting by wafer process. It can be reliably prevented that the element determined to be a defective product due to such a defect caused by the wafer process.

Modified Example Here, a case where an element determined to be defective is recognized from an image will be described as an example. First, a plurality of elements each having the same function are formed on a SiC wafer, and a wafer test is performed on the plurality of elements to determine whether or not the elements are non-defective as shown in FIG. 10 (step T1). . Next, a bad mark is given to the element determined to be defective (step T2). As a bad mark, for example, predetermined ink or the like is applied on the element.

  Next, the semiconductor chip is taken out by dicing the SiC wafer so as to form an element group including a predetermined number of elements (step T3). Thereafter, whether the element in the semiconductor chip is good or bad is determined as necessary (step T4). A bad mark is given to the element determined to be defective as before (step T5).

  Next, the semiconductor chip is disposed (die-bonded) on the insulating substrate (step T6). Next, wire bonding is performed (step T7). At this time, each element is recognized by an image so that a wire is not bonded to the element determined to be defective (step T8), and a defective element with a bad mark is detected (step T9). However, a wire is bonded only to elements determined to be non-defective. Thereafter, an insulating substrate on which wire-bonded semiconductor chips are disposed is disposed on a base plate and a predetermined package is formed, whereby the semiconductor device shown in FIG. 1 is completed.

  In particular, in this manufacturing method, when the number of elements constituting the element group of the semiconductor chip is relatively large and the position of the element determined to be defective is random on the semiconductor chip, such a defect is determined. It is suitable for electrically connecting elements determined to be non-defective by removing the formed elements.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. 4 is a graph showing the relationship between the size of a semiconductor chip and the yield in the same embodiment. FIG. 3 is a first plan view showing an element group constituting a semiconductor chip in the embodiment. In the same embodiment, it is the 2nd top view showing the element group which constitutes a semiconductor chip. FIG. 4 is a partial plan view showing a semiconductor chip disposed on an insulating substrate in the same embodiment. FIG. 6 is a cross-sectional view taken along a cross-sectional line VI-VI shown in FIG. 5 in the same embodiment. It is a fragmentary top view which shows the semiconductor chip in the semiconductor device which concerns on Embodiment 2 of this invention. FIG. 8 is a cross-sectional view taken along a cross-sectional line VIII-VIII shown in FIG. 7 in the same embodiment. It is a figure which shows the main flows of the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention. In the same embodiment, it is a figure which shows the main flows of the manufacturing method of the semiconductor device which concerns on a modification.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor device, 3 base board, 5 insulating board, 7a diode chip, 7b transistor chip, 8 element group, 88 element, 9 metal bus bar, 11 resin case, 13, 13a, 13b, 13c, 13d bonding wire, 15 gel , 17 lid, 21 SiC substrate, 22 epitaxial layer, 23 p layer, 24 barrier metal, 25 electrode layer, 26 protective film.

Claims (9)

A plurality of semiconductor chips disposed on the main surface of the insulating substrate; and a conductive member that electrically connects the plurality of semiconductor chips to each other;
Each of the plurality of semiconductor chips includes an element group consisting of a plurality of elements formed in a matrix shape having the same function on a predetermined predetermined substrate portion,
The semiconductor device, wherein the conductive member is a conductive wire that electrically connects elements determined to be non-defective in the element group.   The semiconductor device according to claim 1, wherein the predetermined substrate portion is made of a wafer containing silicon carbide as a main component.   3. The semiconductor device according to claim 1, wherein each of the plurality of semiconductor chips is disposed on the insulating substrate such that an element determined to be defective is disposed at a specific position.   The semiconductor device according to claim 1, wherein a predetermined mark is attached to an element determined to be a defective product in the semiconductor chip. Forming a plurality of elements each having the same function on a wafer mainly composed of silicon carbide;
A screening step of testing each function of the plurality of elements and selecting a non-defective element and a defective element,
Dividing the wafer into semiconductor chips each including a group of elements each including a predetermined number of the elements;
A disposing step of disposing each of the divided semiconductor chips on a surface of a predetermined insulating substrate;
A method of manufacturing a semiconductor device, comprising: a connection step of electrically connecting non-defective elements in the semiconductor chip with conductive wires.   6. The method of manufacturing a semiconductor device according to claim 5, wherein in the arranging step, each of the semiconductor chips is arranged in a matrix so that the defective device is arranged at a specific position.   The method of manufacturing a semiconductor device according to claim 6, wherein in the connection step, the connection by the conductive wire is performed based on data regarding the position of the defective element.   The method of manufacturing a semiconductor device according to claim 5, wherein an identification mark is attached to a defective element in the sorting step.   The method of manufacturing a semiconductor device according to claim 8, wherein in the connecting step, the conductive wire is connected by recognizing an image of the identification mark.

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