JPH11242898A - Memory module and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a memory module to relieve defects and to miniaturize the module by enabling it to output and input data in plural bits unit while combining plural memory chips and also connecting non-used terminals to high resistances to unnecessitate a spare memory chip and a control circuit. SOLUTION: The outputting of data of 8 bits unit of D0 to D7 is performed as a memory module by performing the outputting and inputting of data of 4 bits unit of data d0 to d3 to four pieces of paired memory chips RAM0 to RAM3. Partial chips are used in the RAM0 to RAM3 and chips in which a defect does not exist in all and the total number of data is 8 bits or more are combined. In the figured example, low-order 4 bits are realized by bondingly connecting the defective bit data d0 of the RAM0 to a high resistance for pulling up a level and by connecting other bits d1 to d3 to input-output terminals I01 to I03 and by utilizing the nondefective data d0 of the RAM to data d0 and upper bits are realized by combining the RAM2 and the RAM3 similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory module and an electronic device, and more particularly to a technology effective when used in a technique for relieving a defect of a memory chip and a technique for assembling and manufacturing a suitable electronic device.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. Hei 1-26929 discloses a memory module having a redundant circuit. This memory module includes a regular memory chip partially having non-defective memory cells and a spare memory chip, stores a defective position of the regular memory, and switches an address or an I / O signal of the regular memory and the spare memory. And a circuit. As a result, a memory chip including defective bits that have been discarded until now can be used.

[0003]

In the above-mentioned memory module, a regular memory chip and a spare memory chip are provided as semiconductor chips, and a control circuit for switching between them is required. Therefore, there are problems such as an increase in the number of semiconductor chips and an increase in the size of the memory module itself. Therefore, the inventors of the present invention have realized a miniaturized memory by simultaneously performing the assembly of the memory module and the defect relief while eliminating the need for a special semiconductor chip or control circuit such as a spare memory chip as described above. Modules and
It has led to the development of a suitable electronic device assembly and manufacturing technique.

An object of the present invention is to provide a memory module which has a simple structure and can be reduced in size. Another object of the present invention is to provide a memory module which realizes high reliability at low cost. Another object of the present invention is to provide an electronic device capable of reducing the number of assembly steps. Still another object of the present invention is to provide an electronic device which realizes miniaturization and high performance. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, on a wiring board provided with a plurality of electrodes used for wiring and connection with other devices, data output in a unit of a plurality of bits or data input therewith is enabled, and a part of the data is output. A plurality of memory chips including a data terminal having a defect are mounted thereon, and among the data terminals of the plurality of memory chips, a combination of the data terminals having no defect is connected to the electrode via the wiring, A pull-up or pull-down resistor is connected to the remaining data terminals of the plurality of memory chips.

The following is a brief description of an outline of another typical invention disclosed in the present application. That is, on a wiring board provided with a plurality of electrodes used for wiring and connection with other devices,
In an electronic device including a plurality of semiconductor chips having a predetermined circuit function or circuit element, an electronic component including the semiconductor chip is mounted on a wiring board by using a silver base formed on the wiring board side. Electrical connection with predetermined wiring is performed integrally.

[0007] The outline of another typical invention disclosed in the present application will be briefly described as follows. An electronic device comprising a plurality of semiconductor chips having a predetermined circuit function or circuit element mounted on a wiring board provided with a plurality of electrodes used for wiring and connection with other devices, A cap is provided on the side of the substrate on which the electronic component including the semiconductor chip is mounted, so as to cover the electronic component, and the substrate is sealed.

[0008]

FIG. 1 is a schematic block diagram of one embodiment of a memory module according to the present invention. In the memory module of this embodiment, a printed (PCB) board is used as a mounting board. On the PCB board, four memory chips RAM0 to RAM3 in a bare state as indicated by dotted lines and a high resistance for pulling up or pulling down an input / output terminal including a defective bit are mounted. Each of the memory chips RAM0 to RAM3 is
It is a bare chip that is still divided from the semiconductor wafer and is not provided with a plastic package or the like that covers the surface thereof. The PCB substrate includes a bonding electrode for connecting to the bonding pads of the memory chips RAM0 to RAM3, an electrode for connecting to another electronic device, and a connection between the bonding electrode and the electrode. Is formed. In addition,
If necessary, a capacitor for power supply stabilization is also mounted.

In this embodiment, each of the memory chips RA
M0 to RAM3 output or input data in units of 4 bits like data d0 to d3. On the other hand, the memory module outputs or inputs data in 8-bit units such as D0 to D8.
In this embodiment, each of the RAM0 to RAM3 stores at least one of the 4-bit data d0 to d3.
A so-called partial chip is used in which one has a defect and at least one has no defect. Then, in all of the RAM0 to RAM3, those having the total number of data having no defect of 8 bits or more are combined.

In the example of FIG. 1, in the memory chip RAM0, since a defective bit exists in the data d0, the power supply voltage VDD is applied to one end of the input / output node d0 in order to pull up its level. Bonded to the other end of the high resistance. Then, the remaining data d1
Since there is no defective bit in .about.d3, it is bonded to the connection electrode of the wiring led to the input / output terminals IO1 to IO3 of the memory module. As the data d0 having the defect, data d0 having no defect in the memory chip RAM1 is used. That is, the data d of the memory chip
0 is bonded to a connection electrode of a wiring led to the input / output terminal IO0 of the memory module. In the memory chip RAM1, the remaining data d1 to d3 are not used, so that they are bonded to the pull-up resistors regardless of the presence or absence of a defect. Therefore, in this embodiment, the lower 4 bits of the 8 bits are realized by the memory chips RAM0 and RAM1.

For the upper four bits of the memory module, a combination of the memory chips RAM2 and RAM3 is used. In the example shown in the figure, since there is no defect in only the data d0 in the RAM 2, it is bonded to the connection electrode of the wiring led to the input / output terminal IO4 of the memory module. Then, the remaining input / output terminals IO5 to IO
7 is connected to the bonding pads of the data d1 to d3 of the memory chip RAM3 in the same manner as described above. Then, data d1 to d3 and data d0 of the memory chip RAM2 are stored.
Is connected to the pull-up resistor by bonding.

The memory chips RAM0-RA of this embodiment
In M3, bonding pads are arranged at the center in the longitudinal direction of the memory chip as described later with reference to FIG. In this embodiment, the arrangement of the non-defective data and the defective data is flexibly allocated by utilizing the arrangement of the bonding pads of the memory chip. In other words, the memory chips are arranged in a direction perpendicular to the arrangement of the bonding pads, and the pull-up resistors are provided on both sides of the memory chip row, that is, on both sides of the PCB substrate, so as to be defective areas.
Between AM1, between RAM2 and RAM3, a connection electrode of a wiring led to the input / output terminal is arranged as a non-defective area,
The pull-up resistor is disposed between the RAM 1 and the RAM 2 as a defective area.

Contrary to the above configuration, connection electrodes for wiring leading to the input / output terminals are arranged on both sides of the memory chip row, and between the memory chips RAM0 and RAM1, the RAM2
The pull-up resistor may be arranged between RAM 1 and RAM 3 as a defective area, and a connection electrode of a wiring led to the input / output terminal may be arranged between RAM 1 and RAM 2 as a non-defective area. That is, the defective area and the non-defective area may be arranged alternately with the memory chip interposed therebetween. In such a configuration, the non-defective area and the defective area can be shared between the two memory chips, so that the defect can be easily remedied so as to be applicable to any combination of chips.

The pull-up resistor may use a resistor element formed by a printing technique in addition to a resistor chip described below. In other words, pulling up a defective bit or the like to a high level means that the data terminal of the memory chip is also connected to the input circuit, and when the input signal is set to the floating level,
This prevents a large DC current from flowing in the input circuit or an undesired high potential from being applied to cause latch-up due to a parasitic thyristor element.Accuracy of the resistance value is not required. What is necessary is just a high resistance that does not flow.

Although not shown in FIG. 1, electrodes for connecting to other electronic devices provided on the PCB substrate include those for supplying an address signal and those for memory chips RAM0 to RA0.
When M3 is a dynamic RAM, / RAS (row address strobe), / CAS (column address strobe), / WE (write enable) and / OE
(Output enable) or in a synchronous DRAM,
One that supplies a control signal such as (clock) and / CKE (clock enable), and one that supplies the power supply voltage VDD and the circuit ground potential VSS are included. Here, / represents that the low level is the active level. These electrodes are connected to the RAM0 via wiring.
To the address terminal and control terminal of the RAM3. In this embodiment, the RAM0 to RAM3 are connected in parallel to the address terminals, the control terminals, and the power supply terminals.

For example, in the embodiment of FIG. 1, when each of the memory chips RAM0 to RAM3 has a storage capacity of 64 Mbits, the memory module is 64M × 2.
= 128 Mbits (= 32 Mbytes). The storage capacity that can be realized by the memory module is to increase the storage capacity by increasing the bit width by connecting memory chips in parallel as described above, and to increase the storage capacity by expanding the addresses. Is also good. For example, the address space may be divided into an upper side and a lower side, and the data terminal may be bonded to a connection electrode led to the same input / output terminal.

The storage capacity can be increased by combining both the bit width and the address expansion. For example, in the embodiment of FIG. 1, an address space in which four memory chips similar to the above are provided on the back side is set on the upper side. Thus, 64M × 4 = 256M bits (64M
(M bytes) of storage capacity. The above address space is allocated using address terminals,
A signal using a / RAS signal or the like which functions as a substantial chip select signal may be used.

FIG. 2 is a schematic sectional view of one embodiment of the memory module according to the present invention. In this embodiment, as shown in FIG. 2A, the mounting of the chip on the PCB substrate and the electrical connection are performed simultaneously.
A silver paste pattern is formed on the PCB substrate by a printing technique, and the mounting of the memory chip, the resistor, and the capacitor on the PCB substrate and the electrical connection can be simultaneously performed by bonding with the silver paste. That is,
The back surface side of the substrate of the memory chip is provided with the ground potential of the circuit together with the adhesion to the PCB substrate by the silver paste. One end of the resistor (R) is connected to a wiring side connected to the power supply voltage VDD by a silver paste, and a wiring guided to a connection electrode at the other end is connected by a silver paste. Similarly, both ends of the smoothing capacitor C inserted between the power supply voltage VDD and the ground potential of the circuit are simultaneously mounted on the PCB substrate and connected between the power supply wirings by the silver paste.

A bonding wire is used for selective connection between the memory chip and an electrode of a wiring led to the input / output terminal as described above of the PCB substrate or an electrode connected to a pull-up (or pull-down) resistor. . There are two types of bonding wire connection methods: reverse bonding as shown in FIG. 2B and forward bonding as shown in FIG. That is, the reverse bonding is performed as shown in FIG.
As shown in (2), the bonding wires are first connected to the above-mentioned electrodes of the PCB substrate as shown in (1), and then connected to the bonding pads of the memory chip as shown in (2). In contrast, forward bonding is
As shown in (B), the bonding wires are first connected to the bonding pads of the memory chip as shown in (1), and then connected to the electrodes on the PCB substrate as shown in (2).

[0020] The reverse bonding and the forward bonding as described above are performed by bonding the bonding pad provided on the surface of the memory chip and the PCB substrate in the reverse bonding as shown in FIG. The difference in height from the provided electrodes can be effectively cleared. In other words, the bonder head
After the first connection, it rises almost vertically and moves horizontally to the next bonding point. Therefore, in order to secure the height h of the wire at the end of the memory chip, the horizontal movement distance L1 of the bonder head is shorter in the reverse bonding than in the forward bonding, and the wire length is shorter. In addition, the distance between the memory chip formed on the PCB substrate and the connection electrode can be reduced.
For this reason, in the present embodiment, the memory chip and the connection electrode of the PCB substrate are connected by the reverse bonding.

FIG. 3 is a flowchart for explaining one embodiment of a schematic assembling process of an electronic device including a memory module according to the present invention. In step (1), a PCB substrate is prepared. That is, wiring, electrodes, and connection electrodes are formed using a resin substrate by a multi-layer wiring technique corresponding to the electronic device such as the memory module.

In the step (2), a silver paste is printed by a printing technique in accordance with a connection location of a bare chip such as a memory chip and a connection location of an external component such as a resistor and a capacitor.

In the step (3), elements such as a memory chip, a resistor and a capacitor are bonded by using the silver paste. The mounting and electrical connection of the element are performed at the same time by the adhesive force and conductivity of the silver paste.

In step (4), bonding is performed. For example, in the case of a memory chip having a defect partially, the defective portion is connected to the pull-up resistor as described above, and the non-defective portion is connected to the input / output terminal. Connected to At the same time, bonding for supplying an address signal, a control signal, and power to the memory chip is also performed.

By adopting the above steps, the assembly of an electronic device such as a memory module can be performed.
In addition to being simple and realizable in a process, a memory module having a defective chip in part can be flexibly combined to form a good memory module.

FIG. 4 shows a configuration diagram of a memory module according to the present invention. In this embodiment, an example of a memory module using a PCB board on which nine memory chips can be mounted is shown. FIG. 4A shows an example in which a non-defective chip (KGD) is used as the chip. Therefore, since it is not necessary to perform defect repair, a portion for mounting one memory chip is left empty. In FIG. 4B, seven chips are non-defective products (KGD), and the remaining two chips are partial products (MGM) having defective input / output terminals. In other words, one good chip is equivalently produced using two partial products and combined with the above-mentioned seven memory chips. In FIG. 4C, three chips are non-defective (KGD), and the remaining six chips are partial products (MGM) having a defect in input / output terminals. That is, five non-defective chips are equivalently produced using six partial products and combined with the above-mentioned three memory chips.

As described above, the combination of partial products requires only nine mounted chips in any case. Therefore, the increase in current is 1 compared to the case where eight non-defective chips shown in FIG. It is possible to suppress the increase to about 13%, which is the amount of the chip, and it is possible to design the memory module within the standard.

FIG. 5 is a block diagram showing one embodiment of the memory module according to the present invention. In this embodiment, nine memory chips for inputting and outputting data in 8-bit units are used, and 64-bit input / output terminals IO0 to IO0 are used.
An example in which a memory module having the IO 63 is realized is shown. Of the nine memory chips, six are completely non-defective KGD and the remaining three are input / output terminals (I
O) Partial product MGM is used. Of the electrodes corresponding to the 8 bits provided on the memory chip, white indicates a bonding pad corresponding to non-defective data, and black indicates a bonding pad corresponding to data having a defective bit. ing.

As the memory chip, a type in which bonding pads are arranged at the center in the longitudinal direction of the chip is used. Then, four electrodes are arranged on both sides of the memory chip, and are guided to input / output terminals IO0 to 51 of the memory module through wiring (not shown). Therefore, a total of eight electrodes each having four electrodes are provided in a region between the two memory chips. 4, four electrodes corresponding to the memory chip are provided above the uppermost memory chip, and four input / output terminals IO are provided.
0-3.

The IO partial product MGM is used for the three memory chips from the bottom in FIG. Between the third and second memory chips from the bottom, the electrodes shown in black are connected in parallel to the respective memory chips by five electrodes each leading to a resistor for pulling up defective data. Be placed. Then, the connection electrodes corresponding to the input / output terminals IO52-55 are formed in a vertically long shape so as to be applicable to both chips, so that they can be adapted to the memory chips on both sides.
Are provided. Between the second and the lowest memory chips from the bottom, similarly, five electrodes shown in black, which are led to the pull-up resistors, are arranged in parallel corresponding to the respective memory chips, Four connection electrodes corresponding to the input / output terminals IO56-59 are provided in a vertically elongated shape so as to be applicable to both chips, and are provided so as to be applicable to both memory chips. On the lower side of the lowermost memory chip, five electrodes each of which are drawn in black and led to a pull-up resistor, and four connection electrodes corresponding to the input / output terminals IO60-63 are arranged in one row. Are arranged side by side.

In the IO partial product MGM, the third memory chip from the bottom has defective bits on both sides of the 8 bits, is connected to the pull-up electrode, and has 4 bits out of the remaining 6 bits. Is connected to a connection electrode provided between the fourth non-defective chip KGD from the bottom. In the third memory chip, although the remaining two bits are non-defective, they are connected to the electrodes shown in black as extra bits.

Then, 8-bit input / output terminals IO56-59 and IO60-6 are used by using two memory chips from the bottom.
Correspond to 3. That is, in the memory chip of the second memory from the bottom, one of the eight bits has a defect, and that bit is connected to the lower pull-up resistor electrode. Four of the remaining seven bonding pads corresponding to non-defective data are connected to connection electrodes led to the input / output terminals IO52-55 provided on the upper side, and the remaining three input / output terminals provided on the lower side. Connected to three of terminals IO56-59. In the bottom memory chip, 2
Since the bits are defective and 6 bits are good, one of the bits is an input / output terminal IO5 provided on the upper side.
6-59, and the remaining 4 bits are connected to input / output terminals IO60-63 provided below,
The remaining one bit is connected to the electrode indicated as black as a surplus bit, though it is a good product.

FIG. 6 is a block diagram showing another embodiment of the memory module according to the present invention. Also in this embodiment, an example is shown in which a memory module having input / output terminals IO0 to IO63 of 64 bits is realized by using nine memory chips for inputting / outputting data in 8-bit units in the same manner as described above. ing. In this embodiment, an example is shown in which, in a memory chip, four bonding pads are arranged in the peripheral portion of the chip so as to be distributed vertically. Of the nine memory chips, six are made of completely non-defective products KGD, and the remaining three are made of IO partial products MGM similar to the above. Of the electrodes corresponding to the 8 bits provided on the memory chip, white indicates a bonding pad corresponding to non-defective data, and black indicates a bonding pad corresponding to data having a defective bit. ing.

As the memory chip, a type in which four bonding pads are arranged on the left and right (up and down in the figure) with respect to the longitudinal direction of the chip as described above is used. Then, four electrodes are arranged on both sides of the memory chip, and are guided to input / output terminals IO0 to 51 of the memory module through wiring (not shown). Therefore, in a region sandwiched between two memory chips, four electrodes are arranged in parallel and eight electrodes are provided in total. 4, four electrodes corresponding to the memory chip are provided above the uppermost memory chip, and four input / output terminals I
It corresponds to O0-3.

The IO partial product MGM is used as the three memory chips from the bottom in FIG. For such an IO partial product, two electrodes are provided in an up and down manner corresponding to each bonding pad. In the third memory chip from the bottom, a connection electrode led to the input / output terminal is formed nearer the memory chip as shown in white, and a connection electrode led to a pull-up resistor shown in black is located farther from the memory chip. An electrode is formed. On the other hand, in the second and lowermost memory chips from the bottom, the arrangement of the connection electrodes is alternately black and white, including the electrodes provided below the third memory chip. The electrodes are formed as described above. Therefore, if the electrodes are regularly arranged, the third memory chip may be arranged so that black and white of the electrodes are alternately arranged.

In the IO partial product MGM, in the third memory chip from the bottom, one of the eight bits is determined to be defective, connected to the upper pull-up electrode, and the remaining three bits are input / output. Terminals 44-51 are connected to 49-51. Then, the input / output terminal IO48 corresponding to the defective bit is guided to the lower electrode through the wiring, and the remedy is performed using one of the lower four good bits. The lower four bits are all non-defective, but one bit is connected as a surplus bit to the connection electrode led to the pull-up resistor. And the remaining 2
The bits are used for two bits of the input / output terminals IO52-55. That is, two of the input / output terminals IO52-55 jump over the two electrodes arranged in the vertical direction.
Connected to bits.

In the second memory chip from the bottom, since there is a 2-bit defect on the upper side, it is connected to the connection electrode led to the upper pull-up resistor, and the remaining 2 bits are connected to the input / output terminals IO52-55. Used for two of them. Since the lower four bits are all non-defective, they are connected to the input / output terminals IO56-59. In the lowermost memory chip, one bit of the lower four bits has a defect, so that it is connected to the connection electrode led to the pull-up resistor, and the remaining three bits are used for the input / output terminals IO60-63. One bit corresponding to the defective bit, which is connected to three of the bits, uses an upper non-defective bit and is led to a lower electrode through a wiring to be used for relieving the defective bit. In the upper 4 bits of the lowermost memory chip, there is a 1-bit defect, so it is connected to the electrode led to the pull-up resistor, and the remaining 2 bits are good, but the remaining 2 bits are non-defective. Is connected to the connection electrode led to.

As described above, even when the bonding pads are provided on both sides of the memory chip, the IO partial chip can be effectively used by utilizing the arrangement of the electrodes provided on the PCB substrate side and the wiring for connecting the electrodes. To form a memory module.

FIG. 7 is a schematic configuration diagram for explaining a bonding method in an electronic device according to the present invention. In the electronic device including the memory module as described above in this embodiment, electronic components such as memory chips are mounted on both sides of the wiring board, and the bonding pads and the wiring of the wiring board are connected by bonding wires.
In such a bonding operation, as shown in the figure, in bonding to a semiconductor chip such as a memory chip mounted on the back side, gold wire thermocompression is faster than ultrasonic bonding, but the PCB substrate is It will be hot. Therefore, in the gold wire thermocompression bonding, if only the edge of the PCB substrate is pressed, the PCB substrate is curved and bonding cannot be performed. Therefore, in the gold wire thermocompression bonding, the front surface can be bonded, but the back surface is difficult to bond.

In the present invention, when a memory chip or the like is mounted only on the surface of a PCB substrate, the above-described gold wire thermocompression bonding that can perform high-speed bonding may be used. Therefore, when a memory chip or the like is mounted on both sides as shown in the figure, ultrasonic bonding is basically used. That is, the PCB substrate is mounted on the card edge holder, and ultrasonic bonding using an aluminum wire is performed on the back surface mounted chip while protecting the bonding wires applied to the surface mounted chip. Even in the case of the above-mentioned double-sided PCB substrate, the bonding to the surface-mounted chip can support the entire surface in a state where the bonding is not performed to the chip mounted on the rear surface.
A gold wire thermocompression bonding which is advantageous for the high speed bonding is used. Then, as shown in the drawing, the edge of the PCB substrate is pressed against the backside mounting chip by a card edge holder to protect the surface mounting bonding wires,
Ultrasonic bonding may be performed on the backside mounting chip.

FIG. 8 is an external view of one embodiment of the memory module according to the present invention. FIG. 8A shows the front surface of the memory module, and FIG. 8B shows the back surface of the memory module. The PCB substrate is about 30 mm long and about 38 mm wide.

As shown in FIG. 8A, four non-defective memory chips KGD, a resistor chip R constituting a pull-up resistor, a smoothing capacitor C, and a nonvolatile memory chip SPD are mounted on the front side. . This memory chip SP
In D, history information and the like of each memory chip are recorded, and are used for IO defect relief during assembly. The memory chip may also record the manufacturer, the date of manufacture, the number of terminals, the storage capacity, and the like.

As shown in FIG. 8B, two non-defective memory chips KGD and three IO partial products (secondary silicon) are provided on the back side. As shown schematically in the enlarged view of the figure, defective areas and non-defective areas are alternately arranged with a memory chip interposed therebetween. That is, the configuration is the same as that of the embodiment of FIG. 1, and two non-defective memory chips are equivalently realized by using three IO partial products. Of these three partial products, the defective bits and the surplus bits even if they are good products as described above are connected to the connection electrodes of the wiring led to the pull-up resistor R mounted on the surface side of the defective area. Is done.

FIG. 9 is an overall structural diagram of an embodiment of the memory module according to the present invention. In other words, this embodiment corresponds to the memory module shown in FIG. 8, and the mutual relationship can be understood in a form in which semiconductor components such as a PCB substrate and a memory chip and a cap plate for sealing them are separated. As shown in a development view. By combining these parts,
This is to obtain a memory module as shown in FIG.

In FIG. 9, the four good memory chips KGD, a plurality of pull-up resistors R and capacitors C, and one storage device SPD-IC as described above are mounted on the front and back surfaces of the PCB substrate. On the back side, three secondary silicon and two non-defective memory chips KGD are mounted. Since these semiconductor components and the wiring of the PCB board are connected by bonding wires, a stainless (SUS) cap plate is provided so as to cover the surface thereof. These cap plates are provided with connection portions along the periphery thereof and are adhered to the periphery of the PCB substrate, and the caps protect the semiconductor elements and the bonding wires on the surface of the PCB substrate as shown in FIG. To be.

SUS (stainless steel) as the above cap
By using a conductive metal material such as that described above, it is possible to implement an EMI measure by providing a shielding function of absorbing an undesired electromagnetic wave emitted from a semiconductor chip and a bonding wire or a wiring of a PCB. In addition, by using the stainless steel cap as described above, the heat dissipation of the memory module can be increased, and the required environmental resistance can be secured.

As sealing means for the memory module,
When the surface of the PCB substrate using the cap as described above is covered, mechanical stress on the semiconductor chip and the bonding wires can be reduced as compared with the case where the entire semiconductor chip is solidified with resin. That is,
Due to the difference in thermal expansion between the semiconductor chip and the PCB substrate and the sealing resin, undesired mechanical stress can be prevented from being applied to the semiconductor chip and the bonding wire. A highly reliable memory module can be realized.

FIG. 11 is a sectional view of an embodiment of an electronic device such as a memory module according to the present invention.
In this embodiment, a case is shown in which a bare-chip electronic device is mounted using only one side of a PCB substrate. As described above, a bare chip such as a memory chip is mounted on the surface of a PCB substrate, and its bonding pad and PC
An electronic device such as a memory module having a desired circuit function is configured by connecting the wiring of the B substrate with a bonding wire.

As a sealing means of such an electronic device, a cap made of a metal such as stainless steel or the like which covers the surface is covered. The connection between the cap and the PCB board is not particularly limited, but is bonded with an adhesive through a ventilation material having a large number of extremely small ventilation holes that do not allow water droplets widely used as fibers of various sportswear to pass through. . With this configuration, -50 ° C to 125 °
It is possible to flexibly cope with a change in the internal pressure in the storage operation range such as C. In addition, for example, the space covered with the cap may be filled with an inert gas such as a liquid or nitrogen having an effect of increasing the thermal conductivity or preventing corrosion of the electrodes and the bonding wires. However, when filling with an inert gas, the above-mentioned ventilation material is deleted so that the gas does not leak.

When a conductive material is used for the cap, it is possible to prevent an electrical short circuit from occurring in other electronic components when the electronic component is mounted on the system, or to establish an electrical connection with an internal bonding wire. In order to prevent this, it is convenient to use one having an insulating film formed on its surface. In the case where the cap is made of a conductive metal material and the above-described heat dissipation and EMI countermeasures are taken, the cap is electrically connected to the ground wire of the PCB substrate. Also, PCB
When electronic components are also mounted on the back surface of the substrate, a cap similar to the above is provided on the back surface side.

FIG. 12 is a process chart for explaining an assembling method of one embodiment of the memory module according to the present invention. In step (1), a probe test of a memory chip formed on a semiconductor wafer is performed. That is, a probe is applied to a memory chip formed on a semiconductor wafer to supply a power supply and a test signal, and pass / fail judgment is performed. As a result of the probe test, a defective bit is repaired by a defect repair circuit.

In step (2), the semiconductor wafer is diced, and individual memory chips are divided and stored in a tray. At this time, those having a direct current failure by the probe inspection are excluded, and those having a predetermined number or more of the number of input / output bits as non-defective products are stored as IO partial products in a tray together with non-defective chips. In this tray, non-defective products, defective relief products, and I
In the case of an O partial product, information on which IO is defective is recorded by, for example, a 2D barcode.

In the step (3), mountaining is performed. In other words, the chip is mounted on a dummy substrate made of a plastic die bonding material for a burn-in test, and the connection is made extremely weakly by bonding, so that power supply and input signal supply are enabled.

In the step (4), an accelerated test (burn-in) of supplying a high voltage to the chip mounted on the dummy substrate in a high-temperature atmosphere is performed, and initial defects are identified.

In the step (5), sorting is performed, and a perfect non-defective product and the above-mentioned IO partial product are selected and combined except for the defective product due to the burn-in. For example, in the above example, six perfectly good KGDs and three IOs
Pursue goods MGM, and the good IO is 1 in all
Combinations of 6 or more are selected.

In step (6), assembly is performed. That is, a non-defective chip and an IO partial product are selected by the combination as shown in FIG. 5, FIG. 6 or FIG. 8, and mounted on the PCB substrate. In addition, a pull-up resistor and a capacitor are also mounted. At this time, the PCB substrate
IO defect information of the mounted chip is recorded.

In the step (7), bonding (Bonding)
Is performed. In this case, the bonding to the perfect non-defective KGD is regularly connected to the wiring on the PCB board.
For IO partial products, the 2
The memory module is electrically completed by connecting to the defective area or non-defective area with reference to IO defect information such as a D (two-dimensional) bar code.

In step (8), a temporary cap is placed.

In the step (9), module selection is performed. That is, the burn-in test is performed in a state where the temporary cap is put on, and defects such as the bonding process are washed out.

In the step (10), those which are determined to be defective (FAIL) in the step (9) are decapped, the defective chips are removed in the step (11), and the process returns to the step (6). If a defect occurs in the IO part product and the surplus bits exist as described above, the bonding of that part is changed, and if a defect occurs in the completely non-defective chip, it is replaced with a non-defective chip, and the replaced memory chip is replaced. Can be separately used as an IO partial product. For such a change of bonding wire,
The 2D barcode is referred to. Then, in the same manner as described above, in the history record such as the 2D bar code,
In the case of O partial products, information on which IO has a defect is changed. Then, steps similar to the above are added.

A non-defective product (PAS) is selected by the above step (9).
Those determined as S) are replaced with the present caps to complete the memory module.

In this embodiment, since a burn-in test is performed at the module stage as described above and a non-defective one is selected, a highly reliable memory module can be obtained. And the memory module that failed there,
Instead of discarding as a defect, only a defective chip is removed and replaced with another chip. For this reason,
As described above, a chip having as many as six non-defective chips is not discarded as a defective memory module due to the presence of a single bit defect, so that the cost of the memory module can be significantly reduced. . That is, since the chips formed on the semiconductor wafer can be effectively used, the product yield can be equivalently increased.

FIG. 13 is a process chart for explaining an assembling method of one embodiment of the memory module according to the present invention. In the memory module of this embodiment,
Partial combination of IO partial products, and which IO
Since it is not uniform whether or not there is a defect, it is necessary to respond flexibly to individual defect situations. In this embodiment, what kind of information is added to each memory chip will be described. The basic process flow is the same as in FIG. 12, and a detailed description thereof will be omitted.

In FIG. 13A, all information is recorded in a storage device under computer management. That is, in the probe inspection in the step (1), the history of non-defective pellets and the address in the wafer are recorded in the storage device. In the dicing / tray of the step (2), the result of the probe inspection, that is, the non-defective chips based on the addresses of non-defective chips in the wafer are sorted and placed in the tray. Then, the in-tray address information and the tray number are recorded in the storage device.

In the mounting in the step (3), carrier ID information as a dummy substrate is recorded, and in the step (4)
In the burn-in and the selection in the step (5), the test and selection of the defective IO are omitted by using the IO mask data, and the selection result for each IO is recorded.

In the assembly in the step (6), the position information DiMM of the memory chip on the PCB substrate is added. In the bonding in the step (7), the defective IO is relieved in accordance with the result of the IO selection in the step (5). While the memory module is assembled.

The above process is reasonable because the information for all the IO-purchase rescue is performed by the computer management. On the other hand, if the CIM network becomes complicated and the database is damaged for any reason, the bare chip or the PCB is not used. Since the correspondence information with the substrate is lost, it is necessary to temporarily stop all the processes and start over from creating the first database.

In FIG. 13B, at the time of assembling in the step (6), a database of individual memory chips, that is, the above-mentioned defective IO information and the like is stored in a 2D barcode on the PCB substrate. . Therefore, in the bonding in the step (7), the 2D barcode as described above attached to each PCB substrate is decoded without relying on the IO selection information from the CIM network,
As described above, the memory module is assembled while relieving the defective IO. In this configuration, when the B / I test as a module is performed by applying the temporary cap, the defective chip is removed and replaced with a good chip in the defective module, or a defect occurs in the IO partial portion. In such a case, it can be used for reassembly using another extra bit.

FIG. 14 is a block diagram showing another embodiment of the memory module according to the present invention. In this embodiment, an IO register (buffer) is mounted on a memory module. 1 for modules with multiple banks
A plurality of IO terminal capacities in a module are added to a data bus of a system mounted in one module. When such modules are mounted on a large number of buses, the capacity load of the data bus increases, and high-speed data transfer on the data bus becomes impossible.

In this embodiment, an IO register is provided between the memory module and the system bus. With this configuration, the I on the memory module side
O and the data bus of the system, in other words, the capacity separation between the input / output terminal of the memory module and the capacity load of the data bus of the system can be reduced. Data transfer on the data bus can be performed at high speed. Then, although not particularly limited, in the IO register section, as shown in the enlarged view of the figure, a defective IO is switched by a selector, and only a good IO is connected to the data bus of the system.

The selector selectively connects the terminals 10a and 10b on the memory module side to the terminal 10c on the data bus side by a control signal. The selector is constituted by a clocked inverter circuit. The clocked inverter circuit is activated or deactivated by a high-level / low-level control signal formed by connecting a fuse or the bonding wire, and the memory module side and the data bus side of the system (input terminal side of the memory module). And so on.

The IO register may have only a buffer function. That is, an IO good product MGM is equivalently formed by combining IO partial products MGM with bonding wires, and the IO register is used only for separating the capacitance between the wiring side of the module and the input / output terminal as the module. It may be used. In this case, the input buffer is activated when a write operation is instructed, and the output buffer is activated when a read operation is instructed.

When a switch function for relieving a defective IO is added to the IO register, the memory chip may be a bare chip as described above, or may be a resin-sealed one. That is, the lead terminals of the memory chip are connected to the wiring of the PCB substrate, and the remedy of the defective IO is switched by a high-level / low-level control signal formed by the connection of the fuse and the bonding wire. . When the switching signal is formed by the bonding wire, only that portion may be covered with the resin.

FIG. 15 is a schematic block diagram of another embodiment of the memory module according to the present invention. In this embodiment, a memory module is configured using a package-sealed memory. That is, as described above, nine dynamic RAMs having a × 8 bit configuration are used, and
This implements a bit configuration memory module.
After the above-mentioned dynamic RAM, three IO-purple products MGM and two perfectly good products KGD are provided on the surface shown in the figure.
Is mounted. Then, four completely non-defective products KGD are mounted on the back side (not shown).

Two perfect non-defective products K on the front side and four on the back side
The input / output terminal of GD is IO0 through the wiring of the PCB board.
It is led to the −47 input / output electrode. Then, for the remaining 16 bits of the 64 bits, the three I bits
The 16-bit input / output electrodes IO48-63 are realized by combining non-defective IOs among the O-purple products MGM. In this case, the eight input / output terminals of the three MGMs are guided to the 24 electrodes arranged in the chip IO area through wirings. That is, PC
The B board has a multilayer wiring, and is connected to the input / output terminals IO48-63 of the memory module through the internal wiring.
The chip is led to the electrodes in the chip IO area.

With the chip IO area as the center, a total of 64 electrodes forming a defective area are provided on the other end side of the electrodes IO48-63, that is, inside the PCB substrate. Each of these electrodes is connected to the other end of the pull-up resistor to which the power supply voltage is supplied to one end as described above through a wiring (not shown). This electrode is painted black according to the above-mentioned display method to indicate a defective area. The electrodes corresponding to the defective IOs of the IO partial product MGM are shown in black similarly to the above. Therefore, of the electrodes in the chip IO area, the electrodes shown in black are unconditionally connected to the electrodes in the defective area.

Among the electrodes provided with the chip IO areas, 16 of the 24 good electrodes shown in white are selected as electrodes IO48-63 as non-defective areas.
To be connected. Then, the surplus non-defective products IO are connected to the electrodes in the defective area shown in black. For the connection between these selective electrodes, a bonding wire as described above is used. In addition to the connection using such bonding wires, wiring may be performed using appropriate wiring means. When the above-mentioned bonding wire is used, the wire portion is hardened and protected with an insulating material such as resin. Alternatively, it may be sealed in the same manner as described above with a small cap. Even in the case of using the memory sealed in the package as described above, one memory module can be formed by combining the completely non-defective product and the IO-purple product as described above.

FIG. 16 is a schematic layout diagram showing one embodiment of the dynamic RAM used in the memory module according to the present invention. In the figure, of the circuit blocks constituting the dynamic RAM, a portion related to the present invention is shown so as to be understood. It is formed on one semiconductor substrate.

In this embodiment, although not particularly limited, the memory array is divided into four as a whole. That is,
Two memory arrays are divided into two on the left and right sides in the longitudinal direction of the semiconductor chip, and an address input circuit, a data input / output circuit, an input / output interface circuit including a bonding pad row, and the like are provided in the central portion 14. The portions in contact with the memory array on both sides of the central portion 14 include:
A column decoder region 13 is provided.

As described above, in each of the four memory arrays divided into two on the left and right and two on the upper and lower sides with respect to the longitudinal direction of the semiconductor chip, the main row decoder is disposed at the upper and lower central portions in the longitudinal direction. An area 11 is provided. Main word driver regions 12 are formed above and below the main row decoder, and drive the main word lines of the vertically divided memory array.

The memory cell array (sub-array) 15
Are formed so as to be surrounded by the sense amplifier region 16 and the sub-word driver region 17 with the memory cell array 15 interposed therebetween, as shown in the enlarged view. An intersection between the sense amplifier region and the sub-word driver region is an intersection region (cross area) 18. The sense amplifiers provided in the sense amplifier region 16 are configured by a shared sense method, and except for the sense amplifiers arranged at both ends of the memory cell array, complementary bit lines are provided on the left and right around the sense amplifier. Selectively connected to the complementary bit lines of the memory cell array.

As described above, the memory arrays divided into four on the left and right sides in the longitudinal direction of the semiconductor chip are arranged in groups of two. In the two memory arrays thus arranged in pairs, the main row decoder region 11 and the main word driver 12 are arranged in the center. This main row decoder 11
It is provided in common corresponding to the two memory arrays which are divided up and down around the center. The main word driver 12 generates a selection signal of a main word line extended so as to penetrate the one memory array. Also,
The main word driver 12 is also provided with a driver for selecting a sub-word, and extends in parallel with the main word line to form a selection signal for the sub-word selection line, as described later.

Although not shown, one memory cell array (sub-array) 15 shown as an enlarged view has 256 sub-word lines and 256 pairs of complementary bit lines (or data lines) orthogonal thereto. In the one memory array, 16 memory cell arrays (sub arrays) 15 are provided in the word bit line direction. Therefore, the sub word lines as a whole are provided for about 4K, and 8 sub word lines are provided in the word line direction. The bit line is about 2
K are provided. Since eight such memory arrays are provided in total, a large storage capacity such as 8 × 2K × 4K = 64 Mbits is provided.

The one memory array is divided into eight in the main word line direction. A sub-word driver (sub-word line driving circuit) 17 is provided for each of the divided memory cell arrays 15. The sub-word driver 17 is divided into の 長 of the length of the main word line, and forms a sub-word line selection signal extending in parallel with the length. In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. Are arranged four sub-word lines. In order to select one sub-word line from among the sub-word lines divided into eight in the main word line direction and four in the complementary bit line direction, a sub-word selection driver is used. Be placed. This sub-word selection driver is extended in the arrangement direction of the sub-word drivers.
A selection signal for selecting one of the sub-word selection lines is formed.

Focusing on the one memory array, 1
One sub-word selection line is selected in a sub-word driver corresponding to one memory cell array including a memory cell to be selected among eight memory cell arrays allocated to one main word line, resulting in one main word One sub-word line is selected from 8 × 4 = 32 sub-word lines belonging to the line. As described above, 2K (2048) memory cells are provided in the main word line direction.
/ 8 = 256 memory cells are connected.
Although not particularly limited, in a refresh operation (for example, a self-refresh mode), eight sub-word lines corresponding to one main word line are selected.

One memory array divided into four as described above has a storage capacity of 4 K bits in the complementary bit line direction. However, if as many as 4K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and a signal level that is read out cannot be obtained due to the capacitance ratio with a fine information storage capacitor. Is also divided into 16 in the complementary bit line direction. That is, the complementary bit line is divided into 16 parts by the sense amplifier 16 indicated by a thick black line. Although not particularly limited, the sense amplifier 16 is configured by a shared sense method, and except for the sense amplifiers 16 arranged at both ends of the memory array, complementary bit lines are provided on the left and right around the sense amplifier 16, and the left and right sides are provided. Are selectively connected to the complementary bit lines.

When the bonding pads are arranged side by side in the central portion 14 of the semiconductor chip as described above, the bonding pads can be connected to either the left or right of the bonding pad row of the semiconductor chip.
Therefore, as in the embodiment of FIG. 1 and the like, the defective area and the non-defective area are separately provided on the PCB substrate side. Relief can be provided.

FIG. 17 is a block diagram showing a case where a bare chip of an actual 64-Mbit dynamic RAM is mounted on the back side of a PCB substrate as shown in FIG. 8B. A memory chip (DRAM) has a faulty IO
Three O-partial products MGM are arranged in the vertical direction such that the above-mentioned bonding pad row is parallel.
On the other hand, the two non-defective chips KGD are arranged so that the bonding pad rows are arranged on one straight line adjacent to the electrodes of the PCB substrate. As for the resistor chip, four resistors are built in one chip, and 16 resistors are provided by mounting four resistors in total. The capacitor is
A total of six are provided. The outer edge of the cap is indicated by a dotted line, the inner side is indicated by a solid line, and the PCB is used as an adhesive between them.
Glued to the surface of the substrate. With such a configuration, as described above, a small size of 30 mm × 38 mm is used.
A 4M × 8 = 8M × 64 bit memory module can be realized.

FIG. 18 is a block diagram showing one embodiment of a multi-chip microcomputer system to which the present invention is applied. In the microcomputer of this embodiment, the memory and the input / output unit I /
Access O equipment. In order to improve the processing capacity, various coprocessors and cache memories are provided, and these are connected to a high-throughput system bus. Various I / O devices are I / O separate from the system bus
Often mounted on buses. This is to prevent data transfer from a low-speed I / O device from occupying the system bus. Some of the I / O buses have an I / O processor and a local memory. Since transfer between the system bus and the I / O bus requires high speed, a DMA controller may be used.

In this embodiment, the microcomputer system as described above is realized by three modules. That is, the microprocessor, the coprocessor, the cache, the high-speed I / O, and the DMAC are configured as one module. The main memory is configured by the module 2, and another local memory, an IO processor, and the like are realized by the module 3.

FIG. 19 is a block diagram showing an embodiment of the module 1. A microprocessor and coprocessors 1 to 3 are mounted on the front surface of the same PCB substrate, and a cache memory, high-speed I / O and DMAC are mounted on the back surface. The coprocessor is responsible for, for example, rendering processing, special arithmetic operations such as multiplication and division, and image processing to perform high-speed and high-performance data processing. The cache memory and DMA
By configuring one electronic device by also mounting C and high-speed I / O, a small and high-performance data processing device can be realized.

These are formed in the form of bare chips as described above.
It is mounted on a CB substrate and connected by bonding wires. Then, by sealing using the cap as described above, if there is a defect, the chip can be removed and replaced with a good chip. In addition, a chip to be mounted according to a user's request can be arbitrarily selected using a developed general-purpose chip.
As a result, it is possible to provide a low-cost electronic device such as a microcomputer with high performance and high performance in small-lot production of many kinds.

The operation and effect obtained from the above embodiment are as follows. (1) Data can be read and written in units of a plurality of bits on a wiring board provided with a plurality of electrodes used for wiring and connection with other devices, and a data terminal is partially defective. Using a plurality of memory chips including a memory chip, combining the data terminals of the plurality of memory chips without the defect and connecting the electrodes via the wiring, By connecting pull-up or pull-down resistance means to the remaining data terminals among the data terminals, undesired DC currents at the defective data terminals and latch-up can be prevented, and the assembly of the memory module can be prevented. An effect is obtained that defect relief can be performed integrally.

(2) The wiring board provided with a plurality of electrodes including a plurality of M electrodes, which are used for wiring and connection with other devices, and are used for data output or data input therewith. A plurality of memory chips including a plurality of memory chips including a memory terminal having a data terminal having a defect in a part of a plurality of N-bit units; Of the plurality of memory chips, the data terminals of the plurality of memory chips are connected to the M electrodes via the wiring, and the remaining data terminals are pulled up or connected to the M electrodes. By connecting a pull-down resistor, it is possible to prevent undesired DC current from being generated at the defective data terminal and to prevent latch-up, and to prevent the memory module from being assembled. The effect of being able to perform the fall relief in an integrated manner is obtained.

(3) As the plurality of memory chips,
By combining a completely non-defective memory chip with a memory chip having a defect in one of the data terminals, a practical memory module utilizing IO partial products can be obtained while suppressing an increase in power consumption. The effect is obtained.

(4) The memory chip is a bare chip, and among the bonding pads for inputting / outputting data, a bonding pad having no defect and a wiring leading to the electrode are connected by bonding wires. By connecting the bonding pad and the wiring for leading to the pull-up or pull-down resistor by bonding wires, the number of assembly steps for the entire memory module can be significantly reduced, and
Since the bare chip is mounted on the CB substrate, the effect that the size of the memory module can be reduced can be obtained.

(5) By providing the memory chips on both sides of the wiring board, it is possible to obtain a memory module having an increased storage capacity and a reduced size.

(6) The above-mentioned wiring board is provided with a recording means on which at least defective data terminal information of a memory chip mounted thereon is recorded, so that assembly or re-assembly can be easily performed. Can be obtained.

(7) As the memory chip, one in which bonding pad rows are arranged in the central portion in the longitudinal direction of the memory chip is used, and the wiring board is connected to the electrode on one of both longitudinal sides of the memory chip. By providing a wiring which is connected to the pull-up or pull-down resistor on the other side, it is possible to obtain an effect that bonding can be simplified while securing a degree of freedom of IO relief.

(8) The memory chips are arranged side by side in a direction perpendicular to the longitudinal direction in which the bonding pads are arranged,
For the memory chips adjacent to each other, by forming so that the wiring leading to the electrode or the wiring leading to the pull-up or pull-down resistor can be shared,
The effect is that the degree of freedom of IO rescue can be ensured while simplifying the pattern on the PCB substrate side.

(9) In the case where a row of bonding pads arranged along two opposing sides of the memory chip is used as the memory chip, the two bonding pads of the memory chip are provided on the wiring board. A connection end of a wiring led to the electrode corresponding to each of the columns,
By providing the connection end of the wiring led to the pull-up or pull-down resistor, it is possible to obtain an effect that the degree of freedom of IO relief can be secured.

(10) By adopting reverse bonding in which the bonding wires are first connected to the wiring side of the wiring board and then connected to the bonding pads of the memory chip, the memory chips can be densely mounted on the wiring board. Is obtained.

(11) The electronic components including the memory chip and the pull-up or pull-down resistor are mounted on the wiring board and electrically connected integrally using a conductive adhesive formed on the wiring board side. By doing so, the effect that the number of assembling steps can be reduced can be obtained.

(12) By using a silver paste as the conductive adhesive, it is possible to obtain an effect that application to a PCB substrate is facilitated by a printing technique, and good electrical connection and adhesive strength can be obtained. .

(13) By providing a cap for covering the electronic component and the bonding portion on the surface of the wiring board on which the electronic component is mounted, it is possible to ensure good heat dissipation and to improve the electronic performance. The effect is obtained that the mechanical stress applied to the parts and the bonding wires can be minimized.

(14) The cap is formed of a conductive metal, and the connection between the cap and the wiring board is made by bonding with an adhesive through a gas-permeable material having many small holes through which water droplets do not pass. As a result, an effect that good environmental resistance and EMI countermeasures can be realized is obtained.

(15) By forming an insulating film on the surface of the cap, the above-mentioned good environment resistance and EMI countermeasures are realized, while undesired electrical short-circuit with the internal bonding wire and the system can be prevented. In this case, it is possible to avoid an undesired electrical connection with another electronic component at the time of mounting.

(16) It is possible to output data in a unit of a plurality of bits or input data together with the data on a wiring board provided with a plurality of electrodes used for wiring and connection with other devices. , Equipped with multiple memory chips including those with defective data terminals,
The data terminals of the plurality of memory chips are connected via wiring, are switch-controlled by a control signal stored by a storage unit, and are connected to the electrodes by combining those having no defect and connecting the remaining data terminals. By providing a changeover switch circuit for connecting the pull-up or pull-down resistance means to the memory module, it is possible to obtain an effect that a memory module that effectively utilizes a defective chip can be obtained.

(17) In the above switch circuit, by incorporating a data output buffer or a data input buffer function together with the data output buffer, it is possible to reduce a capacity load on a data bus on a system side in which the data output buffer is mounted and maintain high-speed data transfer. The effect that it can be obtained is obtained.

(18) It is possible to output data in units of a plurality of bits or input data together with the data on a wiring board provided with a plurality of electrodes used for wiring and connection with other devices. A plurality of packaged semiconductor memory devices including those having a defect in a data terminal of a part thereof are mounted, and among the data terminals of the plurality of semiconductor memory devices, those having no defect are combined. By connecting the electrodes via the wiring and connecting the pull-up or pull-down resistance means to the remaining data terminals of the data terminals of the plurality of memory chips, undesired DC at the defective data terminals is reduced. The effect of being able to integrally perform defect relief of memory module assembly while preventing current generation and wrap-up is achieved. can get.

(19) The data terminal of the semiconductor memory device is connected to the first connection electrode via a wiring, and the second terminal connected to the wiring led to the electrode on one side with the first connection electrode interposed therebetween. A connection electrode is provided, and the other is connected to a third wire connected to the pull-up or pull-down resistor means.
A connection electrode is provided, and by selectively connecting the first connection electrode and the second or third connection electrode, the data terminal of the plurality of semiconductor memory devices is combined with the data terminal having no defect to connect the wiring. Connected to the electrode through
By connecting pull-up or pull-down resistor means to the remaining data terminals among the data terminals of the plurality of memory chips, an effect is obtained that the rescue can be simplified while securing the degree of freedom of IO rescue.

(20) On a wiring board provided with a plurality of electrodes used for wiring and connection to other devices, a plurality of electrodes having a predetermined circuit function or circuit element mounted on the wiring board are provided. The electronic component including the semiconductor chip is mounted on the wiring board, and the electronic component including the semiconductor chip is mounted on the wiring board using a conductive adhesive formed on the wiring board side and the electrical connection with predetermined wiring is integrally performed. Accordingly, an effect that a high-performance and small-sized electronic device can be easily obtained is obtained.

(21) The electrical connection between the bonding pad of the semiconductor chip and the wiring is made by a bonding wire, thereby facilitating assembly with flexibility equivalent to the function required of the electronic device. The effect that it can be obtained is obtained.

(22) On a wiring board provided with a plurality of electrodes used for wiring and connection with other devices, a plurality of electrodes mounted on the wiring board and having predetermined circuit functions or circuit elements are provided. A high-performance and small-sized electronic device by providing a cap for covering the electronic component on the side of the wiring substrate on which the electronic component including the semiconductor chip is mounted. Can be easily obtained.

(23) The cap is formed of a conductive metal, and the connection between the cap and the wiring board is
Good environmental resistance by bonding with an adhesive through a breathable material with many small holes that do not allow water droplets to pass
The EMI countermeasure and the effect of repairing when a defect occurs can be achieved.

The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the memory chip may be a read-only memory in which only reading is performed, in addition to a RAM (random access memory) in which writing and reading are performed. The cap may be made of a hard resin, and a conductive film may be formed inside the cap to take the EMI measure. The input / output lines on the memory chip side, which are extended in the horizontal direction, are extended on the PCB substrate by the multi-layer wiring technology so that the wiring connected to the input / output terminals of the memory module is orthogonal to the input / output lines on the memory chip side. In this case, the defective IO may be relieved by extending in the vertical direction and selectively forming a through hole at the intersection thereof to connect the two wirings.

[0117] The electronic device may be such as to realize a computing device for performing complicated data processing operations, an input / output control device, or the like, such as a large-sized computer, in addition to the components constituting the microcomputer as described above. In other words, the semiconductor chip is composed of a digital integrated circuit such as a gate array,
They may be combined to form one electronic device. INDUSTRIAL APPLICABILITY The present invention can be widely used for electronic devices in which a plurality of memory modules and bare-chip semiconductor integrated circuit devices are combined.

[0118]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, on a wiring board provided with a plurality of electrodes used for wiring and connection with other devices, data output in a unit of a plurality of bits or data input therewith is enabled, and a part of the data is output. A plurality of memory chips including a data terminal having a defect are mounted thereon, and among the data terminals of the plurality of memory chips, a combination of the data terminals having no defect is connected to the electrode via the wiring, By connecting pull-up or pull-down resistance means to the remaining data terminals among the data terminals of the plurality of memory chips, it is possible to prevent undesired DC current from being generated or wrap-up at the defective data terminal, and It is possible to integrally perform the defect relief of the module assembly.

An electronic device in which a plurality of semiconductor chips having predetermined circuit functions or circuit elements are mounted on a wiring board provided with a plurality of electrodes used for wiring and connection with other devices. In the above, the electronic component including the semiconductor chip is mounted on the wiring board by using the silver base formed on the wiring board side and the electrical connection with a predetermined wiring is integrally performed, thereby achieving high performance. A small electronic device can be easily obtained.

In an electronic device in which a plurality of semiconductor chips having predetermined circuit functions or circuit elements are mounted on a wiring substrate provided with a plurality of electrodes used for wiring and connection with other devices. On the side of the wiring substrate on which the electronic component including the semiconductor chip is mounted, a cap that covers the electronic component is provided and sealed, so that a high-performance and small electronic device can be easily obtained. Can be.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing one embodiment of a memory module according to the present invention.

FIG. 2 is a schematic sectional view showing one embodiment of a memory module according to the present invention.

FIG. 3 is a flowchart for explaining one embodiment of a schematic assembling process of an electronic device including a memory module according to the present invention.

FIG. 4 is a configuration diagram of a memory module according to the present invention.

FIG. 5 is a configuration diagram showing one embodiment of a memory module according to the present invention.

FIG. 6 is a configuration diagram showing another embodiment of the memory module according to the present invention.

FIG. 7 is a schematic configuration diagram for explaining a bonding method in the electronic device according to the present invention.

FIG. 8 is an external view showing one embodiment of a memory module according to the present invention.

FIG. 9 is an overall structural diagram showing one embodiment of a memory module according to the present invention.

FIG. 10 is an external view showing one embodiment of a memory module according to the present invention.

FIG. 11 is a sectional view showing an embodiment of an electronic device such as a memory module according to the present invention.

FIG. 12 is a process chart for explaining one embodiment of a method of assembling a memory module according to the present invention.

FIG. 13 is a process chart for explaining one embodiment of a method of assembling a memory module according to the present invention.

FIG. 14 is a configuration diagram showing another embodiment of the memory module according to the present invention.

FIG. 15 is a schematic configuration diagram showing another embodiment of the memory module according to the present invention.

FIG. 16 is a schematic layout diagram showing one embodiment of a dynamic RAM used in the memory module according to the present invention.

FIG. 17 is a configuration diagram when a bare chip of a 64 Mbit dynamic RAM is mounted on the back side of a PCB substrate as shown in FIG. 8B.

FIG. 18 is a block diagram showing one embodiment of a multi-chip microcomputer system to which the present invention is applied.

FIG. 19 is a configuration diagram showing one embodiment of the module 1 of FIG. 18;

[Explanation of symbols]

RAM1 to RAM3: Memory chip, KGD: Completely good product, MGM: IO partial product, 10: Memory chip,
11: Main row decoder area, 12: Main word driver area, 13: Column decoder area, 14: Peripheral circuit, bonding pad area, 15: Meseli cell array (sub-array), 16: Sense amplifier area, 17: Sub-word driver area , 18 ... intersection area (cross area)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hirotaka Nishizawa 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Takeshi Wada Inventor Takefumi Josumihoncho, Kodaira-shi, Tokyo No. 20-1, Hitachi Semiconductor Co., Ltd. Semiconductor Division (72) Inventor: Kimihisa Goto 3-1-1, Higashi Koikebo, Kokubunji-shi, Tokyo Hitachi Ultra-SII Engineering Co., Ltd. (72) Inventor: Tanaka Hideki 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the Semiconductor Division, Hitachi, Ltd.

Claims (23)

[Claims] 1. A wiring board provided with a plurality of electrodes used for wiring and connection to another device, and data output in units of a plurality of bits mounted on the wiring board or data output therefrom And a plurality of memory chips including a memory terminal including a part of which has a defect in the data terminal, and combining the data terminals of the plurality of memory chips which do not have the defect with the wiring. And a pull-up or pull-down resistor connected to the remaining data terminals among the data terminals of the plurality of memory chips. 2. A wiring board provided with a plurality of electrodes including M electrodes, which are used for wiring and connection with other devices, and output data or perform data input therewith; A plurality of N smaller than the above M
A plurality of memory chips including a data terminal in which a data output in a bit unit or a data input therewith is enabled, and a data terminal having a defect in a part of the data terminals is provided; Combining a defect-free device, connecting the M electrodes via the wiring, and connecting pull-up or pull-down resistor means to the remaining data terminals of the plurality of memory chips A memory module, comprising: 3. The memory module according to claim 2, wherein the plurality of memory chips include a completely non-defective memory chip and a memory chip having a defect in some of the data terminals. 4. The data terminal of the memory chip is a bonding pad for outputting or inputting data together with the data terminal. The data terminal is connected to a bonding pad having no defect and a wiring for leading to the electrode. 4. The memory module according to claim 1, wherein the connection between the bonding pad and a wiring for leading to the pull-up or pull-down resistor is performed by a bonding wire. 5. The memory module according to claim 4, wherein said memory chips are provided on both sides of said wiring board. 6. The wiring board according to claim 1, wherein said wiring board is provided with recording means for recording at least defective data terminal information of a memory chip mounted thereon. 3 memory module. 7. The memory chip, wherein a bonding pad row is arranged in a central portion in a longitudinal direction of the memory chip, and the wiring board has the electrode on one of both longitudinal sides of the memory chip. 5. The memory module according to claim 3, wherein a wiring guided to the pull-up or pull-down resistor is provided on the other side. 6. 8. The memory chip is arranged side by side in a direction perpendicular to a longitudinal direction in which the bonding pads are arranged. 8. The memory module according to claim 7, wherein a wiring led to an up or pull-down resistor can be shared. 9. The memory chip, wherein a bonding pad row is arranged along two opposing sides of the memory chip, and the wiring board is provided with each of the two bonding pad rows of the memory chip. 5. The memory module according to claim 3, wherein a connection end of a wiring led to the electrode and a connection end of a wiring led to the pull-up or pull-down resistor are provided. 10. The bonding device according to claim 1, wherein the bonding wire is connected to a wiring side of the wiring board first, and then connected to a bonding pad of a memory chip to perform reverse bonding. The memory module according to claim 8 or claim 9. 11. The electronic component including the memory chip and the pull-up or pull-down resistor is mounted and electrically connected to the wiring board integrally using a conductive adhesive formed on the wiring board side. The memory module according to claim 1, wherein the memory module is a memory module. 12. The memory module according to claim 11, wherein the conductive adhesive is a silver paste. 13. The wiring board according to claim 3, wherein a cap is provided on a surface of the wiring board on which the electronic component is mounted, so as to cover the electronic component and a bonding portion. Memory module. 14. The cap is formed of a metal having conductivity, and the connection between the cap and the wiring board is made by bonding an air-permeable material having a large number of small holes through which water droplets do not pass. 14. The memory module according to claim 13, wherein the memory module is adhered by: 15. The memory module according to claim 14, wherein an insulating film is formed on a surface of the cap. 16. A wiring board provided with a plurality of electrodes used for wiring and connection with another device, and output of data in units of a plurality of bits mounted on the wiring board or output therefrom. A plurality of memory chips including those having a defect in some of the data terminals, a control signal connected to the data terminals of the plurality of memory chips via wiring, and stored by the storage means. And a switch circuit for connecting the electrodes having no defect and connecting the electrodes and connecting the pull-up or pull-down resistance means to the remaining data terminals. A memory module, characterized in that: 17. The memory module according to claim 16, wherein said switch circuit has a data output buffer or a data input buffer function incorporated therein. 18. A wiring board provided with a plurality of electrodes used for wiring and connection with another device, and output of data in units of a plurality of bits mounted on the wiring board or data output therefrom. And a plurality of packaged semiconductor memory devices including a device having a defect in some of the data terminals, wherein the defect exists among the data terminals of the plurality of semiconductor memory devices. The plurality of memory chips are connected to the electrodes via the wiring, and a pull-up or pull-down resistor is connected to the remaining data terminals among the data terminals of the plurality of memory chips. Memory module. 19. A data terminal of the semiconductor memory device,
The second connection electrode is connected to the first connection electrode via a wire, one of the two connection electrodes is connected to the wire led to the electrode, and the other is the pull-up or pull-down resistor. A third connection electrode connected to the wiring led to the means; and a selective connection between the first connection electrode and the second or third connection electrode, among the data terminals of the plurality of semiconductor storage devices, Combining the defect-free components, connecting the electrodes via the wiring, and connecting the pull-up or pull-down resistance means to the remaining data terminals among the data terminals of the plurality of memory chips. The memory module according to claim 18, wherein: 20. A wiring board provided with a plurality of electrodes used for wiring and connection to another device, and a plurality of electrodes mounted on the wiring board and having predetermined circuit functions or circuit elements. An electronic component including the semiconductor chip is mounted on the wiring board and electrically connected to predetermined wiring using a conductive adhesive formed on the wiring board side. An electronic device, which is an electronic device. 21. The electronic device according to claim 20, wherein an electrical connection between the bonding pad of the semiconductor chip and the wiring is connected by a bonding wire. 22. A wiring board provided with a plurality of electrodes used for wiring and connection with other devices, and a plurality of electrodes mounted on the wiring board and having predetermined circuit functions or circuit elements. An electronic device, comprising: a semiconductor chip; and a cap that covers the electronic component on a surface of the wiring board on which the electronic component including the semiconductor chip is mounted. 23. The cap is formed of a metal having conductivity, and the connection between the cap and the wiring board is made by bonding an air-permeable material having a large number of small holes through which water droplets do not pass. 23. The electronic device according to claim 22, wherein the electronic device is bonded by: