JPH0358544B2 - - Google Patents
Info
- Publication number
- JPH0358544B2 JPH0358544B2 JP59219207A JP21920784A JPH0358544B2 JP H0358544 B2 JPH0358544 B2 JP H0358544B2 JP 59219207 A JP59219207 A JP 59219207A JP 21920784 A JP21920784 A JP 21920784A JP H0358544 B2 JPH0358544 B2 JP H0358544B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- array
- memory cell
- semiconductor device
- long side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000003491 array Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 11
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 239000000919 ceramic Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dram (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置に関し、特に半導体記憶装
置のメモリセルアレイの配置に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to the arrangement of a memory cell array in a semiconductor memory device.
歴史的にダイナミツクRAMはアドレスマルチ
プレクス方式を採用しており、ロウとカラムのア
ドレスを同一ピンから入力し、時間をずらしてと
り込む方法を行うため、スタチツクRAMに比
べ、アドレス入力ピンの数は1/2ですむ。このた
め、16〜256KビツトまでのダイナミツクRAMで
は16ピン、300mil（7.62mm）幅の小さなDIP（Dual
In Line）型パツケージに収納することが可能と
なつた。したがつて、多くのICを実装する基板
のIC密度が向上し、高密度実装が可能となつて
きた。ところで、材質、製造法により分類する
と、パツケージの種類にはセラミツク型、サーデ
イツプ型、プラスチツク型があるが、大量生産に
適し、コストの低減を達成できるのはプラスチツ
ク型である。ところが、IC基板の実装密度を更
に向上させる場合、プラスチツク型で300mil幅
のDIPパツケージにICチツプを収納するのは以下
のような理由から困難である。
Historically, dynamic RAM has adopted an address multiplexing method, in which row and column addresses are input from the same pin and taken in at different times, so the number of address input pins has been lower than that of static RAM. It only takes 1/2. Therefore, for dynamic RAM from 16 to 256K bits, a small 16-pin, 300mil (7.62mm) wide DIP (Dual
It became possible to store it in a (In Line) type package cage. Therefore, the IC density of a board on which many ICs are mounted has improved, and high-density mounting has become possible. Incidentally, when classified according to material and manufacturing method, there are three types of packages: ceramic type, ceramic type, and plastic type, but the plastic type is suitable for mass production and can achieve cost reduction. However, in order to further improve the packaging density of IC boards, it is difficult to house IC chips in a plastic type DIP package with a width of 300 mils for the following reasons.
まず、プラスチツクパツケージはセラミツクパ
ツケージより機械的強度が弱いため、リードピン
をパツケージ内に埋め込まなければならない。こ
のため、リードピンのためのスペースを確保しな
ければならず、ICチツプの横幅が制限される。
したがつて、チツプ内のメモリセル及び周辺回路
のレイアウトに制限が加わる。これはダイナミツ
クRAMの容量が256Kビツトから1Mビツト更に
4Mビツトへと向上するに従い、微細な加工技術
を使用してもなお増大するチツプサイズに上限を
与えることになる。このことは、単位メモリセル
のサイズを小さくしてしまい、１トランジスタ１
キヤパシタ型のメモリセルであれば、情報を貯え
るキヤパシタ面積の減少を招く。したがつて、ダ
イナミツクRAMのデータ保持特性の劣化及びソ
フトエラー率の増大を引き起し、信頼性が少な
く、商品価値の低いものとなつてしまう。 First, since plastic packages have lower mechanical strength than ceramic packages, lead pins must be embedded within the package. Therefore, space must be secured for the lead pins, which limits the width of the IC chip.
Therefore, restrictions are placed on the layout of memory cells and peripheral circuits within the chip. This means that the dynamic RAM capacity has increased from 256K bits to 1M bits.
As chips advance to 4M bits, there will be an upper limit to the chip size, which will continue to increase even with the use of microfabrication techniques. This reduces the size of the unit memory cell, and 1 transistor 1
If the memory cell is a capacitor type, the area of the capacitor for storing information will be reduced. Therefore, the data retention characteristics of the dynamic RAM deteriorate and the soft error rate increases, resulting in low reliability and low commercial value.
また、プラスチツク型のパツケージでは、リー
ドピンとICチツプのボンデイングパツドとの間
の金属細線によるボンデイング長を長くすること
は、金属細線の断線あるいはボンデイング部の接
続不良を引き起こし、好ましくない。チツプサイ
ズが小さく、チツプの周囲に配置されるリードピ
ンとチツプ内のボンデイングパツドとの距離を小
さくできる場合には、チツプ内のメモリセル及び
ボンデイングパツドのレイアウトは第３図に示す
ようなものである。すなわち、矩形のチツプ１内
に複数のメモリセルアレイ２，…が配列して形成
され、ボンデイングパツド３，…はチツプ１の短
辺に沿つた周縁部にのみまとめて形成される。こ
の場合、回路動作にとつては無駄な領域（チツプ
１の長辺に沿つた周縁部）を極力小さくできるこ
とから有利である。ところが、メモリ容量が大き
くなり、チツプサイズが増大したりピン数が増加
した場合にはリードピンとボンデイングパツドと
の距離を短くするために第４図のようなレイアウ
トを採用する。すなわち、矩形のチツプ１内にお
いてボンデイングパツド３，…はチツプ１の短辺
に沿つた周縁部だけでなく、長辺に沿つた両側の
周縁部にも形成される。このようなレイアウトに
すると、長辺に沿つた周縁部のボンデイングパツ
ドを形成するために要する面積をメモリセルアレ
イ及び周辺回路に利用できなくなる。例えば、第
４図においてはパツド周りの余裕を考慮するとチ
ツプの長辺に沿う周縁部の幅ａとして約200μｍ
づつ必要であり、両側で400μｍの幅の領域がボ
ンデイングパツドのためだけに無駄に使われる。
この結果、メモリセルアレイの横幅を減少せざる
を得なくなりメモリセルの面積が減少し、これに
より製品の信頼性が著しく低下する。 Furthermore, in a plastic package, increasing the bonding length between the lead pin and the bonding pad of the IC chip using a thin metal wire is undesirable because it may cause disconnection of the thin metal wire or poor connection of the bonding portion. If the chip size is small and the distance between the lead pins placed around the chip and the bonding pads inside the chip can be made small, the layout of the memory cells and bonding pads inside the chip will be as shown in Figure 3. be. That is, a plurality of memory cell arrays 2, . . . are arranged in a rectangular chip 1, and bonding pads 3, . In this case, it is advantageous for the circuit operation because the wasted area (periphery along the long side of the chip 1) can be minimized. However, when the memory capacity increases, the chip size increases, and the number of pins increases, a layout as shown in FIG. 4 is adopted to shorten the distance between the lead pins and the bonding pads. That is, within the rectangular chip 1, the bonding pads 3, . With this layout, the area required to form bonding pads along the long sides of the periphery cannot be used for the memory cell array and peripheral circuitry. For example, in Figure 4, considering the margin around the pad, the width a of the periphery along the long side of the chip is approximately 200 μm.
A 400 μm wide area on both sides is wasted just for the bonding pad.
As a result, the width of the memory cell array has to be reduced, and the area of the memory cells is reduced, thereby significantly reducing the reliability of the product.
本発明は上記事情に鑑みてなされたものであ
り、ボンデイングパツドに要する面積を減少して
チツプを有効に利用し、信頼性の向上した半導体
装置を提供しようとするものである。
The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device with improved reliability by reducing the area required for bonding pads and making effective use of chips.
本発明の半導体装置は、チツプ長辺に沿つて隣
接するアレイのチツプ長辺に平行な中心線を互い
にずらした状態で複数列のアレイを配列し、チツ
プの短辺に沿う周縁部及びチツプの長辺に沿う周
縁部のうちアレイとチツプ長辺との間の距離が大
きい方の周縁部にボンデイングパツドを設けたこ
とを特徴とするものである。
In the semiconductor device of the present invention, a plurality of arrays are arranged in such a manner that the center lines parallel to the long sides of the chips of adjacent arrays are shifted from each other along the long sides of the chips. The chip is characterized in that a bonding pad is provided at the peripheral edge along the long side where the distance between the array and the long side of the chip is greater.
このような半導体装置によれば、実質的にチツ
プの長辺に沿う周縁部では片側にのみボンデイン
グパツドを配置したことになるので、ボンデイン
グパツドにより無駄にされる領域を減少してチツ
プを有効に利用することができ、製品の信頼性を
向上することができる。 According to such a semiconductor device, since the bonding pad is arranged only on one side of the periphery along the long side of the chip, the area wasted by the bonding pad can be reduced and the chip can be expanded. It can be used effectively and product reliability can be improved.
以下、本発明の実施例を第１図を参照して説明
する。
Embodiments of the present invention will be described below with reference to FIG.
第１図において、矩形のチツプ１１の中央部に
はデコーダ１２，１２が形成されている。デコー
ダ１２，１２で分割された２つの領域にはそれぞ
れメモリセルアレイ１３1，１３1とメモリセルア
レイ１３2，１３2がチツプ１１の短辺に沿つて２
列づつ配列されている。メモリセルアレイ１３1，
１３1とメモリセルアレイ１３2，１３2とはチツ
プ１１の長辺に沿う中心線を互いにずらした状態
で配列されている。ボンデイングパツド１４，…
はチツプ１１の短辺に沿う周縁部と、長辺に沿う
周縁部のうちチツプ１１長辺とメモリセルアレイ
１３1，１３1，１３2，１３2との距離が大きい方
に設けられている。 In FIG. 1, decoders 12, 12 are formed in the center of a rectangular chip 11. In the two regions divided by the decoders 12, 12, memory cell arrays 13 1 , 13 1 and memory cell arrays 13 2 , 13 2 are arranged along the short side of the chip 11, respectively.
Arranged in columns. Memory cell array 13 1 ,
13 1 and memory cell arrays 13 2 and 13 2 are arranged with their center lines along the long sides of the chip 11 shifted from each other. Bonding pad 14,...
is provided at the peripheral edge along the short side of the chip 11 and the peripheral edge along the long side of the chip 11, whichever has a larger distance between the long side of the chip 11 and the memory cell arrays 13 1 , 13 1 , 13 2 , 13 2 .
しかして上記半導体装置によれば、チツプ１１
の長辺に沿う周縁部のうちボンデイングパツド１
４，…が形成される領域は幅ａとして約200μｍ
を要するが、ボンデイングパツド１４，…が形成
されない領域の幅ｂは約30μｍまで狭くすること
ができる。そして、実質的にはチツプ１１の長辺
に沿う周縁部のうち片側のみがボンデイングパツ
ドに使用されるので、チツプ１１の面積をメモリ
セルアレイとして有効に利用することができ、メ
モリセルのセルサイズを大きくすることができ
る。なお、メモリセルアレイをずらすことにより
アレイを接続する配線を斜めにすることになる
が、この配線に必要な面積の増大はわずかであ
る。 However, according to the above semiconductor device, the chip 11
Bonding pad 1 of the periphery along the long side of
The area where 4,... are formed has a width a of approximately 200 μm.
However, the width b of the region where the bonding pads 14, . . . are not formed can be reduced to about 30 μm. Since only one side of the periphery along the long side of the chip 11 is used for the bonding pad, the area of the chip 11 can be effectively used as a memory cell array, and the cell size of the memory cell can be reduced. can be made larger. Note that by shifting the memory cell arrays, the wiring connecting the arrays is made oblique, but the area required for this wiring increases only slightly.
以上のようなことから蓄積容量を増大でき、セ
ンスアンプに入力される入力信号量を増大させて
感度のよい増幅作用を行なわせることが可能とな
るのでプロセスのバラツキによる特性のバラツキ
を減少させることができる。また、300milの幅
狭なプラスチツクパツケージにも対応でき、リー
ドピンとボンデイングパツドとの配線長を短くす
ることが可能であり、アセンブリ後の配線の断線
あるいは接続不良の問題を減少させることができ
る。したがつて、信頼性の高い高集積メモリIC
を実現できる。 From the above, it is possible to increase the storage capacity, increase the amount of input signal input to the sense amplifier, and perform a highly sensitive amplification action, thereby reducing variations in characteristics due to process variations. I can do it. In addition, it can be used with narrow plastic packages of 300 mil, making it possible to shorten the wiring length between lead pins and bonding pads, and reducing problems with wiring breaks or poor connections after assembly. Therefore, highly reliable and highly integrated memory IC
can be realized.
なお、メモリセルアレイとボンデイングパツド
との配置は第１図に示すものに限らず第２図に示
すようなものでもよい。第２図において、矩形の
チツプ１１の中央部にはデコーダ１２が形成さ
れ、メモリセルアレイ１３3，１３4，１３3，１
３4はチツプ１１の長辺に平行な中心線を交互に
ずらした状態で配列されている。ボンデイングパ
ツド１４，…はチツプ１１の短辺に沿う周縁部及
び長辺に沿う周縁部のうち長辺とメモリセルアレ
イとの距離が大きい方の周縁部に設けられてい
る。 Note that the arrangement of the memory cell array and bonding pads is not limited to that shown in FIG. 1, but may be as shown in FIG. 2. In FIG. 2, a decoder 12 is formed in the center of a rectangular chip 11, and memory cell arrays 13 3 , 13 4 , 13 3 , 1
3 4 are arranged in such a manner that the center lines parallel to the long sides of the chips 11 are alternately shifted. The bonding pads 14, . . . are provided at the periphery along the short side of the chip 11 and the periphery along the long side of the chip 11, whichever has a larger distance from the long side to the memory cell array.
このような配置の半導体装置でも上記実施例と
同様な効果を得ることができる。 Even with a semiconductor device arranged in this manner, the same effects as in the above embodiment can be obtained.
また、以上の説明ではアレイ群がメモリセルア
レイである場合について述べたが、ゲートアレ
イ、ロジツク回路などの回路ブロツクについても
本発明を同様に適用することができる。 Further, in the above description, the case where the array group is a memory cell array has been described, but the present invention can be similarly applied to circuit blocks such as gate arrays and logic circuits.
以上詳述した如く本発明の半導体装置によれ
ば、ボンデイングパツドに要する面積を減少して
チツプを有効に利用し、信頼性を向上できる等顕
著な効果を奏するものである。
As described in detail above, the semiconductor device of the present invention has remarkable effects such as reducing the area required for bonding pads, making effective use of chips, and improving reliability.
第１図は本発明の実施例におけるメモリICの
配置を示す平面図、第２図は本発明の他の実施例
におけるメモリICの配置を示す平面図、第３図
及び第４図は従来のメモリICの配置を示す平面
図である。
１１……チツプ、１２……デコーダ、１３1，
１３2，１３3，１３4……メモリセルアレイ、１
４……ボンデイングパツド。
FIG. 1 is a plan view showing the arrangement of memory ICs in an embodiment of the present invention, FIG. 2 is a plan view showing the arrangement of memory ICs in another embodiment of the invention, and FIGS. FIG. 3 is a plan view showing the arrangement of memory ICs. 11...chip, 12...decoder, 13 1 ,
13 2 , 13 3 , 13 4 ... memory cell array, 1
4...Bonding pad.
Claims (1)
を有し、該アレイ群を外部回路と接続するための
ボンデイングパツドをアレイ外周のチツプ周縁部
に設けた半導体装置において、チツプ長辺に沿つ
て隣接するアレイのチツプ長辺に平行な中心線を
互いにずらした状態で複数列のアレイを配列し、
チツプの短辺に沿う周縁部及びチツプの長辺に沿
う周縁部のうちアレイとチツプ長辺との間の距離
が大きい方の周縁部にボンデイングパツドを設け
たことを特徴とする半導体装置。 ２ アレイの単位構成要素が記憶素子であること
を特徴とする特許請求の範囲第１項記載の半導体
装置。[Scope of Claims] 1. A semiconductor device having a plurality of array groups divided into a rectangular chip, and having bonding pads provided at the chip periphery on the outer periphery of the array for connecting the array groups to an external circuit. , arranging a plurality of arrays in such a manner that center lines parallel to the long sides of the chips of adjacent arrays are shifted from each other along the long sides of the chips;
A semiconductor device characterized in that a bonding pad is provided at a peripheral edge along a short side of a chip and a peripheral edge along a long side of a chip, whichever has a larger distance between the array and the long side of the chip. 2. The semiconductor device according to claim 1, wherein the unit component of the array is a memory element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59219207A JPS6197854A (en) | 1984-10-18 | 1984-10-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59219207A JPS6197854A (en) | 1984-10-18 | 1984-10-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6197854A JPS6197854A (en) | 1986-05-16 |
| JPH0358544B2 true JPH0358544B2 (en) | 1991-09-05 |
Family
ID=16731882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59219207A Granted JPS6197854A (en) | 1984-10-18 | 1984-10-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6197854A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5184208A (en) * | 1987-06-30 | 1993-02-02 | Hitachi, Ltd. | Semiconductor device |
| US5365113A (en) * | 1987-06-30 | 1994-11-15 | Hitachi, Ltd. | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6140053A (en) * | 1984-07-31 | 1986-02-26 | Toshiba Corp | Semiconductor device |
-
1984
- 1984-10-18 JP JP59219207A patent/JPS6197854A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6140053A (en) * | 1984-07-31 | 1986-02-26 | Toshiba Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6197854A (en) | 1986-05-16 |
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