JP2656256B2 - Manufacturing method of integrated circuit - Google Patents
Manufacturing method of integrated circuitInfo
- Publication number
- JP2656256B2 JP2656256B2 JP15706287A JP15706287A JP2656256B2 JP 2656256 B2 JP2656256 B2 JP 2656256B2 JP 15706287 A JP15706287 A JP 15706287A JP 15706287 A JP15706287 A JP 15706287A JP 2656256 B2 JP2656256 B2 JP 2656256B2
- Authority
- JP
- Japan
- Prior art keywords
- heat
- resistant conductive
- conductive film
- integrated circuit
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、砒化ガリウム集積回路の製造方法に関す
るものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gallium arsenide integrated circuit.
第２図に示すように、砒化ガリウム集積回路作製プロ
セスにおいて、耐熱性導電材料をFET電極あるいは配線
に用いる場合に、従来はGaAs基板１上に耐熱性導電膜２
の成膜並びにパターン20の加工を行う。その際、耐熱性
導電膜２がパターン加工されたパターン20の表面は大気
中に露出されている。As shown in FIG. 2, when a heat-resistant conductive material is used for an FET electrode or wiring in a gallium arsenide integrated circuit manufacturing process, a heat-resistant conductive film 2 is conventionally formed on a GaAs substrate 1.
Is formed and the pattern 20 is processed. At this time, the surface of the pattern 20 on which the heat resistant conductive film 2 has been patterned is exposed to the atmosphere.
砒化ガリウム集積回路作製プロセスにおいて、耐熱性
導電膜２を用いる利点は、FETゲート電極としてそれを
用いると、ソース・ドレイン電極下のn+層用注入イオン
活性化のための高温アニールに耐えられるので、n+層を
ゲート電極に対してセルフアラインに形成できるプロセ
スフローが作れることにある。なお、ゲート電極形成と
同時に配線パターンとしても形成できる。The advantage of using the heat-resistant conductive film 2 in the gallium arsenide integrated circuit fabrication process is that if it is used as the FET gate electrode, it can withstand high-temperature annealing for activation of implanted ions for the n + layer under the source / drain electrodes. , N + layer can be formed in a self-aligned manner with respect to the gate electrode. Note that the wiring pattern can be formed simultaneously with the formation of the gate electrode.
通常、耐熱性導電膜２のパターン加工後に高温アニー
ルが行われるので、耐熱性導電膜２上部に非耐熱性材料
は形成しない。したがって、上記パターン加工後、耐熱
性導電膜２からなるパターン20表面は大気中に露出され
た状態で次工程に進む。Usually, high-temperature annealing is performed after the patterning of the heat-resistant conductive film 2, so that a non-heat-resistant material is not formed on the heat-resistant conductive film 2. Therefore, after the above pattern processing, the process proceeds to the next step with the surface of the pattern 20 made of the heat resistant conductive film 2 exposed to the atmosphere.
従来、FET電極あるいは配線材料として用いられる耐
熱性導電膜２の表面は、少なくともそのパターン加工工
程移行、大気中に露出されるので、パターン20の表面に
は酸化膜等が形成され、後に形成される上部配線とのコ
ンタクト特性が劣化する等の問題点がった。Conventionally, since the surface of the heat-resistant conductive film 2 used as an FET electrode or a wiring material is exposed to the atmosphere at least during the pattern processing step, an oxide film or the like is formed on the surface of the pattern 20 and formed later. There is a problem that the contact characteristics with the upper wiring deteriorate.
この発明は、上記のような問題を解消するためになさ
れたもので、FET電極あるいは配線材料として用いられ
る耐熱性導電材料と、後に形成される上部配線とのコン
タクト特性を良好に、かつ安定して形成することを目的
とする。The present invention has been made to solve the above-described problems, and has a good and stable contact characteristic between a heat-resistant conductive material used as an FET electrode or a wiring material and an upper wiring formed later. The purpose is to form.
この発明に係る集積回路の製造方法は、耐熱性導電材
料による成膜直後に同一装置内で低融点金属の多層膜を
連続して形成するものである。According to the integrated circuit manufacturing method of the present invention, a low-melting-point metal multilayer film is continuously formed in the same apparatus immediately after film formation using a heat-resistant conductive material.
この発明においては、耐熱性導電材料による成膜直後
に、同一装置内で低融点金属の多層膜を形成することに
より、大気中において酸化膜による表面高抵抗層を形成
しやすい耐熱性導電材料からなるパターン表面がカバー
され、表面高抵抗層の生成はなくなる。In the present invention, immediately after film formation with a heat-resistant conductive material, by forming a multilayer film of a low-melting-point metal in the same apparatus, it is possible to form a surface high-resistance layer by an oxide film in the air. And the formation of a surface high resistance layer is eliminated.
以下、この発明の一実施例を第１図について説明す
る。An embodiment of the present invention will be described below with reference to FIG.
第１図（ａ），（ｂ）はこの発明の製造工程を示す断
面図で、まず、第１図（ａ）に示すように、砒化ガリウ
ム基板１上に耐熱性導電膜2aを形成し、その上に低融点
金属の多層膜３を形成する。その後、パターン加工を行
い第１図（ｂ）に示すように、パターン20を形成する。1 (a) and 1 (b) are cross-sectional views showing a manufacturing process of the present invention. First, as shown in FIG. 1 (a), a heat-resistant conductive film 2a is formed on a gallium arsenide substrate 1, A low-melting-point metal multilayer film 3 is formed thereon. Thereafter, pattern processing is performed to form a pattern 20 as shown in FIG. 1 (b).
通常、耐熱性導電膜2a表面は酸化しやすく、表面高抵
抗層が形成されやすい。これによりこの後工程で形成さ
れる上層配線とのコンタクト特性は非オーミック特性を
呈しやすく、信頼性レベルでの配線コンタクト不良の生
じる可能性が高い。Usually, the surface of the heat-resistant conductive film 2a is easily oxidized, and a surface high-resistance layer is easily formed. As a result, the contact characteristics with the upper layer wiring formed in the subsequent process are likely to exhibit non-ohmic characteristics, and there is a high possibility that a wiring contact defect at a reliability level occurs.
一方、上記実施例の如く、耐熱性導電膜2a形成直後に
同一装置で低融点金属の多層膜３を耐熱性導電膜2a上に
形成することにより、前記表面高抵抗層の存在はなくな
る。また、Au等の低融点金属膜は大気中にさらされても
表面酸化を生じず、上層配線とのコンタクト特性は良好
となる。On the other hand, by forming the multilayer film 3 of a low melting point metal on the heat-resistant conductive film 2a by using the same apparatus immediately after the formation of the heat-resistant conductive film 2a as in the above embodiment, the surface high-resistance layer is not present. Further, the low melting point metal film such as Au does not oxidize the surface even when exposed to the air, and the contact characteristics with the upper wiring are improved.
なお、上記実施例では、耐熱性導電膜2aの使用が多く
見込まれる砒化ガリウム集積回路について述べたが、S
i,InP等他の基板材料を用いたプロセスにも適用可能で
ある。In the above embodiment, the gallium arsenide integrated circuit in which the heat-resistant conductive film 2a is likely to be used has been described.
It is also applicable to processes using other substrate materials such as i, InP.
以上説明したように、この発明は、半導体基板上に耐
熱性導電膜を形成した直後に、同一装置内で耐熱性導電
膜上に低融点金属の多層膜を形成し、その後、パターン
形成を行うようにしたので、耐熱性導電膜からなるパタ
ーン表面は低融点金属の多層膜で覆われているので、表
面酸化に基づく高抵抗層の形成が回避でき、上層配線と
の信頼性の高いコンタクト特性が得られる効果がある。As described above, in the present invention, immediately after forming a heat-resistant conductive film on a semiconductor substrate, a multilayer film of a low-melting-point metal is formed on the heat-resistant conductive film in the same device, and thereafter, a pattern is formed. As a result, the pattern surface made of a heat-resistant conductive film is covered with a multilayer film of a low-melting-point metal, so that formation of a high-resistance layer based on surface oxidation can be avoided, and highly reliable contact characteristics with the upper-layer wiring can be avoided. The effect is obtained.
第１図（ａ），（ｂ）はこの発明の一実施例の製造工程
を説明する断面図、第２図（ａ），（ｂ）は従来の製造
工程を説明する断面図である。 図において、１は砒化ガリウム基板、2aは耐熱性導電
膜、３は低融点金属の多層膜、20はパターンを示す。 なお、各図中の同一符号は同一または相当部分を示す。1 (a) and 1 (b) are cross-sectional views illustrating a manufacturing process according to an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are cross-sectional views illustrating a conventional manufacturing process. In the figure, 1 is a gallium arsenide substrate, 2a is a heat-resistant conductive film, 3 is a multilayer film of a low melting point metal, and 20 is a pattern. The same reference numerals in each drawing indicate the same or corresponding parts.
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/43 29/812 Continuation of the front page (51) Int.Cl. 6 Identification number Agency reference number FI Technical display location H01L 29/43 29/812
Claims (1)
いる砒化ガリウム集積回路作製プロセスにおいて、半導
体基板に耐熱性導電膜を形成した直後に、同一装置内で
前記耐熱性導電膜上に低融点金属の多層膜を連続して形
成し、その後、パターン形成を行うことを特徴とする集
積回路の製造方法。In a gallium arsenide integrated circuit manufacturing process in which a heat-resistant conductive film is used for an FET electrode or a wiring, a low melting point is formed on the heat-resistant conductive film in the same apparatus immediately after the heat-resistant conductive film is formed on a semiconductor substrate. A method for manufacturing an integrated circuit, comprising forming a metal multilayer film continuously, and thereafter performing pattern formation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15706287A JP2656256B2 (en) | 1987-06-23 | 1987-06-23 | Manufacturing method of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15706287A JP2656256B2 (en) | 1987-06-23 | 1987-06-23 | Manufacturing method of integrated circuit |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPS641231A JPS641231A (en) | 1989-01-05 |
| JPH011231A JPH011231A (en) | 1989-01-05 |
| JP2656256B2 true JP2656256B2 (en) | 1997-09-24 |
Family
ID=15641377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15706287A Expired - Lifetime JP2656256B2 (en) | 1987-06-23 | 1987-06-23 | Manufacturing method of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2656256B2 (en) |
-
1987
- 1987-06-23 JP JP15706287A patent/JP2656256B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS641231A (en) | 1989-01-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3946426A (en) | Interconnect system for integrated circuits | |
| US3918149A (en) | Al/Si metallization process | |
| KR920017184A (en) | Manufacturing Method of Semiconductor Device | |
| JPS6213819B2 (en) | ||
| JP2656256B2 (en) | Manufacturing method of integrated circuit | |
| JPH02231712A (en) | Manufacture of semiconductor device | |
| JPH11204654A (en) | Method for forming gate electrode with double gate insulating films | |
| JPH01130566A (en) | Manufacture of composite unit of emitter/base | |
| EP0514103A1 (en) | Barrier metal process for sub-micron contacts | |
| JPS5923475B2 (en) | Method for forming electrodes for semiconductor devices | |
| JPH011231A (en) | Integrated circuit manufacturing method | |
| JP3651901B2 (en) | Method for manufacturing lateral bipolar transistor | |
| JPS5856459A (en) | Manufacture of semiconductor device | |
| JPS6143484A (en) | Formation of electrode in semiconductor device | |
| JPS62291956A (en) | Semiconductor device | |
| JPH03165515A (en) | Contact forming method | |
| JPH01120065A (en) | Manufacture of semiconductor device | |
| JPS6068634A (en) | Semiconductor device | |
| JPS63114261A (en) | Self-aligning base shunt for transistor | |
| JPS59152643A (en) | Forming method of wirings | |
| JPS6130031A (en) | Manufacture of semiconductor device | |
| JPH01107523A (en) | Manufacture of electrode of compound semiconductor device | |
| JPH02260569A (en) | Schottky diode | |
| JPS6014466A (en) | Manufacture of semiconductor integrated circuit | |
| JPH0461496B2 (en) |