JPS6068634A - Semiconductor device - Google Patents

Abstract

PURPOSE:To accelerate the operation of a semiconductor device with a silicide layer by connecting a metal silicide layer formed on a polycrystalline silicon of lower layer with two polycrystalline silicon layers, thereby enabling to reduce the contacting area between two polycrystalline silicon layers. CONSTITUTION:A high melting point metal layer is formed on the first polycrystalline silicon layer 3, a molybdenum silicide layer 8 is formed by exposing, for example, in nitrogen atmosphere of high temperature to remove the prescribed portion such as by a lithographic technique. Then, the second polycrystalline silicon layer 5 is formed, and the prescribed portion is allowed to remain. According to this method, even if the layers 3, 5 are in reverse conductive types, no P-N junction is formed due to the presence of an intermediate silicide layer 8. Thus, the layers 3, 5 coupled by a wiring material becomes an overlapped portion only, thereby eliminating a space for contacting and increasing the degree of freedom of wirings. The layer resistance can be reduced by silicifying the layer 3, thereby being effective for acceleration.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a semiconductor device having two or more polycrystalline semiconductor layers. , when the first polycrystalline silicon layer and the second polycrystalline silicon layer have different conductivity types, when the first polycrystalline silicon layer and the second polycrystalline silicon layer are brought into direct contact, the contacted portion A PN junction is made in
There is a drawback that current will not flow if a reverse bias is applied to the PN junction.For this reason, when connecting the first polycrystalline silicon layer and the second polycrystalline silicon layer, it is necessary to use a wiring material (such as At). ) are used to connect them.

This method requires a contact part for connecting the first polycrystalline silicon layer and the wiring material, and a contact part for connecting the second polycrystalline silicon layer and the wiring material, which wastes space. This is a disadvantageous factor for miniaturization of semiconductor devices, and at the same time, freedom in wiring is also lost. In addition, two contact resistors are inserted to connect the first polycrystalline silicon layer and the second polycrystalline silicon layer, and even if the polycrystalline silicon layer is heavily doped with impurities, the layer resistance remains low. The resistance decreases to only about 10 Ω/port, which is disadvantageous for increasing the speed of semiconductor devices.

The present invention provides a semiconductor device that is effective in miniaturizing and increasing the speed of semiconductor devices.

The present invention is characterized in that two polycrystalline silicon layers are connected by a metal silicide layer formed on the underlying polycrystalline silicon. FIG. 1 shows a cross-sectional view of the structure of a semiconductor device produced by a conventional method. When the first polycrystalline silicon layer 3 and the second polycrystalline layer 5 formed on the insulating film 2 on the silicon substrate 1 are of opposite conductivity type, the two polycrystalline silicon layers are directly connected to each other. ? When brought into contact, an N junction is formed, so the wiring material 7 (for example, A/
The two polycrystalline/recon layers 3 and 4 are connected via a wire. In this case, area for contacts is required.

Since the insulator film layers 4 and 6 on the first polycrystalline silicon layer 3 are thick, there are drawbacks such as a large contact hole. Furthermore, even if impurities are diffused in a high concentration in the polycrystalline silicon layer, the layer resistance decreases only to a few tens of degrees, which is disadvantageous for high-speed operation. Structural cross section 1q of a semiconductor device according to an embodiment of the present invention is shown in Figure 2. In the present invention, after forming the first layer of polycrystalline silicon 3, a layer of high melting point metal (for example, molybdenum, etc.) is formed thereon, and the dimolybdenum silicide layer 8 is formed by exposing it to air at high temperature for 1 minute, for example. Form. An insulating film 4 is formed on the silicide layer 8, and a predetermined portion of the insulating film 4 on the silicide layer 8 is removed using, for example, a phosphorography technique. Next, a second polycrystalline silicon layer 5 is formed, and a predetermined portion of the second polycrystalline silicon layer is left by a known method.

According to the above method, even if the first polycrystalline silicon layer 3 and the second polycrystalline silicon layer 5 are of opposite conductivity types, the presence of the silicide layer 8 between the two layers makes the PN junction Because of this, the first polycrystalline silicon layer 3 and the second polycrystalline silicon layer 5, which were connected by the wiring material, have only the space for the two layers of auto-contact. This eliminates the need for wiring, and increases the degree of freedom in wiring. By siliciding the first polycrystalline layer 3, the layer resistance can be lowered, which is also effective in increasing speed. Further, as shown in FIG. 3, by forming, for example, a platinum silicide layer 9 (low melting point metal silicide) on the second polycrystalline silicon layer 5, even higher speeds can be expected. A refractory metal silicide layer may be formed in the second polycrystalline silicon layer 5.

As described above, according to the present invention, the contact area between two layers of polycrystalline silicon can be reduced, and by using a silicide layer, it is expected that the speed of semiconductor devices will be increased.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a conventional example, and FIGS. 2 and 3 are sectional views showing an embodiment of the present invention. 1 is a semiconductor substrate, 2 is an insulating film, 3 is a first polycrystalline silicon layer, 4 is an insulating film between the eyebrows between the first polycrystalline silicon layer and the second polycrystalline silicon layer, and 5 is a second layer Polycrystalline silicon layer, 6 is an interlayer insulating film between the second polycrystalline silicon layer and wiring material, 7 is wiring material, 8 is a high melting point metal silicide layer (for example, molybdenum silicide), 9 is a low melting point metal silicide layer (e.g. platinum silicide) t-respectively. Agent Patent Attorney Yen Hara

Claims (1)

[Claims] 1. A semiconductor device having two or more polycrystalline semiconductor layers, characterized in that a metal semiconductor layer is formed between two polycrystalline semiconductor layers.