JP2649511B2 - Semiconductor storage device - Google Patents

Semiconductor storage device

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Publication number
JP2649511B2
JP2649511B2 JP61022180A JP2218086A JP2649511B2 JP 2649511 B2 JP2649511 B2 JP 2649511B2 JP 61022180 A JP61022180 A JP 61022180A JP 2218086 A JP2218086 A JP 2218086A JP 2649511 B2 JP2649511 B2 JP 2649511B2
Authority
JP
Japan
Prior art keywords
film
silicon oxide
thickness
memory device
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61022180A
Other languages
Japanese (ja)
Other versions
JPS62181474A (en
Inventor
和夫 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61022180A priority Critical patent/JP2649511B2/en
Publication of JPS62181474A publication Critical patent/JPS62181474A/en
Application granted granted Critical
Publication of JP2649511B2 publication Critical patent/JP2649511B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体記憶装置、特に書込・消去特性の優
れた不揮発性半導体記憶装置に関する。
Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having excellent write / erase characteristics.

(従来の技術) 従来、不揮発性半導体記憶装置の代表的なものとし
て、MNOS(金属−ナイトライド膜−酸化シリコン膜−半
導体)構造の半導体記憶装置がよく知られている。MNOS
型半導体記憶装置は、ゲート電極−半導体基板間に比較
的高い電圧(15〜25V程度)を印加し、極薄の酸化シリ
コン膜とナイトライド膜の界面付近、又はその近傍のナ
イトライド膜中に存在するトラップに、半導体側から電
荷のトンネリング注入,蓄積を行ない、トランジスタの
しきい値電圧を変化させて情報を記憶させることを原理
としている。
(Prior Art) Conventionally, as a typical nonvolatile semiconductor memory device, a semiconductor memory device having an MNOS (metal-nitride film-silicon oxide film-semiconductor) structure is well known. MNOS
In a semiconductor memory device, a relatively high voltage (about 15 to 25 V) is applied between the gate electrode and the semiconductor substrate, and the nitride film is formed near the interface between the ultra-thin silicon oxide film and the nitride film or in the vicinity thereof. The principle is that tunneling injection and accumulation of charges are performed from the semiconductor side to existing traps, and information is stored by changing the threshold voltage of the transistor.

第3図は、従来のnチャンネルMNOS型半導体記憶装置
の断面構造の一例を示したものである。1はp型シリコ
ン基板、2及び3はn型の選択拡散領域であり、ソー
ス,ドレイン領域と呼ばれる。また、4はトンネリング
媒体となり得る薄い酸化シリコン膜、6はナイトライド
膜、7はポリシリコン膜からなるゲート電極である。
FIG. 3 shows an example of a cross-sectional structure of a conventional n-channel MNOS type semiconductor memory device. Reference numeral 1 denotes a p-type silicon substrate, and 2 and 3 denote n-type selective diffusion regions, which are called source and drain regions. Reference numeral 4 denotes a thin silicon oxide film that can serve as a tunneling medium, 6 denotes a nitride film, and 7 denotes a gate electrode made of a polysilicon film.

(発明が解決しようとする問題点) 第3図に示すような従来構成のMNOS型半導体記憶装置
の書込・消去特性の一例を第2図に破線8,9で示す。例
えば±20Vのパルス電圧を用いた場合、書込・消去に必
要な時間は、書込の場合2ms以上、消去の場合50ms以上
の時間が必要となっており、書込時間に比べ消去時間が
著しく長くなるという欠点を有し、大容量メモリに適用
する際の実用上の問題点となっている。
(Problems to be Solved by the Invention) An example of the write / erase characteristics of the MNOS type semiconductor memory device having the conventional configuration as shown in FIG. 3 is shown by broken lines 8 and 9 in FIG. For example, when a pulse voltage of ± 20 V is used, the time required for writing / erasing is 2 ms or more for writing and 50 ms or more for erasing, and the erasing time is longer than the writing time. It has a drawback of being extremely long, which is a practical problem when applied to a large capacity memory.

本発明の目的は、かかる問題点に鑑み、書込・消去特
性、特に消去特性を大幅に向上させた新規な構成のMNOS
型半導体記憶装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a MNOS having a novel configuration in which write / erase characteristics, particularly erase characteristics, are significantly improved in view of the above problems.
It is an object of the present invention to provide a type semiconductor memory device.

(問題点を解決するための手段) 上記問題点を解決するために、本発明は、一導電型の
単結晶半導体基板上の所定の領域に、絶縁膜、ナイトラ
イド膜、導電膜が順次積層され、前記所定の領域の両側
にそれぞれ隣接した前記半導体基板に前記半導体基板と
は反対導電型の領域を有する半導体記憶装置において、
前記絶縁膜は15〜30Åの膜厚を有し、酸化シリコン膜と
オキシナイトライド膜から構成され、かつ前記オキシナ
イトライド膜の膜厚は前記絶縁膜の膜厚のほぼ半分であ
ることを特徴とするものである。
(Means for Solving the Problems) In order to solve the above problems, the present invention provides an insulating film, a nitride film, and a conductive film sequentially stacked in a predetermined region on a single conductivity type single crystal semiconductor substrate. In the semiconductor memory device, the semiconductor substrate adjacent to both sides of the predetermined region has a region of the opposite conductivity type to the semiconductor substrate,
The insulating film has a thickness of 15 to 30 °, is composed of a silicon oxide film and an oxynitride film, and the thickness of the oxynitride film is substantially half the thickness of the insulating film. It is assumed that.

(作用) 本発明は、オキシナイトライド膜+酸化シリコン膜の
膜厚が15〜30Åであり、従来のものに比較して酸化シリ
コン膜を薄くすることによって、トンネリング注入に対
するバリアを低下させることが可能となり、書込・消去
特性を向上させることができる。ここで、単に酸化シリ
コン膜を薄くしただけでは、その上のナイトライド膜に
注入され書き込まれた電荷、特に酸化シリコン膜−ナイ
トライド膜界面付近に存在する電荷が酸化シリコン膜を
通して逃げることになる。
(Operation) In the present invention, the thickness of the oxynitride film + silicon oxide film is 15 to 30 °, and the barrier against tunneling implantation can be reduced by making the silicon oxide film thinner than the conventional one. This makes it possible to improve the write / erase characteristics. Here, if the silicon oxide film is simply thinned, charges injected into and written into the nitride film thereon, particularly charges existing near the interface between the silicon oxide film and the nitride film, escape through the silicon oxide film. .

一方、薄いオキシナイトライド膜は、電荷をトンネリ
ングさせる酸化シリコン膜の性質とともに、電荷をトラ
ップするナイトライド膜の性質を兼ね備えているので、
書込あるいは消去が行なわれる程の高い電圧が膜の両端
に印加されない限り、ナイトライド膜界面付近に存在す
る電荷を十分保持することができる。このように、オキ
シナイトライド膜は、電荷の拡散を抑え、記憶状態を維
持するという役目を果たすことになる。
On the other hand, a thin oxynitride film has the properties of a nitride film that traps electric charges, as well as the properties of a silicon oxide film that tunnels electric charges.
Unless a voltage high enough to perform writing or erasing is applied to both ends of the film, the charge existing near the interface of the nitride film can be sufficiently held. As described above, the oxynitride film has a role of suppressing charge diffusion and maintaining a memory state.

(実施例) 本発明の具体的な実施例を第1図に従って説明する。
本半導体記憶装置は、第1図に示すように、単結晶p型
シリコン基板1上の所定の領域に、薄い酸化シリコン膜
4,薄いオキシナイトライド膜5,ナイトライド膜6及びポ
リシリコン膜からなるゲート電極7を順次積層し、この
領域に隣接した両側にそれぞれn型領域からなるソー
ス,ドレイン領域2,3を設け、その上にソース,ドレイ
ン電極12,13を形成したものである。
(Example) A specific example of the present invention will be described with reference to FIG.
As shown in FIG. 1, the present semiconductor memory device has a thin silicon oxide film in a predetermined region on a single crystal p-type silicon substrate 1.
4, a thin oxynitride film 5, a nitride film 6, and a gate electrode 7 made of a polysilicon film are sequentially stacked, and source and drain regions 2, 3 each made of an n-type region are provided on both sides adjacent to this region, Source and drain electrodes 12 and 13 are formed thereon.

トンネリング媒体となり得る薄い酸化シリコン膜4
と、薄いオキシナイトライド膜5は、トンネリング効果
を有効に利用するために、両方の膜の膜厚の合計を15〜
30Å程度にする必要があり、本実施例では酸化シリコン
膜10Å,オキシナイトライド膜10Åとした。薄い酸化シ
リコン膜は、公知のシリコン基板の酸化により形成し、
また、オキシナイトライド膜の形成法としては、(1)
アンモニア(NH3),ジクロルシラン(SiH2Cl2)及び亜
酸化窒素(N2O)の化学反応に基づく気相成長法により
形成する方法,(2)酸化シリコン膜4をアンモニア
(NH3)などで直接窒化する方法,(3)アンモニア(N
H3)とジクロルシラン(SiH2Cl2)との化学反応に基づ
く気相成長法によりナイトライド膜を形成し、そのナイ
トライド膜を酸化する方法などがあるが、本実施例では
(1)の方法で形成した。
Thin silicon oxide film 4 that can be a tunneling medium
In order to effectively use the tunneling effect, the thin oxynitride film 5 has a total thickness of both films of 15 to
It is necessary to set the thickness to about 30 °. In this embodiment, the thickness is set to 10% for the silicon oxide film and 10% for the oxynitride film. A thin silicon oxide film is formed by oxidation of a known silicon substrate,
Further, as a method of forming the oxynitride film, (1)
A method of forming by a vapor phase growth method based on a chemical reaction of ammonia (NH 3 ), dichlorosilane (SiH 2 Cl 2 ) and nitrous oxide (N 2 O), (2) a silicon oxide film 4 such as ammonia (NH 3 ) (3) Ammonia (N
There is a method of forming a nitride film by a vapor phase growth method based on a chemical reaction between H 3 ) and dichlorosilane (SiH 2 Cl 2 ), and then oxidizing the nitride film. Formed by the method.

次に、オキシナイトライド膜5上に、NH3/SiH2Cl2
10の割合で、750℃の条件下の気相成長法により、ナイ
トライド膜6を約500Å形成した。
Next, on the oxynitride film 5, NH 3 / SiH 2 Cl 2 =
A nitride film 6 was formed at a rate of 10 by a vapor phase growth method at 750 ° C. at about 500 °.

次いで、ナイトライド膜6の上にポリシリコン膜を約
4000Å形成させ、ゲート電極7を形成した。その後、イ
オン注入法により、リンを打ち込み、ソース,ドレイン
領域2,3を形成し、その上にソース,ドレイン電極を形
成することにより、第1図に示すような構成の半導体記
憶装置を得ることができる。
Next, a polysilicon film is formed on the nitride film 6 approximately.
The gate electrode 7 was formed by forming the electrode at 4000 °. Thereafter, phosphorus is implanted by ion implantation to form source / drain regions 2 and 3 and source / drain electrodes are formed thereon to obtain a semiconductor memory device having the structure shown in FIG. Can be.

以上のように構成された本実施例の書込・消去特性を
第2図に実線10,11で示す。例えば±20Vのパルス電圧を
用いた場合、従来例の特性(破線8,9)に比べ、書込・
消去特性の向上が見られ、特に消去側で著しい向上が見
られる。
The write / erase characteristics of this embodiment configured as described above are shown by solid lines 10 and 11 in FIG. For example, when a pulse voltage of ± 20 V is used, the write / read characteristics are lower than the characteristics of the conventional example (broken lines 8 and 9).
Erasure characteristics are improved, and remarkably improved especially on the erasure side.

(発明の効果) 以上説明したように、本発明によれば、書込・消去特
性の大幅な向上を図ることができ、大容量メモリに適用
する際の実用上の問題解決に大きく寄与するものであ
る。
(Effects of the Invention) As described above, according to the present invention, the write / erase characteristics can be significantly improved, and this greatly contributes to solving practical problems when applied to a large capacity memory. It is.

【図面の簡単な説明】[Brief description of the drawings]

第1図は、本発明の一実施例の断面図、第2図は、本発
明の効果を説明するための書込・消去特性図、第3図
は、従来のMNOS型半導体記憶装置の断面図である。 1……単結晶p型シリコン基板、2,3……ソース,ドレ
イン領域、4……酸化シリコン膜、5……オキシナイト
ライド膜、6……ナイトライド膜、7……ゲート電極、
12,13……ソース,ドレイン電極。
FIG. 1 is a sectional view of one embodiment of the present invention, FIG. 2 is a write / erase characteristic diagram for explaining the effect of the present invention, and FIG. 3 is a sectional view of a conventional MNOS type semiconductor memory device. FIG. 1 ... single crystal p-type silicon substrate, 2, 3 ... source and drain regions, 4 ... silicon oxide film, 5 ... oxynitride film, 6 ... nitride film, 7 ... gate electrode,
12,13 ... Source and drain electrodes.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】一導電型の単結晶半導体基板上の所定の領
域に、絶縁膜、ナイトライド膜、導電膜が順次積層さ
れ、前記所定の領域の両側にそれぞれ隣接した前記半導
体基板に前記半導体基板とは反対導電型の領域を有する
半導体記憶装置において、前記絶縁膜は15〜30Åの膜厚
を有し、酸化シリコン膜とオキシナイトライド膜から構
成され、かつ前記オキシナイトライド膜の膜厚は前記絶
縁膜の膜厚のほぼ半分であることを特徴とする半導体記
憶装置。
An insulating film, a nitride film, and a conductive film are sequentially laminated on a predetermined region on a single conductivity type single crystal semiconductor substrate, and the semiconductor film is formed on the semiconductor substrate adjacent to both sides of the predetermined region. In a semiconductor memory device having a region of a conductivity type opposite to a substrate, the insulating film has a thickness of 15 to 30 °, is composed of a silicon oxide film and an oxynitride film, and has a film thickness of the oxynitride film. Is a half of the thickness of the insulating film.
JP61022180A 1986-02-05 1986-02-05 Semiconductor storage device Expired - Lifetime JP2649511B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61022180A JP2649511B2 (en) 1986-02-05 1986-02-05 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61022180A JP2649511B2 (en) 1986-02-05 1986-02-05 Semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS62181474A JPS62181474A (en) 1987-08-08
JP2649511B2 true JP2649511B2 (en) 1997-09-03

Family

ID=12075597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61022180A Expired - Lifetime JP2649511B2 (en) 1986-02-05 1986-02-05 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JP2649511B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2718931B2 (en) * 1987-09-29 1998-02-25 松下電子工業株式会社 Method for manufacturing semiconductor memory device
KR100345662B1 (en) * 1995-12-16 2002-11-07 주식회사 하이닉스반도체 Method for forming gate insulating layer in semiconductor device
US6767794B2 (en) * 1998-01-05 2004-07-27 Advanced Micro Devices, Inc. Method of making ultra thin oxide formation using selective etchback technique integrated with thin nitride layer for high performance MOSFET

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58212180A (en) * 1982-06-03 1983-12-09 Matsushita Electronics Corp Nonvolatile memory device and manufacture thereof
US4876582A (en) * 1983-05-02 1989-10-24 Ncr Corporation Crystallized silicon-on-insulator nonvolatile memory device

Also Published As

Publication number Publication date
JPS62181474A (en) 1987-08-08

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