JP2644647B2 - Direct detection receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct detection type receiver.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an electrical configuration of a typical prior art direct detection receiver 1. As shown in FIG. The received signal received by the antenna 2 is provided to the orthogonal transform circuit 4 via the high frequency amplifier circuit 3. Orthogonal transform circuit 4
A voltage-controlled oscillation circuit 5 that oscillates at a frequency corresponding to the tuning voltage from the tuning control circuit 20, a multiplier 7 that multiplies a reference signal from the voltage-controlled oscillation circuit 5 by the received signal, The phase shifter 6 derives the signal by shifting the phase of the signal by 90 degrees, and a multiplier 8 that multiplies the received signal by the reference signal from the phase shifter 6.

The outputs from the multipliers 7 and 8 are supplied to low-pass filters (hereinafter abbreviated as LPFs) LPFs 9 and 1, respectively.
After the audio signal band to be demodulated at 0 is filtered, it is input to the demodulation circuit 11. The demodulation circuit 11 includes a so-called digital signal processor and the like.
An audio signal demodulated by, for example, obtaining the mean square of the outputs from the PFs 9 and 10 is provided to the speaker 13 via the power amplifier 12.

The tuning control circuit 20 is composed of a phase lock loop circuit of an electronic tuning type tuner, and a programmable counter 21 for dividing the frequency of the oscillation signal of the voltage controlled oscillation circuit 5 and a dividing ratio of the programmable counter 21. A control circuit 22 for controlling a crystal oscillator 23 for oscillating at a reference frequency; a frequency dividing circuit 24 for dividing the oscillation signal of the crystal oscillator 23; an output from the programmable counter 21 and a frequency dividing circuit 24 And a LPF 26 that provides a DC voltage level output corresponding to the comparison result of the phase comparison circuit 25 to the voltage control oscillation circuit 5 as a tuning voltage. .

Accordingly, when the frequency division ratio of the programmable counter 21 is changed by the control circuit 22, a phase difference occurs between the output from the programmable counter 21 and the output from the frequency dividing circuit 24, and this phase difference becomes zero. As described above, the tuning voltage is applied to the voltage controlled oscillation circuit 5. Thus, a broadcast of a desired frequency can be received.

[0006]

In the prior art described above, the phase shifter 6 is constituted by a so-called LC resonance circuit including an inductor 27, a capacitor 28, and a resistor 29. Therefore, its resonance frequency is constant, for example, 76 MHz to 90 MH at the time of frequency modulation broadcast reception.
The frequency is selected to be 83 MHz, which is the center frequency of z, and about 1000 kHz, which is the center frequency of approximately 531 kHz to 1611 kHz when receiving amplitude modulated broadcasting.

In such a configuration, when a frequency-modulated broadcast having a relatively small frequency change width is received, the phase difference between the reference signal from the phase shifter 6 and the reference signal from the voltage-controlled oscillation circuit 5 is demodulated. The range can be set to 90 ± 2 to 3 degrees at which the audio signal can be reproduced by the circuit 11 without distortion.

On the other hand, when an amplitude-modulated broadcast having a relatively large frequency change width is received, for example, while the resonance frequency is set to 1000 kHz as described above, the frequency of the oscillation signal from the voltage-controlled oscillation circuit 5 is increased. 500kHz
In the case of, the phase difference deviates from the aforementioned 90 degrees to nearly 10 degrees, and the reproduced sound is distorted. Also, the demodulation circuit 11 is configured to perform phase correction by digital signal processing or the like on both outputs after the orthogonal transformation from the multipliers 7 and 8 input via the LPFs 9 and 10 to suppress the occurrence of the distortion. Even in this case, there is a problem that the phase shift between the outputs from the multipliers 7 and 8 is large and correction cannot be performed.

SUMMARY OF THE INVENTION It is an object of the present invention to output a reference signal which is exactly 90 degrees out of phase with respect to an input reference signal over the entire reception frequency band even when the reception frequency change width is large. An object of the present invention is to provide a direct detection receiver that includes a phase shifter that can perform demodulation with less distortion.

[0010]

According to the present invention, there is provided a first reference signal generating means for generating a first reference signal having a frequency corresponding to a tuning voltage from a tuning control circuit, and the first reference signal and the tuning voltage being input. And a second reference signal having a resonance frequency that changes in accordance with the tuning voltage and generating a second reference signal having a phase different from that of the first reference signal by 90 degrees.
Reference signal generating means, first and second mixing means for mixing the received signal and the first and second reference signals, respectively, and passing predetermined frequency bands from outputs of the first and second mixing means, respectively. First and second filter means, and demodulation means for mutually processing both outputs of the first and second filter means to obtain a demodulated signal, wherein the first and second reference signal generation means have the same characteristics, respectively. And a variable capacitance diode whose capacitance varies in accordance with the tuning voltage.

[0011]

[0012]

According to the present invention, the first reference signal generating means generates a first reference signal having a frequency corresponding to a tuning voltage from a tuning control circuit realized by a phase lock loop circuit or the like. Is mixed with the received signal in the first mixing means. Further, the first reference signal is provided to a second reference signal generating means, and the second reference signal generating means changes a resonance frequency in accordance with the tuning voltage, and accordingly, inputs the first reference signal. And the phase of the first reference signal is converted by 90 degrees and output as the second reference signal. The second reference signal is mixed with the received signal in second mixing means.

The outputs of the first and second mixing means are filtered by a first and second filter means in a predetermined frequency band such as an audio frequency band, and input to a demodulation means. The demodulation means derives a demodulated signal such as an audio signal by obtaining a root mean square of the outputs of the first and second filter means, and the demodulated signal is acousticized via a power amplifier and a speaker.

[0014] The first and second reference signal generating means include:
A so-called LC resonance circuit or the like including an inductor and a variable capacitance diode is provided. By changing the capacitance of the variable capacitance diode according to the tuning voltage, it is possible to set a desired resonance frequency. it can. Therefore, the first and second reference signal generating means are constituted by the inductors and the variable capacitance diodes which are parts having the same characteristics as described above, and the constants are selected to be equal to each other. From each other, the mutual phase required for direct detection is exactly 90
Different reference signals can be obtained, and demodulated signals with less distortion can be obtained.

[0015]

FIG. 1 is a block diagram showing an electrical configuration of a direct detection receiver 51 according to one embodiment of the present invention. The received signal received by the antenna 52 is transmitted to a high-frequency amplifier 53
To the orthogonal transform circuit 54 via

The orthogonal transform circuit 54 oscillates at a frequency corresponding to the tuning voltage from the tuning control circuit 55, and includes a voltage-controlled oscillation circuit 56 as first reference signal generating means and a voltage-controlled oscillation circuit. The first reference signal from the circuit 56 is multiplied by the reception signal from the high-frequency amplifier circuit 53, and a multiplier 57 serving as first mixing means is shifted by 90 degrees from the first reference signal as a second reference signal. Derived,
A phase shifter 58 as a second reference signal generating means, and a multiplier 59 as a second mixing means for multiplying the second reference signal from the phase shifter 58 by the received signal are configured. .

The outputs from the multipliers 57 and 59 are converted into digital signals by analog / digital converters 63 and 64 after an audio signal band to be demodulated is filtered by LPFs 61 and 62, respectively. Is input to The correction circuit 65 performs level correction and phase correction between outputs from the analog / digital converters 63 and 64 as described later, and outputs the result to the demodulation circuit 66. Demodulation circuit 6
6 performs digital signal processing as described later based on the output from the correction circuit 65, demodulates the digital audio signal, and outputs the digital audio signal to the digital / analog converter 67. An analog audio signal is output from the digital / analog converter 67, and the audio signal is converted into a sound from a speaker 69 via a power amplifier 68.

The tuning control circuit 55 comprises a phase lock loop circuit of a so-called electronic tuning type tuner.
A programmable counter 71 for dividing the frequency of the oscillation signal of the voltage-controlled oscillation circuit 56;
Control circuit 72 for controlling the frequency division ratio of the above, a crystal oscillator 73 for oscillating at a reference frequency, a frequency dividing circuit 74 for dividing the oscillation signal of the crystal oscillator 73, and an output from the programmable counter 71. And a phase comparator 75 for comparing the phase of the output from the frequency divider 74 with a tuning voltage of a DC voltage level corresponding to the comparison result of the phase comparator 75. And an LPF 76 provided to the phase shifter 58.

When the direct detection receiver 51 is used for receiving an amplitude-modulated broadcast, the frequency-divided output of the oscillation signal of the crystal oscillator 73 is used as a frequency interval of the amplitude-modulated broadcast, that is, a so-called channel. The frequency is divided so as to be 9 kHz, which is the span, and output.

In the orthogonal transform circuit 54, the voltage controlled oscillation circuit 56 includes an inductor L1 and the inductor L1.
1 and a tuning circuit that includes a DC cut capacitor C1 connected in series to the inductor 1 and a variable capacitance diode D1 connected in parallel to the inductor L1 and the capacitor C1. A tuning voltage via the line 77 is applied to the voltage control oscillation circuit 56 via a resistor R1, and a first reference signal having a frequency corresponding to the tuning voltage is supplied from a line 78 via a buffer 79 and a line 80. This is given to the multiplier 57.

The first reference signal via the buffer 79 is input to the phase shifter 58 via the line 81. The phase shifter 58 includes an inductor L2 and a variable capacitance diode D
2, a DC cut capacitor C2, and a resistor R3. The inductor L2 is connected to the buffer 7.
9 is provided between a line 81 for inputting the first reference signal from the phase shifter 58 to the phase shifter 58 and a line 82 for outputting the second reference signal from the phase shifter 58 to the multiplier 59. .
The line 82 is grounded via a series circuit of a DC cut capacitor C2 and a variable capacitance diode D2, and a resistor R3 is interposed in parallel with the series circuit. DC cut capacitor C2 and variable capacitance diode D
The connection voltage 83 via the line 77 is applied to a connection point 83 with the tuning signal R2 through a resistor R2.

In the voltage-controlled oscillator circuit 56 and the phase shifter 58, which are substantially the same as described above, the variable capacitance diodes D1 and D2 are constituted by so-called pair components having the same characteristics, and the inductors L1 and L2 and the DC By similarly selecting the constants of the cut capacitors C1 and C2,
By applying equal tuning voltages to each other via the resistors R1 and R2, the first and second reference signals can be oscillated signals whose phases are different from each other by 90 degrees.

That is, the first reference signal from the buffer 79 is e1, and the second reference signal output on the line 82 is e1.
2, the inductance and the resistance R of the inductor L2.
3, the transfer function of the phase shifter 58 can be expressed by the following equation (1) when the combined capacitance of the DC cut capacitor C2 and the variable capacitance diode D2 is C0. The characteristic can be expressed by Equation 2.

[0024]

E1 / e2 = 1 / {1−ω ² · L2 · C0 + jω (L2 / R3)}

[0025]

Expressed in Equation 2] ^{φ = tan -1 {(-ω ·} L2 / R3) / (1-ω 2 · L2 · C0)} Thus FIG phase characteristics, the phase phi as apparent from FIG. 2 -90 degrees when is 0 degrees when the omega = 0, the resonance point ω0 of ^{(ω 2 · L2 · C0 =} 1),
It is understood that when ω = ∞, the angle becomes −180 degrees.
In FIG. 2, the characteristic indicated by reference numeral α1 indicates the characteristic when the resistance value of the resistor R3 is relatively large, and the characteristic indicated by reference numeral α2 indicates that the resistance value of the resistor R3 is relatively small. It represents a certain characteristic.

Therefore, when the resistor R3 is not provided, the selectivity (Q) of the phase shifter 58 increases, and as shown by the reference numeral α1, the angular frequency ω of the first reference signal However, it can be understood that the phase of the second reference signal greatly changes only by slightly deviating from the resonance point ω0 of the phase shifter 58.

On the other hand, the smaller the resistance value of the resistor R3, the smaller the phase angle φ even if the angular frequency ω is farther from the resonance point.
Approaches −90 degrees, that is, the change in the phase angle φ with respect to the change in the angular frequency ω becomes gentler. Therefore, by setting the resistance value of the resistor R3 to a relatively small value, the angular frequency ω of the input first reference signal is set.
The second reference signal can be output with a phase shift of substantially 90 degrees with respect to the first reference signal even if the resonance point is shifted from the resonance point.

In this way, even if the frequency change width is relatively large, such as in the case of an amplitude-modulated broadcast wave, the phase shifter 5
8 can convert the phase of the first reference signal input from the voltage controlled oscillation circuit 56 by approximately 90 degrees and output the converted second reference signal. As a result, a demodulated output with little distortion can be obtained.

On the other hand, the correction circuit 65 and the demodulation circuit 6
6 is realized integrally by a so-called digital signal processor or the like. Therefore, these circuits 65 and 66
FIG. 3 is a functional block diagram showing a basic digital signal processing procedure. The correction circuit 65 generally includes an absolute value level correction unit 91, a phase correction unit 92, and a level correction unit 93.

The output ↑ E 1 of the analog / digital converter 63 is input to the multiplier 101 of the absolute value level corrector 91. In the following description, ↑ indicates a vector quantity. After the output ↑ E1a from the multiplier 101 is calculated into an absolute value by the absolute value calculator 102, only the low frequency component is extracted by the LPF 103. The output from LPF 103 is compared in comparator 104 with reference value ref from reference value generation source 105.

The switch 10 associated with the comparator 104
6 is provided. One of the individual contacts of the switch 106 is supplied with the coefficient 1 + a from the coefficient source 107, and the other individual contact is supplied with the coefficient 1-a from the coefficient source 108. ing. The comparator 104 has an LPF
When the output from the switch 103 is larger than the reference value ref, the switch 106 is conducted to the coefficient source 108 side, and when the output is less than the reference value ref, the switch 106 is conducted to the coefficient source 107 side. The output from the common contact of the switch 106 is
9 is given.

In connection with the multiplier 109, a delay unit 110
Is provided, and the previous operation result of the multiplier 109 is fed back via the delay unit 110. Multiplier 10
9 is provided to the multiplier 101 and is multiplied by the output ↑ E1. Therefore, as the output ↑ E1 is smaller, the coefficient 1 + a is raised to the power and the absolute value level of the output ↑ E1 is corrected.

The output ↑ E2 from the analog / digital converter 64 has the same configuration as the output ↑ E1. Corresponding parts are indicated by the same reference numerals with the addition of a suffix s. Therefore, the outputs ↑ E1, ↑ E2
Coefficient 1+ so that the absolute value levels of
a, 1-a are raised to the power, and thus the absolute value level correction unit 9
1, the outputs # E1a and # E2a corrected so that the absolute value levels of the outputs # E1 and # E2 become equal to each other.
Is output.

Output from the Absolute Value Level Correction Unit 91
E1a and ↑ E2a are input to the phase corrector 92, where the multiplier 111 calculates the inner product, and the LPF 112 filters low-frequency components. The inner product of the vector is 0 when forming 90 degrees, becomes + when it is smaller than 90 degrees, and becomes-when it is larger than 90 degrees. Therefore, the output from LPF 112 can be compared with reference value 0 in comparator 113 to determine whether the phase difference is greater than 90 degrees. The comparator 113 determines whether the switch 11
4 switching state.

One of the individual contacts of the switch 114 is provided with the coefficient -a from the coefficient source 115, and the other individual contact is provided with the coefficient + a from the coefficient source 116. The output from the common contact of the switch 114 is
7 and delayed by the delay unit 118
After being added to the previous output of 7, it is input to the multiplier 119.

If the sum is an angle to be corrected, that is, a difference larger than 90 degrees or smaller than 90 degrees of the phase difference between the outputs ΔE1a and ΔE2a, the difference θ is sin θ
Is equivalent to After a product of sin θ and the output ↑ E1a is calculated by a multiplier 119, the output ↑ E1a is calculated by an adder 120.
E2a is added to E2a to obtain a phase-corrected output ΔE2b. In this way, the phase difference between the output ↑ E1a from the multiplier 101 and the output ↑ E2b from the adder 120 is made exactly 90 degrees in the phase corrector 92 and output.

At the start of the process of the phase correction section 92, a constant 0 is stored in the delay unit 118, and the coefficient + a or -a is continuously calculated until the phase shift amount is reached. Then, the correction amount is accumulated by the number of times of correction. Therefore, as shown in FIG. 4, output {E1a and output}
When the phase difference from E2b is shifted from 90 degrees by θ and the absolute values are equal, the output ΔE21 obtained by adding the output ΔE1asin θ to the output ΔE2b becomes the output ΔE1a.
And a phase difference of 90 degrees. However, the case where θ is larger than 90 degrees is defined as −.

As is apparent from FIG. 4, the output ΔE2
b is added to the output ↑ E1asinθ to correct the phase difference to 90 degrees, the output ↑ E2 obtained by the correction is obtained.
The absolute value of 1 is smaller than the output ΔE2b. Therefore, a level correction unit 93 is provided to correct this level error. The level correction unit 93 is similar to the configuration of the absolute value level correction unit 91 described above, and the corresponding parts are indicated by the same reference numerals with the suffix p added.

The output .DELTA.E2b from the phase corrector 92 is input to an absolute value calculator 102p via a multiplier 101p, calculated to an absolute value, and then input to a comparator 104p via an LPF 103p. The comparator 104p is also provided with a reference value ref from the reference value generation source 105. The comparator 104p performs switching of the switch 106p according to which of the output from the LPF 103p and the reference value ref is larger. Control the state. Thus, the coefficient sources 107 and 108 are output from the switch 106p.
Is selectively output from the multiplier 109p, and the multiplier 109p passes through the delay unit 110p
After being multiplied by the previous output of p, the output ↑ E2b is multiplied by the multiplier 101p to obtain an output ↑ E2c having undergone phase correction and level correction.

The outputs {E1a,} from the correction circuit 65
E2c is input to the demodulation circuit 66, and each of the multipliers 12
After being multiplied by the square of 1,122, they are mutually added by the adder 123. The output from the adder 123 is
, And the received signal of the amplitude modulated broadcast can be directly detected and demodulated into an audio signal. The demodulated audio signal is converted to a digital / analog converter 6
After being converted into an analog audio signal at 7, the audio signal is converted from a speaker 69 through the power amplifier 68 to be sounded.

As described above, in the direct detection receiver 51 according to the present invention, the phase shifter 58 is configured in the same manner as the voltage controlled oscillation circuit 56, and its resonance frequency can be changed by the tuning voltage from the tuning control circuit 55. As a result, even if the amplitude modulation broadcast wave has a relatively large frequency change width in the reception frequency band, the second reference signal whose phase is exactly 90 degrees different from that of the first reference signal from the voltage controlled oscillator circuit 56 is obtained. A signal can be obtained, and generation of distortion in the demodulated audio signal can be suppressed.

Further, the correction circuit 65 performs the phase correction of the outputs # E1 and # E2 after the orthogonal transformation with higher accuracy and also performs the level correction, so that a demodulated audio signal with less distortion can be obtained. .

[0043]

As described above, according to the present invention, the first reference signal for generating two reference signals for direct detection is provided.
Since the tuning voltage from the tuning control circuit is commonly applied to the second reference signal generating means and the second reference signal generating means, the resonance frequency of the second reference signal generating means acting as a phase shifter is made to follow the frequency change of the first reference signal. From the second reference signal generating means, the phase is accurately adjusted to 9 with respect to the frequency change of the first reference signal.
The second reference signal shifted by 0 degrees can be obtained, and distortion can be prevented from being generated with respect to the demodulated signal by the direct detection method. In particular, according to the present invention, the first and second
The reference signal generating means is provided with an inductor and a variable capacitance diode, and each of the inductor and the variable capacitance diode is composed of the same specific component. Therefore, it is possible to accurately obtain reference signals differing by 90 degrees with a simple configuration. .

[Brief description of the drawings]

FIG. 1 shows a direct detection receiver 51 according to an embodiment of the present invention.
FIG. 2 is a block diagram showing an electrical configuration of the embodiment.

FIG. 2 is a graph showing a phase characteristic of a phase shifter 58;

FIG. 3 is a functional block diagram for explaining a digital signal processing procedure in a correction circuit 65 and a demodulation circuit 66.

FIG. 4 is a diagram for explaining a level error caused by phase correction by a phase correction unit 92 of the correction circuit 65;

FIG. 5 is a block diagram showing the electrical configuration of a typical prior art direct detection receiver 1.

[Explanation of symbols]

 Reference Signs List 51 Direct detection receiver 52 Antenna 53 High frequency amplifier circuit 54 Quadrature conversion circuit 55 Tuning control circuit 56 Voltage control oscillation circuit 58 Phase shifter 65 Correction circuit 66 Demodulation circuit 69 Speaker 91 Absolute value level correction unit 92 Phase correction unit 93 Level correction unit C1, C2 DC cut capacitor D1, D2 Variable capacitance diode L1, L2 Inductor R1 to R3 Resistance

Claims (1)

(57) [Claims] 1. A first reference signal generating means for generating a first reference signal having a frequency corresponding to a tuning voltage from a tuning control circuit, the first reference signal and a tuning voltage being inputted,
The resonance frequency changes according to the tuning voltage,
Second reference signal generating means for generating a second reference signal having a phase different from that of the first reference signal by 90 degrees, and first and second mixing means for mixing a received signal with the first and second reference signals, respectively. And first and second filter means for passing a predetermined frequency band from the output of the first and second mixing means, respectively, and both outputs of the first and second filter means are arithmetically processed to generate a demodulated signal. And a demodulating means for obtaining the direct detection receiver, wherein the first and second reference signal generating means are each constituted by an inductor having the same characteristics and a variable capacitance diode having a variable capacitance corresponding to the tuning voltage. .