JPH05152855A - Direct detection receiver - Google Patents

Abstract

PURPOSE:To attain the demodulation with less distortion by providing a phase shifter which outputs a reference signal whose phase is shifted accurately by 90 deg. with respect to an input reference signal from a voltage controlled oscillator circuit even when a reception frequency change width is large in the direct detection receiver to the receiver. CONSTITUTION:A phase shifter 58 shifting a phase of a 1st reference signal from a voltage controlled oscillator circuit 56 by 90 deg. and outputting a 2nd reference signal is formed similarly to the voltage controlled oscillator circuit 56, a tuning voltage from a tuning control circuit 55 realized by a phase locked loop circuit or the like is given to the voltage controlled oscillator circuit 56 and given to the phase shifter 58 thereby changing the resonance frequency of the phase shifter 58 corresponding to the oscillating frequency of the voltage controlled oscillator 56. Thus, two reference signals whose phase is accurately different by 90 deg. corresponding to the amplitude modulation broadcast wave having a large frequency amplitude are generated and a demodulation signal with less distortion is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct detection type receiver.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an electrical configuration of a typical prior art direct detection receiver 1. The reception signal received by the antenna 2 is given to the orthogonal transformation circuit 4 via the high frequency amplification circuit 3. Orthogonal transformation circuit 4
Is a voltage control oscillation circuit 5 that oscillates at a frequency corresponding to the tuning voltage from the tuning control circuit 20, a multiplier 7 that multiplies a reference signal from the voltage control oscillation circuit 5 and the received signal, and the reference. It is configured to include a phase shifter 6 for deriving a phase of a signal by shifting by 90 degrees, and a multiplier 8 for multiplying a reference signal from the phase shifter 6 by the received signal.

Outputs from the multipliers 7 and 8 are low-pass filters (hereinafter abbreviated as LPFs) LPFs 9 and 1, respectively.
The audio signal band to be demodulated at 0 is filtered and then input to the demodulation circuit 11. The demodulation circuit 11 includes a so-called digital signal processor and the like, and
An audio signal demodulated by, for example, obtaining the root mean square of the outputs from the PFs 9 and 10 is given to the speaker 13 via the power amplifier 12.

The tuning control circuit 20 is composed of a phase lock loop circuit of an electronic tuning type tuner, and a programmable counter 21 for dividing the oscillation signal of the voltage controlled oscillation circuit 5 and a division ratio of the programmable counter 21. A control circuit 22 for controlling, a crystal oscillator 23 that oscillates at a reference frequency, a frequency divider circuit 24 that divides the oscillation signal of the crystal oscillator 23, an output from the programmable counter 21, and a frequency divider circuit 24. A phase comparison circuit 25 for comparing the phase with the output from the phase comparison circuit 25, and an LPF 26 for giving an output of a DC voltage level corresponding to the comparison result of the phase comparison circuit 25 to the voltage controlled oscillation circuit 5 as a tuning voltage. ..

Therefore, when the frequency dividing ratio of the programmable counter 21 is changed by the control circuit 22, a phase difference occurs between the output from the programmable counter 21 and the output from the frequency dividing circuit 24, and this phase difference becomes zero. Thus, the tuning voltage is applied to the voltage controlled oscillator circuit 5. In this way, the broadcast of the desired frequency can be received.

[0006]

In the above-mentioned conventional technique, the phase shifter 6 is composed of a so-called LC resonance circuit including an inductor 27, a capacitor 28 and a resistor 29. Therefore, its resonance frequency is constant, and for example, 76 MHz to 90 MH when receiving frequency modulation broadcasting.
It is selected to be 83 MHz which is the center frequency of z, and about 1000 kHz which is the center frequency of 531 kHz to 1611 kHz when receiving amplitude modulation broadcasting.

With such a configuration, when receiving a frequency-modulated broadcast having a relatively small frequency change width, the phase difference between the reference signal from the phase shifter 6 and the reference signal from the voltage controlled oscillator circuit 5 is demodulated. The circuit 11 can set the range of 90 ± 2 to 3 degrees in which the audio signal can be reproduced without distortion.

On the other hand, at the time of receiving an amplitude modulation broadcast having a relatively large frequency change width, the frequency of the oscillation signal from the voltage controlled oscillator circuit 5 is, for example, in the state where the resonance frequency is set to 1000 kHz as described above. 500 kHz
, The phase difference deviates from 90 degrees by nearly 10 degrees, and the reproduced sound is distorted. Further, in the demodulation circuit 11, both outputs after the orthogonal transformation from the multipliers 7 and 8 input through the LPFs 9 and 10 are phase-corrected by digital signal processing or the like to suppress the occurrence of the distortion. Even in such a case, there is a problem that the phase shift between the outputs from the multipliers 7 and 8 is large and the correction cannot be performed.

An object of the present invention is to output a reference signal that is exactly 90 degrees out of phase with the input reference signal over the entire reception frequency band, even if the reception frequency change width is large. It is an object of the present invention to provide a direct detection receiver including a phase shifter capable of performing the above and capable of performing demodulation with less distortion.

[0010]

According to the present invention, first reference signal generating means for generating a first reference signal having a frequency corresponding to a tuning voltage from a tuning control circuit, and the first reference signal and the tuning voltage are input. A second reference signal whose resonance frequency changes in response to the tuning voltage and which is 90 degrees out of phase with the first reference signal.
Reference signal generating means, first and second mixing means for mixing the received signal with the first and second reference signals, respectively, and frequency bands determined in advance from the outputs of the first and second mixing means are passed. A direct detection receiver comprising: first and second filter means; and demodulation means for mutually processing both outputs of the first and second filter means to obtain a demodulated signal.

Further, the first and second reference signal generating means of the present invention are characterized by including an inductor and a variable capacitance diode whose capacitance changes in accordance with the tuning voltage.

[0012]

According to the present invention, the first reference signal generating means generates the first reference signal having a frequency corresponding to the tuning voltage from the tuning control circuit realized by a phase lock loop circuit or the like, and the first reference signal is generated. Is mixed with the received signal in the first mixing means. Further, the first reference signal is given to the second reference signal generating means, and the second reference signal generating means changes the resonance frequency in response to the tuning voltage, and therefore the first reference signal to be input. Becomes the optimum resonance frequency, and the phase of the first reference signal is converted by 90 degrees and output as the second reference signal. The second reference signal is mixed with the received signal in second mixing means.

The outputs of the first and second mixing means are filtered by a first and second filter means, respectively, into a predetermined frequency band such as an audio frequency band, and input to the demodulation means. The demodulation means derives a demodulation signal such as a voice signal by obtaining a root mean square of the outputs of the first and second filter means, and the demodulation signal is sonicated through a power amplifier and a speaker.

The first and second reference signal generating means are
For example, a so-called LC resonance circuit or the like including an inductor and a variable-capacitance diode is formed, and a desired resonance frequency is set by changing the capacitance of the variable-capacitance diode according to the tuning voltage. You can Therefore, by constructing the first and second reference signal generating means in the same manner and selecting the constants to be substantially equal to each other, the first and second reference signal generating means can be connected to each other, which are necessary for direct detection. It is possible to obtain a reference signal whose phase is exactly 90 degrees different,
A demodulated signal with little distortion can be obtained.

[0015]

1 is a block diagram showing the electrical construction of a direct detection receiver 51 according to an embodiment of the present invention. The received signal received by the antenna 52 is the high frequency amplifier circuit 53.
To the orthogonal transformation circuit 54.

The orthogonal transformation circuit 54 roughly oscillates at a frequency corresponding to the tuning voltage from the tuning control circuit 55, and a voltage control oscillation circuit 56 which is a first reference signal generating means, and this voltage control oscillation. The first reference signal from the circuit 56 is multiplied by the received signal from the high frequency amplifier circuit 53, and the multiplier 57 as the first mixing means and the phase of the first reference signal are shifted by 90 degrees to obtain a second reference signal. Derive,
It includes a phase shifter 58 which is a second reference signal generating means, and a multiplier 59 which is a second mixing means for multiplying the second reference signal from the phase shifter 58 and the received signal. ..

The outputs from the multipliers 57 and 59 are filtered by the LPFs 61 and 62 for audio signal bands to be demodulated, converted into digital signals by the analog / digital converters 63 and 64, and then corrected by the correction circuit 65. Entered in. The correction circuit 65 performs level correction and phase correction between the outputs from the analog / digital converters 63 and 64, and outputs it to the demodulation circuit 66, as described later. Demodulation circuit 6
6 performs digital signal processing as described below based on the output from the correction circuit 65, demodulates it into a digital audio signal, and then outputs it to the digital / analog converter 67. An analog audio signal is output from the digital / analog converter 67, and this audio signal is sonicated from the speaker 69 via the power amplifier 68.

The tuning control circuit 55 is composed of a phase lock loop circuit of a so-called electronic tuning tuner.
A programmable counter 71 that divides the oscillation signal of the voltage controlled oscillator circuit 56, and this programmable counter 71
Output from the programmable counter 71, a control circuit 72 for controlling the frequency division ratio, a crystal oscillator 73 that oscillates at a reference frequency, a frequency divider circuit 74 that divides the oscillation signal of the crystal oscillator 73. And a phase comparison circuit 75 for comparing the phases of the output from the frequency division circuit 74 and a tuning voltage of a DC voltage level corresponding to the comparison result of the phase comparison circuit 75 via the line 77 to the voltage controlled oscillation circuit 56 and The LPF 76 provided to the phase shifter 58 is included.

When the direct detection receiver 51 is used for receiving the amplitude modulation broadcast, the frequency dividing circuit 74 outputs the frequency division output of the oscillation signal of the crystal oscillator 73, that is, a so-called channel. The frequency is divided and output so that the span is 9 kHz.

In the orthogonal conversion circuit 54, the voltage controlled oscillator circuit 56 includes an inductor L1 and an inductor L1.
1 is composed of a direct current cut capacitor C1 connected in series, and a tuning circuit including the inductor L1 and a variable capacitance diode D1 connected in parallel with the capacitor C1. A tuning voltage via the line 77 is applied to the voltage controlled oscillator circuit 56 via a resistor R1, and a first reference signal having a frequency corresponding to the tuning voltage is applied from a line 78 via a buffer 79 and a line 80. It is given to the multiplier 57.

The first reference signal from the buffer 79 is input to the phase shifter 58 via the line 81. The phase shifter 58 includes an inductor L2 and a variable capacitance diode D.
2, a DC cut capacitor C2, and a resistor R3. The inductor L2 is the buffer 7
It is interposed between a line 81 for inputting the first reference signal from the phase shifter 58 to the phase shifter 58 and a line 82 for outputting the second reference signal from the phase shifter 58 to the multiplier 59. ..
The line 82 is also grounded via a series circuit of a DC cut capacitor C2 and a variable capacitance diode D2, and a resistor R3 is interposed in parallel with this series circuit. DC cut capacitor C2 and variable capacitance diode D
The tuning voltage via the line 77 is applied to the connection point 83 with the line 2 via the resistor R2.

In the voltage controlled oscillator circuit 56 and the phase shifter 58, which are constructed in substantially the same manner as described above, the variable capacitance diodes D1 and D2 are formed by so-called paired parts having the same characteristics, and the inductors L1 and L2 and the direct current are connected. By similarly selecting the constants of the cut capacitors C1 and C2,
By applying equal tuning voltages to each other via the resistors R1 and R2, the first and second reference signals can be oscillation signals whose phases are different from each other by 90 degrees.

That is, the first reference signal from the buffer 79 is e1, and the second reference signal output to the line 82 is e.
2, the inductance of the inductor L2 and the resistance R
When the resistance value of 3 is represented by the same reference numeral, and the combined capacitance of the DC cut capacitor C2 and the variable capacitance diode D2 is C0, the transfer function of the phase shifter 58 can be represented by Equation 1, and the phase The characteristic can be expressed by Equation 2.

[0024]

[Equation 1] e1 / e2 = 1 / {1-ω ² · L2 · C0 + jω (L2 / R3)}

[0025]

(2) φ = tan ⁻¹ {(−ω · L2 / R3) / (1-ω ² · L2 · C0)} Therefore, when the phase characteristic is represented in FIG. -90 degrees when is 0 degrees when the omega = 0, the resonance point ω0 of ^{(ω 2 · L2 · C0 =} 1),
It is understood that when ω = ∞, it becomes −180 degrees.
In FIG. 2, the characteristic indicated by reference numeral α1 represents the characteristic when the resistance value of the resistor R3 is a relatively large value, and the characteristic indicated by reference numeral α2 is the resistance value of the resistor R3 which is a relatively small value. Represents a characteristic at a certain time.

Therefore, when the resistor R3 is not provided, the selectivity (Q) of the phase shifter 58 becomes high, and as indicated by the reference symbol α1, the angular frequency ω of the first reference signal is increased. It will be understood that the phase of the second reference signal greatly changes even when the phase shifter 58 slightly deviates from the resonance point ω0 of the phase shifter 58.

On the other hand, the smaller the resistance value of the resistor R3, the phase angle φ even if the angular frequency ω is far from the resonance point.
Is approaching -90 degrees, that is, it is understood that the change of the phase angle φ with respect to the change of the angular frequency ω becomes gradual. Therefore, by setting the resistance value of the resistor R3 to a relatively small value, the angular frequency ω of the input first reference signal
Even if the resonance point is deviated, the second reference signal can be output with the phase shifted by about 90 degrees with respect to the first reference signal.

In this way, the phase shifter 5 can be used even when the frequency change width is relatively large as in the amplitude modulation broadcast wave.
Reference numeral 8 can convert the phase of the first reference signal input from the voltage controlled oscillator circuit 56 by approximately 90 degrees and output the second reference signal. As a result, a demodulated output with less distortion can be obtained.

On the other hand, the correction circuit 65 and the demodulation circuit 6
6 is integrated and is realized by a so-called digital signal processor or the like. Therefore, these circuits 65, 66
The basic digital signal processing procedure in the above is shown in the functional block diagram of FIG. The correction circuit 65 is generally configured to include an absolute value level correction unit 91, a phase correction unit 92, and a level correction unit 93.

The output ↑ E1 of the analog / digital converter 63 is input to the multiplier 101 of the absolute value level correction unit 91. In the following description, ↑ represents a vector quantity. The output ↑ E1a from the multiplier 101 is calculated into an absolute value by the absolute value calculator 102, and then only the low frequency component is extracted by the LPF 103. The output from the LPF 103 is compared with the reference value ref from the reference value generation source 105 in the comparator 104.

The switch 10 in relation to the comparator 104
6 is provided, one of the individual contacts of the switch 106 is provided with the coefficient 1 + a from the coefficient source 107, and the other of the individual contacts is provided with the coefficient 1-a from the coefficient source 108. ing. The comparator 104 is an LPF.
When the output from 103 is larger than the reference value ref, the switch 106 is conducted to the coefficient source 108 side, and when the output is less than the reference value ref, it is conducted to the coefficient source 107 side. The output from the common contact of the switch 106 is the multiplier 10
9 is given.

In connection with this multiplier 109, a delay device 110
Is provided, and the previous calculation result of the multiplier 109 is fed back through the delay device 110. Multiplier 10
The output from 9 is given to the multiplier 101 and is multiplied by the output ↑ E1. Therefore, the smaller the output ↑ E1, the more the coefficient 1 + a is raised, and the absolute value level of the output ↑ E1 is corrected.

The output ↑ E2 from the analog / digital converter 64 is also provided with the same structure as the output ↑ E1. Corresponding parts are designated by the same reference numerals with a subscript s. Therefore, the outputs ↑ E1 and ↑ E2
Of the coefficient 1+ so that the absolute value levels of
a, 1-a is raised to the power, and thus the absolute value level correction unit 9
From 1, the outputs ↑ E1a and ↑ E2a are corrected so that the absolute value levels of the outputs ↑ E1 and ↑ E2 are equal to each other.
Is output.

Output from the absolute value level correction section 91
E1a and ↑ E2a are input to the phase correction unit 92, the multiplier 111 calculates the inner product, and the LPF 112 filters low-frequency components. The inner product of the vectors is 0 when forming 90 degrees, becomes + when smaller than 90 degrees, and becomes − when larger. Therefore, the output from the LPF 112 can be compared with the reference value 0 in the comparator 113 to determine whether the phase difference is greater than 90 degrees. The comparator 113 switches the switch 11 according to the determination result.
4 changes the switching state.

The coefficient −a from the coefficient source 115 is applied to one individual contact of the switch 114, and the coefficient + a from the coefficient source 116 is applied to the other individual contact. The output from the common contact of the switch 114 is the adder 11
7 and is delayed by the delay device 118.
It is input to the multiplier 119 after being added to the previous output of 7.

When this sum is the angle to be corrected, that is, the difference greater than 90 degrees of the phase difference between the outputs ↑ E1a and ↑ E2a, or the difference is smaller than θ, sin θ
Equivalent to. The product of this sin θ and the output ↑ E1a is calculated by the multiplier 119, and then the output ↑ by the adder 120.
It is added to E2a to obtain the phase-corrected output ↑ E2b. In this way, in the phase corrector 92, the phase difference between the output ↑ E1a from the multiplier 101 and the output ↑ E2b from the adder 120 is accurately set to 90 degrees and output.

It should be noted that at the start of the processing of the phase correction section 92, the constant 0 is stored in the delay device 118, and the coefficient + a or -a is continuously calculated until the phase shift amount is reached. Then, the correction amount is accumulated by the number of corrections. Therefore, as shown in FIG. 4, output ↑ E1a and output ↑
When the phase difference from E2b deviates from 90 degrees by θ, and the absolute values are equal, the output ↑ E1a sin θ is added to the output ↑ E2b and the output ↑ E21 is output ↑ E1a.
And 90 degree phase difference. However, when θ is larger than 90 degrees, it is set to −.

As is clear from FIG. 4, the output ↑ E2
When the output ↑ E1asinθ is added to b and the phase difference is corrected to 90 degrees, the output ↑ E2 obtained by the correction
The absolute value of 1 is smaller than the output ↑ E2b. Therefore, the level correction unit 93 is provided to correct this level error. The level correction unit 93 is similar to the configuration of the absolute value level correction unit 91 described above, and corresponding parts are designated by the same reference numerals with a subscript p.

The output ↑ E2b from the phase corrector 92 is input to the absolute value calculator 102p via the multiplier 101p, calculated to an absolute value, and then input to the comparator 104p via the LPF 103p. The reference value ref from the reference value generation source 105 is also given to the comparator 104p, and the comparator 104p switches the switch 106p according to which of the output from the LPF 103p and the reference value ref is larger. Control the state. As a result, the coefficient sources 107 and 108 are output from the switch 106p.
The coefficient 1 + a or 1-a is selectively output from the multiplier 109p via the delay device 110p.
After being multiplied by the previous output of p, the output ↑ E2b is multiplied by the multiplier 101p, thus obtaining the output ↑ E2c which has been subjected to the phase correction and the level correction.

Outputs from the correction circuit 65 ↑ E1a, ↑
E2c is input to the demodulation circuit 66, and the multiplier 12
After being squared by 1,122, they are mutually added by the adder 123. The output from the adder 123 is the arithmetic unit 124.
Then, the square root is calculated and the received signal of the amplitude modulation broadcast can be directly detected and demodulated to an audio signal. The demodulated voice signal is converted to a digital / analog converter 6
After being converted into an analog voice signal in 7, the speaker 69 is sonicated through the power amplifier 68.

As described above, in the direct detection receiver 51 according to the present invention, the phase shifter 58 is constructed similarly to the voltage controlled oscillator circuit 56, and its resonance frequency can be changed by the tuning voltage from the tuning control circuit 55. With this configuration, the second reference signal whose phase is exactly 90 degrees different from the first reference signal from the voltage controlled oscillator circuit 56 is applied to the amplitude modulation broadcast wave having a relatively large frequency change width in the reception frequency band. It is possible to obtain a signal and suppress the occurrence of distortion in the demodulated audio signal.

Further, the correction circuit 65 corrects the phases of the outputs ↑ E1 and ↑ E2 after the orthogonal transformation with higher accuracy and also performs the level correction, so that a demodulated audio signal with less distortion can be obtained. ..

[0043]

As described above, according to the present invention, the first reference signal for generating two reference signals for direct detection is provided.
Since the tuning voltage from the tuning control circuit is commonly applied to the second reference signal generating means and the resonance frequency of the second reference signal generating means acting as a phase shifter is made to follow the frequency change of the first reference signal, From the second reference signal generating means, the phase is exactly 9 with respect to the frequency change of the first reference signal.
It is possible to obtain the second reference signal that is deviated by 0 degree, and it is possible to prevent distortion from occurring in the demodulated signal by the direct detection method.

[Brief description of drawings]

FIG. 1 is a direct detection receiver 51 according to an embodiment of the present invention.
3 is a block diagram showing the electrical configuration of FIG.

FIG. 2 is a graph showing a phase characteristic of a phase shifter 58.

FIG. 3 is a functional block diagram for explaining a digital signal processing procedure in a correction circuit 65 and a demodulation circuit 66.

FIG. 4 is a diagram for explaining a level error caused by a phase correction by a phase correction unit 92 of the correction circuit 65.

FIG. 5 is a block diagram showing an electrical configuration of a typical prior art direct detection receiver 1.

[Explanation of symbols]

 51 direct detection receiver 52 antenna 53 high frequency amplification circuit 54 quadrature conversion circuit 55 tuning control circuit 56 voltage control oscillation circuit 58 phase shifter 65 correction circuit 66 demodulation circuit 69 speaker 91 absolute value level correction unit 92 phase correction unit 93 level correction unit C1, C2 DC cut capacitor D1, D2 Variable capacitance diode L1, L2 Inductor R1-R3 Resistance

Claims (2)

[Claims] 1. A first reference signal generating means for generating a first reference signal having a frequency corresponding to a tuning voltage from a tuning control circuit, and the first reference signal and the tuning voltage are inputted,
The resonance frequency changes corresponding to the tuning voltage,
Second reference signal generating means for generating a second reference signal having a phase difference of 90 degrees from the first reference signal, and first and second mixing means for mixing a received signal and the first and second reference signals, respectively. A first and a second filter means for respectively passing a predetermined frequency band from the outputs of the first and second mixing means, and both outputs of the first and second filter means are mutually processed to obtain a demodulated signal. A direct detection receiver comprising: a demodulating means for obtaining the same. 2. The first and second reference signal generating means are configured to include an inductor and a variable capacitance diode whose capacitance changes in accordance with the tuning voltage. Direct detection receiver.