JP2629613B2 - Branch prediction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a branch prediction device for predicting a branch destination of a branch instruction in a data processing device.

[0002]

2. Description of the Related Art Conventionally, in this type of technique, the address of a fetched instruction is stored in a branch prediction table by pairing the address of the branch instruction itself and the predicted address of the branch destination when a branch occurs. The above table is indexed as a key to obtain a predicted branch destination address. In this conventional technique, the following problems occur when the operating frequency is improved and the number of entries in the branch prediction table that can be registered is increased in order to improve the performance of the processor. That is, in the register holding the instruction fetch address, the time from when the instruction address of the branch instruction is determined to when the branch destination prediction address obtained by indexing the branch prediction table is determined is the effective time when the branch occurrence prediction is successful. Branch instruction processing time. The circuit delay time required for this processing becomes a barrier to speeding up the processing of the branch instruction.

In order to solve this problem, a technique has been proposed in which, instead of using the instruction address of a branch instruction as an address to be stored as a key in a branch prediction table, the instruction address of the instruction immediately before the branch instruction is used. ing.
For example, in Japanese Patent Application Laid-Open No. 63-124135, the instruction address of the instruction immediately before the branch instruction and the branch destination address are stored in the branch prediction table, and the index of the branch prediction table is stored at the address immediately before the branch instruction. A technique for performing branch prediction at high speed is described.

[0004]

However, the prior art disclosed in Japanese Patent Application Laid-Open No. 63-1124135 has the following problems. Referring to FIG. 8, the branch prediction table stores the instruction address before the M instruction of the branch instruction as a key, and predicts "T" for predicting the occurrence of a branch or that no branch will occur as the direction of branch prediction. And a field for storing a predicted branch destination address. Here, as the past branch situation, the branch instruction 1 at the address “AAA” branches to the instruction address “BBB”, and further the address “BBB +
It is assumed that the sequence of branching from the branch instruction 2 of “1” to the instruction address “CCC” has been executed in advance. In this case, the address is registered in the branch prediction table using the instruction address of the instruction executed M instructions before the instruction address of the branch instruction as a key, and the address “AAA-M”
, The branch destination prediction address “BBB” is registered, and the branch destination prediction address “CCC” is registered using the address “AAA-M + 2” as a key.

In this state, if the actual branch destination address becomes "DDD" as a result of executing the branch instruction 1 again, the predicted branch destination address registered using the address "AAA-M" as a key is changed from "BBB". Changed to "DDD". The problem at this time is that the address "AAA
The branch destination prediction address “CCC” is registered using “−M + 2” as a key. In the execution sequence after the change, what is obtained using the address “AAA-M + 2” as a key is the predicted branch destination address corresponding to the instruction 11 at the address “DDD + 1”. However, the instruction 11 is not always a branch instruction. If the instruction 11 is not a branch instruction but branches to the predicted branch destination address, an illegal operation may occur. Further, even if the instruction 11 is a branch instruction, the branch destination is not always “CCC”, and in this case, some recovery processing is required.

Therefore, in the prior art disclosed in Japanese Patent Application Laid-Open No. 63-1124135, a normal operation cannot be guaranteed in the above-described case, and branch control becomes complicated or performance is reduced.

An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to increase the speed of a branch prediction process and prevent an illegal operation in branch control.

Another object of the present invention is to make it possible to flexibly set the timing for predicting a branch destination, so that a configuration according to the specifications of the system can be adopted.

[0009]

In order to solve the above-mentioned problems, a branch prediction apparatus according to the present invention holds a branch history of a branch instruction in association with an instruction M (M is a positive integer) before the branch instruction. Branch history holding means, a branch prediction address search means for searching the branch history holding means and predicting the next branchable address, and a branch for holding information on the branch prediction searched by the branch prediction address search means A prediction information holding unit, and a branch prediction unit configured to control not to use a branch prediction result held in the branch prediction information holding unit when a branch instruction having a branch is present in the M instructions executed immediately before. Control means.

Further, in the branch prediction apparatus of the present invention, the branch history holding means has a branch history address holding circuit having at least one entry and holding in each entry the address of the previous branch of the branch instruction; An instruction address holding circuit for holding an instruction address of an instruction immediately before a branch instruction corresponding to each entry of the address holding circuit;
An entry validity holding circuit that holds whether or not the contents of the entry are valid for each entry of the instruction address holding circuit; and the branch corresponding to each entry of the branch history address holding circuit. A branch occurrence holding circuit for holding whether or not a previous branch was caused by an instruction; and the branch prediction address search means searches the instruction address holding circuit by an instruction address of the instruction immediately before the branch instruction. A comparator for selecting information held in the entry validity holding circuit, the branch history address holding circuit, and the branch occurrence holding circuit based on a comparison result in the address comparator; and The information holding means is a branch prediction validity holding circuit for holding information from the entry validity holding circuit selected by the selector. A branch prediction address holding circuit that holds information from the branch history address holding circuit selected by the selector, and a branch prediction occurrence holding circuit that holds information from the branch occurrence holding circuit, The branch prediction control means holds that the branch prediction validity holding circuit is valid, and when the branch prediction occurrence holding circuit holds that occurrence is occurring, the instruction executed immediately before It is determined that the instruction is a branch instruction in which a branch has occurred, and control is performed so that the address held in the branch prediction address holding circuit is not used as a branch prediction result.

Further, in another branch prediction device of the present invention, the branch history holding means has at least one entry, and holds a branch history address holding circuit for holding an address of a previous branch of a branch instruction in each entry. An instruction address holding circuit that holds the instruction address of the instruction immediately before the branch instruction corresponding to each entry of the branch history address holding circuit, and that the contents of the entry are valid for each entry of the instruction address holding circuit An entry validity holding circuit that holds whether or not the branch prediction address search means, the branch prediction address search means, an address comparator that searches the instruction address holding circuit by the instruction address of the instruction immediately before the branch instruction, According to the comparison result in the address comparator, the entry validity holding circuit and the branch history address holding circuit A selector for selecting the held information, wherein the branch prediction information holding means holds a branch prediction validity holding circuit for holding information from the entry validity holding circuit selected by the selector; A branch prediction address holding circuit for holding information from the branch history address holding circuit selected by the selector, wherein the branch prediction control means holds that the branch prediction validity holding circuit is valid. If so, it is determined that the instruction executed immediately before is a branch instruction in which a branch has occurred, and control is performed so that the address held in the branch prediction address holding circuit is not used as a branch prediction result.

In another branch prediction apparatus of the present invention, the branch history holding means has at least one entry, and a branch history address holding circuit for holding, in each entry, an address of a previous branch instruction of a branch instruction. An instruction address holding circuit for holding an instruction address of the instruction M before the branch instruction corresponding to each entry of the branch history address holding circuit; and a content of the entry corresponding to each entry of the instruction address holding circuit. An entry validity holding circuit for holding whether or not the branch is valid; and a branch occurrence holding circuit for holding whether or not a previous branch was caused by the branch instruction corresponding to each entry of the branch history address holding circuit Wherein the branch prediction address search means includes an instruction address holding circuit that stores the instruction address of the instruction M before the branch instruction. An address comparator to be searched, and a selector for selecting information held in the entry validity holding circuit, the branch history address holding circuit, and the branch occurrence holding circuit based on a comparison result in the address comparator, The branch prediction information holding unit includes a branch prediction validity holding circuit that holds information from the entry validity holding circuit selected by the selector, and a branch prediction address holding circuit that stores information from the branch history address holding circuit selected by the selector. A branch prediction address holding circuit for holding information, and a branch prediction occurrence holding circuit for holding information from the branch occurrence holding circuit, wherein the branch prediction control means operates after the branch occurrence (M−
1) An instruction number counter for counting instructions is further provided, and when this instruction number counter is in the process of counting (M-1) instructions, or the branch prediction validity holding circuit is valid. And that the branch prediction occurrence holding circuit holds that the occurrence has occurred, it is determined that the branch instruction in which the branch occurred is present in the M instructions executed immediately before, and Control is performed so that the address held in the branch prediction address holding circuit is not used as a branch prediction result.

Further, in another branch prediction device of the present invention, the branch history holding means has at least one entry, and a branch history address holding circuit for holding an address of a previous branch of a branch instruction in each entry. An instruction address holding circuit for holding an instruction address of the instruction M before the branch instruction corresponding to each entry of the branch history address holding circuit; and a content of the entry corresponding to each entry of the instruction address holding circuit. An entry validity retaining circuit that retains whether the instruction is valid or not, wherein the branch prediction address retrieval means retrieves the instruction address retaining circuit according to the instruction address of the instruction M before the branch instruction. An address comparator, and the entry validity holding circuit and the branch history address holding based on a comparison result in the address comparator. And a selector for selecting the information held in the path and the branch prediction information holding means, wherein the branch prediction information holding means holds information from the entry validity holding circuit selected by the selector. And a branch prediction address holding circuit that holds information from the branch history address holding circuit selected by the selector,
The branch prediction control means further includes an instruction number counter for counting (M-1) instructions after the occurrence of the branch. When the instruction number counter is in the course of counting (M-1) instructions, Alternatively, when the branch prediction validity holding circuit holds that the branch prediction address holding circuit is valid, it is determined that the branch instruction in which the branch has occurred is present in the M instructions executed immediately before and the branch prediction address holding circuit is held. Control is performed so that the address held in the circuit is not used as a branch prediction result.

In another branch prediction device of the present invention, the branch prediction control means considers that a branch has occurred even when a branch prediction is incorrect, and stores the address held in the branch prediction address holding circuit. Control not to use as a branch prediction result.

In another branch prediction apparatus according to the present invention, the branch history holding means is configured to determine whether a branch prediction for a branch instruction is erroneous and that the M branch instructions executed immediately before the branch instruction have a different one. If there is no other branch instruction in which the branch has occurred, the instruction address of the instruction M instructions before the instruction address of the branch instruction whose branch prediction is incorrect is held in the instruction address holding circuit and the corresponding entry is stored. The branch history address holding circuit holds the branch destination instruction address at the time of the most recent branch.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the branch prediction device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a data processing apparatus to which the present invention is applied is a processing apparatus 18 which operates in a pipeline.
And an instruction cache 17. The instruction cache 17 is accessed based on the value of the prefetch instruction counter 1, and the instruction cache load data 19 is written or the instruction cache 3 is read. The value of the prefetch instruction counter 1 is held in the fetch instruction counter 2, and together with the instruction in the instruction register 3,
8 given. The instruction register 3 also holds a valid bit indicating whether or not a valid instruction word is included.
The processing unit 18 executes various operation instructions and also executes a branch instruction. When the processor 18 executes a branch instruction, it is determined whether or not a branch of the branch instruction has occurred or whether or not the branch prediction has been successful, and a branch destination address as an execution result of the branch instruction is generated. I do. The branch prediction failure is output via a signal line 38, and the branch destination address is output via a signal line 23. Further, the processing device 18 outputs a hold signal through a signal line 37 as necessary.

On the other hand, the branch prediction table is composed of a comparison address register group 4 and a branch destination prediction address register group 5 each having N entries, and the branch instruction is stored in the comparison address register group 4 using the address of the branch instruction itself as a comparison address. The branch destination predicted address in the case of occurrence is stored in the branch destination predicted address register group 5 such that the corresponding addresses are paired. The comparison address register group 4 includes a valid bit field indicating whether or not each entry contains a valid instruction word. The branch destination prediction address register group 5 includes a T / N field for storing “T” for predicting the occurrence of a branch or “N” for predicting that a branch will not occur as the direction of branch prediction. At the time of new registration in the branch prediction table, a registration activation signal 20 is sent via the decoder 9, and the registration address 21 and the branch destination prediction address 22 correspond to the comparison address register group 4 and the branch destination prediction address register group 5, respectively. Stored in the entry.

The comparator 11 is a circuit for comparing each entry of the comparison address register group 4 of the branch prediction table with the value of the prefetch instruction counter 1. The comparison result is sent to the branch prediction table output selection control circuit 14. Sent. As a result, the branch prediction table is indexed by the registered address.

Branch prediction table output selection control circuit 14
Receives the comparison result 28 of the comparator 11 and the hold signal 37 from the processing unit 18 and generates a control signal 39 for the selectors 12 and 13 and a mask signal 41 for the branch destination prediction address valid register 6.

Referring to FIG. 2, when there is a hold instruction 37 from the processor 18, that is, when the hold signal 3
7 is “1”, the branch prediction table output selection control circuit 14 controls the selectors 12 and 13 so that the branch destination prediction address valid register 6 and the branch destination prediction address register 7 maintain the current state, respectively. Control is exercised. If there is no hold instruction 37, the selectors 12 and 13 select an entry for which a match is detected in the comparison result 28 of the comparator 11. If no match is detected in the comparison result 28 of the comparator 11 without the hold instruction 37, the mask signal 41 becomes "0", and the AND gate 15 sets the branch destination prediction address valid register 6 to "0", that is, invalid. State. In the figure,
"X" means don't care, that is, any value is acceptable.

The prefetch instruction counter input selection control circuit (hereinafter, referred to as a “PIC selection control circuit”) 16 outputs a valid bit field output signal 36 of the instruction register 3 and
An output signal 30 of the branch destination prediction address valid register 6;
An output signal 40 of the branch prediction direction field of the branch destination prediction address register 7, a hold instruction signal 37 from the processing device 18, and a branch prediction failure signal 38 from the processing device 18.
, The control signal 32 to the PIC input selector 10 and the mask signal 42 of the branch destination prediction address valid register 6 are generated.

Referring to FIG. 3, PIC selection control circuit 1
6 is a selector 10 that sets the recovery address 23 when the branch prediction fails, the current prefetch address 25 when the branch is held, the prediction address 26 when the prediction is possible, and the next instruction address 24 otherwise. Control. Then, when the recovery address 23 or the prediction address 26 is selected in the above, the PIC selection control circuit 16 sets the mask signal 42 to “0” to make the branch destination prediction address valid register 6 invalid. That is, the case where the recovery address 23 or the prediction address 26 is selected is a case where the sequence of instructions is not continuous, and in this case, it becomes impossible to obtain the branch destination prediction address for the M instructions after branching. . However, in the first embodiment, it is assumed that M = 1.

When the prediction failure signal 38 is "1", the branch prediction is failed, when the hold signal 37 is "1", the hold has occurred in the processor 18, and the prediction valid signal 30 is "1". Means that the branch destination prediction address of the branch destination prediction address register 7 is valid.
When "0" is "1", the direction in which the branch occurs is predicted, and when the instruction valid signal 36 is "1", the instruction word in the instruction register 3 is valid. Also, it is assumed that all instruction words are 4 bytes.

Next, the operation of the first embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 4, since it is assumed that M = 1 in this embodiment, the instruction is registered in the branch prediction table using the instruction address of the instruction immediately before the branch instruction as a key. Also, it is assumed that the execution of the instruction proceeds according to the arrow with respect to the arrangement of the instruction in the memory or the instruction cache. Further, it is assumed that no hold occurs for a subsequent instruction in each instruction.

Referring to FIG. 5, there is shown a diagram showing the operation when the instruction sequence of FIG. 4 is executed. In FIG. 5, the value of the prefetch instruction counter 1, the instruction word of the instruction register 3, and the value of the branch destination prediction address valid register 6 are shown. And the predicted branch destination address of the predicted branch destination address register 7.

First, at time 0, it is assumed that the prefetch instruction counter 1 holds the initial value "AAA" and the branch destination prediction address valid register 6 holds the initial value "0". Thereafter, the prefetch instruction counter 1 is sequentially incremented until time 5, and the corresponding instruction is held in the instruction register 3 with a delay of 1T.

At time 4, the address BBB is indexed as a branch destination prediction address. As a result, at time 5, “BBB” is held in the branch destination prediction address register 7 and “1” is stored in the branch destination prediction address valid register 6. Will be retained. Thereby, the PIC selection control circuit 16 selects the selector 1
0 to select the prediction address 26. As a result, at time 6, the prefetch instruction counter 1 sets "BB
B ”is held. Further, at time 5, the PIC selection control circuit 16 sets the mask signal 42 to “0”.
Is forcibly set to "0". This compulsory processing is necessary to prevent an erroneous operation at the instruction 6 of the instruction address BBB. This is because the address obtained in the branch destination prediction address register 7 at the time 6 is the instruction address “X
This is a branch destination prediction address when the instruction of “XX + 4” is a branch instruction. When a branch occurs from the instruction address “XXX” to the instruction address “BBB” as in the present execution sequence, the branch destination prediction address is used. This is because it must not be used.

Thereafter, the instruction is executed in the same manner, but the address "C" is given by the branch instruction at the address "YYY".
When a branch occurs at the "CC" branch instruction, as described above,
For a branch instruction at address "CCC", a predicted branch destination address cannot be obtained. Therefore, it is considered that a branch does not occur, and the addresses “CCC + 4”,
Proceed with "CCC + 8". When the wrong branch prediction is performed as described above, the processor 18 detects the branch prediction failure, cancels the instruction that should not be executed, and sends the recovery address.
Execution is resumed from the instruction at the address DDD.

As described above, according to the branch predicting apparatus of the first embodiment of the present invention, by using the address immediately before the branch instruction as a key for registration in the branch prediction table, the branch prediction processing is performed. And at the same time, when the branch occurs, the branch destination prediction address valid register 6 is forcibly reset by the mask signal 42, so that the branch prediction immediately after the occurrence of the branch can be suppressed and the illegal operation can be prevented. .

Next, a second embodiment of the branch prediction apparatus of the present invention will be described in detail with reference to the drawings.

The second embodiment of the present invention is the same as that of the first embodiment except that the branch destination prediction address register group 5 does not include a field for specifying the direction of branch prediction. In this embodiment, the comparison address register group 4
If the value of the valid bit field indicates "valid", it operates as if the corresponding entry of the branch destination prediction address register group 5 is predicted in the branch occurrence direction.

Referring to FIG. 6, the PIC selection control circuit 16 according to the second embodiment of the present invention does not consider the branch prediction direction, unlike the first embodiment of FIG. Accordingly, in the first embodiment, the next address 24 is selected when the prediction is made that the branch does not occur, but in the present embodiment, the prediction address 26 is selected regardless of the prediction direction.

As described above, according to the branch prediction apparatus of the second embodiment of the present invention, the configuration of the branch prediction table is simplified by registering the branch prediction table only when a branch occurs. Furthermore, the control of the instruction address can be simplified, and the speeding up of the branch prediction process and the stable operation can be ensured more efficiently.

Next, a third embodiment of the branch prediction device of the present invention will be described in detail with reference to the drawings.

The third embodiment of the present invention differs from the third embodiment in that an instruction counter is provided to count the number of instructions after branching.
This is the same as that of the first embodiment. That is, in the first embodiment, the branch destination prediction address is registered by using the instruction address of the instruction immediately before the branch instruction as a key, but in the present embodiment, this is set to the instruction M instructions before the branch instruction. Is registered using the instruction address as a key. For this reason, in the present embodiment, an instruction number counter for subtracting the value (M-1) for each instruction is provided in order not to use the branch destination prediction address for M instructions after the occurrence of the branch. .

Referring to FIG. 7, the PIC selection control circuit 16 according to the third embodiment of the present invention inputs the value of the instruction number counter, and when this value is 1 or more, the mask signal 4
2 is forcibly set to "0". When a branch occurs, a value (M-1) is set in the instruction number counter to suppress branch prediction for M instructions after the branch.

As described above, according to the branch predicting apparatus of the third embodiment of the present invention, by using the address M instructions before the branch instruction as a key for registration in the branch prediction table, the branch prediction is performed. Higher processing speed and stable operation can be realized more flexibly.

In the above embodiment, the structure of the fully associative branch prediction table is premised. However, it is also conceivable that the set associative structure is adopted. Furthermore, in a set associative configuration,
It is also conceivable to adopt a configuration in which the address array to be compared is shared with the address array of the instruction cache.

[0041]

As is apparent from the above description, according to the present invention, the branch prediction processing is accelerated by using the address M instructions before the branch instruction as a key for registration in the branch prediction table, and When a branch occurs, the branch prediction for M instructions after the occurrence of the branch can be suppressed to prevent illegal operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a branch prediction device of the present invention.

FIG. 2 is a diagram illustrating an operation of a branch prediction table output selection control circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an operation of a prefetch instruction counter input selection control circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram for explaining an instruction sequence in the branch prediction device according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating an operation of the branch prediction device according to the first embodiment of this invention.

FIG. 6 is a diagram illustrating an operation of a branch prediction table output selection control circuit according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating an operation of a branch prediction table output selection control circuit according to a third embodiment of the present invention.

FIG. 8 is a diagram for explaining a problem in the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 prefetch instruction counter 2 fetch instruction counter 3 instruction register 4 comparison address register group 5 branch destination prediction address register group 6 branch destination prediction address valid register 7 branch destination prediction address register 8 adder 9 registration entry selection decoder 10 selector 11 comparator 12 , 13 selector 14 branch prediction table output selection control circuit 15 AND gate 16 prefetch instruction counter input selection control circuit 17 instruction cache 18 processing unit

Claims (5)

(57) [Claims] 1. The branch history of a branch instruction is stored in M
(M is a positive integer) a branch history holding unit that holds the instruction in association with the preceding instruction, a branch prediction address search unit that searches the branch history holding unit and predicts an address that can be taken next, A branch prediction information holding unit for holding information relating to a branch prediction searched by the address search unit; and a branch instruction where a branch has occurred among the M instructions executed immediately before, the branch prediction information holding unit. Branch prediction control means for controlling not to use the held branch prediction result. 2. A branch history address holding circuit having at least one entry and holding in each entry the address of a previous branch instruction, and a branch history address holding circuit corresponding to each entry of the branch history address holding circuit. And an instruction address holding circuit for holding the instruction address of the instruction immediately before the branch instruction, and an entry validity holding for each entry of the instruction address holding circuit whether or not the contents of the entry are valid And a branch occurrence holding circuit that holds whether or not a previous branch has occurred by the branch instruction corresponding to each entry of the branch history address holding circuit. An address comparator for searching the instruction address holding circuit according to the instruction address of the instruction immediately before the branch instruction; A selector for selecting information held in the entry validity holding circuit, the branch history address holding circuit, and the branch occurrence holding circuit according to the comparison result in the branch prediction information holding means. A branch prediction validity holding circuit that holds information from the entry validity holding circuit selected by: a branch prediction address holding circuit that holds information from the branch history address holding circuit selected by the selector; A branch prediction occurrence holding circuit for holding information from the branch occurrence holding circuit, wherein the branch prediction control means holds that the branch prediction validity holding circuit is valid, and If the holding circuit holds that the branch has occurred, it is determined that the instruction executed immediately before is the branch instruction in which the branch has occurred, and the branch prediction address storage is performed. Branch predicting apparatus according to claim 1, wherein the controlling the address held in the circuit so as not to use as a branch prediction result. 3. A branch history address holding circuit having at least one entry and holding in each entry the address of a previous branch of a branch instruction, and a branch history address holding circuit corresponding to each entry of the branch history address holding circuit. And an instruction address holding circuit for holding the instruction address of the instruction immediately before the branch instruction, and an entry validity holding for each entry of the instruction address holding circuit whether or not the contents of the entry are valid An address comparator for searching the instruction address holding circuit according to the instruction address of the immediately preceding instruction of the branch instruction, and the entry according to a comparison result in the address comparator. A selector for selecting information held in the validity holding circuit and the branch history address holding circuit. The branch prediction information holding unit includes a branch prediction validity holding circuit that holds information from the entry validity holding circuit selected by the selector, and a branch prediction address holding circuit that stores information from the branch history address holding circuit selected by the selector. A branch prediction address holding circuit for holding information, and the branch prediction control means, when holding that the branch prediction validity holding circuit is valid, the instruction executed immediately before 2. The branch prediction apparatus according to claim 1, wherein it is determined that the generated branch instruction is a branch instruction, and control is performed such that the address held in the branch prediction address holding circuit is not used as a branch prediction result. 4. A branch history address holding circuit having at least one entry and holding in each entry the address of a previous branch instruction, and a branch history address holding circuit corresponding to each entry of the branch history address holding circuit. And an instruction address holding circuit for holding the instruction address of the instruction M before the branch instruction, and for each entry of the instruction address holding circuit, whether or not the contents of the entry are valid. A branch validity holding circuit, and a branch occurrence holding circuit for holding whether or not a previous branch has occurred by the branch instruction corresponding to each entry of the branch history address holding circuit; Means for searching the instruction address holding circuit according to the instruction address of the instruction M before the branch instruction; A selector for selecting information held in the entry validity holding circuit, the branch history address holding circuit, and the branch occurrence holding circuit based on a comparison result in a comparator, wherein the branch prediction information holding means includes: A branch prediction validity holding circuit for holding information from the entry validity holding circuit selected by the selector, and a branch prediction address holding circuit for holding information from the branch history address holding circuit selected by the selector And a branch prediction occurrence holding circuit that holds information from the branch occurrence holding circuit, and the branch prediction control unit further includes an instruction number counter that counts (M−1) instructions after the branch occurrence. If the instruction number counter is in the course of counting (M-1) instructions, or holds that the branch prediction validity holding circuit is valid, On the other hand, when the branch prediction occurrence holding circuit holds that the branch is occurring, the branch prediction address holding circuit is determined by determining that the branch instruction in which the branch has occurred exists in the M instructions executed immediately before. 2. The branch prediction apparatus according to claim 1, wherein the control is performed such that the address held in the branch is not used as a branch prediction result. 5. A branch history address holding circuit having at least one entry, wherein each entry holds an address of a previous branch of a branch instruction, and a branch history address holding circuit corresponding to each entry of the branch history address holding circuit. And an instruction address holding circuit for holding the instruction address of the instruction M before the branch instruction, and for each entry of the instruction address holding circuit, whether or not the contents of the entry are valid. An address validator that searches the instruction address holding circuit by the instruction address of the M-th previous instruction of the branch instruction; A selector for selecting information held in the entry validity holding circuit and the branch history address holding circuit according to a comparison result A branch prediction information holding unit that holds information from the entry validity holding circuit selected by the selector, and the branch history address selected by the selector. A branch prediction address holding circuit for holding information from a holding circuit, wherein the branch prediction control means further includes an instruction number counter for counting (M-1) instructions after the occurrence of the branch; Is being counted for (M-1) instructions, or if the branch prediction validity holding circuit holds that it is valid, the M instructions executed immediately before 2. The method according to claim 1, wherein it is determined that there is a branch instruction in which a branch has occurred, and the address held in the branch prediction address holding circuit is controlled so as not to be used as a branch prediction result. Prediction device.