JPH06243043A - Entry clearing device for address conversion buffer - Google Patents

Abstract

PURPOSE:To invalidate whole ATB entries, to considerably shorten the time of an ATB clearing processing and to improve ATB access performance by updating an ATB clearing instruction count value by means of an ATB whole entry clearing instruction. CONSTITUTION:When an ATB index request is given to an address in a state where it is registered in ATB, a value registered in a count value registration register 2 is the same as the value of a count field 4a in an ATB key part 4 if the ATB clearing instruction is not given until indexing is executed after the address is registered in ATB. Thus, it is judged to be an ATB unit. When an ATB clearing instruction is given until indexing is executed after a prescribed address is registered in ATB, the value registered in the count value registration register 2 differs from the value of the count field 4a in the ATB key part 4. Thus, it is judged to be an ATB mishit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation buffer entry clearing device for clearing an entry in an address translation buffer which holds an address translation pair of a logical address and a real address.

[0002]

2. Description of the Related Art Conventional entry clearing means of an address translation buffer (ATB) for holding an address translation pair of a logical address and a real address clears all entries of the ATB. At this time, the valid flags of all entries are reset by one clear request.

[0003]

In the conventional entry clearing means as described above, when clearing all the entries in the ATB, it is necessary to repeat the execution of resetting the valid flag by the number of ATB entries. The ATB cannot be used while the entry clearing process is being executed, and thus the ATB access performance is deteriorated.

[0004]

SUMMARY OF THE INVENTION An address translation buffer entry clear device according to the present invention includes a clear instruction counting section for counting the number of clear instructions for an address translation buffer that holds an address translation pair of a logical address and a real address. A count value holding unit that holds a count value in the clear instruction counting unit for each entry of the address translation buffer; and a count value in the clear instruction counting unit when registering the address translation pair in the clear instruction counting unit. A count value registration unit to be registered in a count value holding unit compares the count value registered in the entry of the address translation buffer with the count value of the clear instruction count unit when indexing the address translation buffer, and compares them. The en indexed when there is no match Or a micro instruction for resetting valid flags of all entries in the address translation buffer when the clear instruction counting section overflows. Is provided with a microinstruction reset unit that resets the valid flags of all entries in the address translation buffer, or a clear instruction count unit that counts the number of entries in the address translation buffer as a basic cycle, and A clear instruction reset unit is provided for resetting the valid flag of the entry of the address conversion buffer whose address is the count value of the clear instruction count unit.

[0005]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing the first embodiment of the present invention, and FIG. 2 is a format diagram showing the contents of the ATB key portion of the embodiment of FIG.

In FIG. 1, the clear account unit 1 has 8
It has a bit count value registration register 2 and an 8-bit cyclic +1 counter 3, and the count value registration tester 2 adds +1 by an ATB clear instruction signal.
The output signal of the counter 3 is set. Address translation buffer (AT
The ATB key unit 4 of B) is composed of a random access memory having 256 words in the number of entries, and has an 8-bit count field 4a for registering the output of the count value registration tester 2 and a valid flag for each entry of the ATB. Has a 1-bit V field 4b and a key address field 4c for registering a key address. When the V field 4b is "1", it indicates that a valid address translation pair of a logical address and a real address is registered in the corresponding entry, and when it is "0",
Indicates that a valid address translation pair has not been registered.
The count field 4a is used for the count value registration register 2
It has the same data width as.

The comparator 6 compares the output of the count value registration register 2 and the output of the count field 4a of the ATB key section 4, and outputs "1" when they match and does not match. In this case, "0" is output.

The comparator 7 compares the output of the key address part of the request address register 5 with the output of the key address field 4c of the ATB key part 4, and outputs "1" when they match. If they do not match, "0" is output.

The ATB hit decision section 8 inputs the outputs of the comparator 6 and the comparator 7 and the V field 4b of the ATB key section 4, and outputs "1" when all of them are "1", and otherwise. In the case of, "0" is output.

Next, the operation of the entry clearing device configured as described above will be described.

First, the operation when an ATB index request is generated while nothing is registered in the ATB will be described.

First, the ATB index address is set in the request address register 5. ATB key section 4 is A
Although it is indexed by the set address of the TB index addresses, in this state, since nothing is registered in the ATB key portion 4, "0" is output from the V field 4b. The ATB hit determination unit 8 uses the V field 4b
Is 0, the ATB judges that it is a mishit regardless of the outputs of the comparator 6 and the comparator 7, and outputs "0". At this time, the ATB index address is "A0", the key address of the ATB index address "A0" is "K0", and the set address is "S0".
If the value registered in the count value registration register 2 is set to “0”, the ATB mishit processing causes
In the entry of the set address "S0" of the ATB key section 4, the data shown in FIG. 2A, that is, "0" in the count field 4a, "1" in the V field 4b, and "K0" in the key address field 4c are written. be registered.

Next, the operation when the ATB index request is generated again for the same address "A0" while the data shown in FIG. 2A is registered in the ATB will be described.

First, the ATB index address is set in the request address register 5. ATB key section 4 is A
It is indexed by the set address of the TB index addresses, and the set address at this time is the previous ATB.
Since it is the same as the index address, it is "S0". Since the data shown in FIG. 2A is registered in the entry of the set address “S0” of the ATB key section 4, “0” is read from the count field 4a and “1” is written from the V field 4b. Key address field 4c
Outputs "K0". The comparator 6 outputs "1" because both the value registered in the count value registration register 2 and the value in the count field 4a are "0". The comparator 7 outputs "1" because the value of the key address of the request address register 5 and the value of the key address field 4c are both "K0". Since the outputs of the comparator 6, the comparator 7, and the V field 4b of the ATB key unit 4 are all "1", the ATB hit determination unit 8 determines that there is an ATB hit and outputs "1".

Next, in the state where the data shown in FIG. 2A is registered in the ATB, first, an ATB clear instruction is issued, and then an ATB index request is issued again to the same address "A0". The operation of will be described.

First, in response to an ATB clear instruction, the count value registration register 2 stores "0" in the +1 counter 3.
The value "1" that is counted up is set. next,
An ATB index request is generated and the ATB index address is set in the request address register 5. The ATB key section 4 is indexed by the set address of the ATB index address, and the set address at this time is
Since it is the same as the above ATB index address, "S0"
Is. Since the data shown in FIG. 2A is registered in the entry of the set address “S0” of the ATB key section 4, “0” is read from the count field 4a and “1” is written from the V field 4b. Key address field 4
“K0” is output from c. In the comparator 6, the value registered in the count value registration register 2 is “1”,
Since the value of the count field 4a is "0",
Output "0". The comparator 7 uses the key address value of the request address register 5 and the key address field 4
Since both the values of c are "K0", "1" is output.
The ATB hit determination section 8 determines that the outputs of the comparator 7 and the V field 4b of the ATB key section 4 are both "1", but the output of the comparator 6 is "0", so that the ATB is a mishit. Judges and outputs "0". At this time, since the value registered in the count value registration register 2 is "1", the entry of the set address "S0" of the ATB key section 4 is shown in FIG. Data, that is, "1" is registered in the count field 4a, "1" in the V field 4b, and "K0" in the key address field 4c.

Thus, when an ATB index request is generated for the same address while a certain address is registered in the ATB, an ATB clear instruction is issued between the time the address is registered in the ATB and the index is executed. If is not generated, the value registered in the count value registration register 2 and the value in the count field 4a of the ATB key section 4 are the same, so it is determined that the ATB hit. When an ATB clear instruction is issued between the time an address is registered in the ATB and the index is executed, the value registered in the count value registration register 2 and the value in the count field 4a of the ATB key section 4 are Since the values are different, it is judged as an ATB miss. Therefore, if the phase between the ATB clear instructions is one phase, interference between different phases does not occur, and it is possible to invalidate all the entries of the ATB.

FIG. 3 is a block diagram showing the second embodiment of the present invention, and FIG. 4 is a format diagram showing the contents of the ATB key portion of the embodiment of FIG.

The clear account section 11, the count value registration register 12, the +1 counter 13, the ATB key section 14, the count field 14a, the V field 14b, the key address field 14c, the request address register 15, the comparator 16 and the comparator of this embodiment are compared. Device 17 and ATB hit determination unit 1
The structure and operation of 8 are the same as the structure and operation of the corresponding parts in the embodiment of FIG.

The overflow detection circuit 19 detects an overflow and outputs "1" when the value of the count value register 12 becomes "255" and an ATB clear instruction is issued, and otherwise "0". Is output.

When the output of the overflow detection circuit 19 becomes "1", the all clear control circuit 20 resets the V fields 14b of all the entries of the ATB key section 14, so that the clear address generation circuit 22 and the selection circuit. 25 are controlled.

The clear address generation circuit 22 has an 8-bit clear address registration register 23 and an 8-bit cyclic +1 counter 24. The clear address generation circuit 22 receives 25 bits of the ATB key section 14 according to an instruction from the all clear control circuit 20.
A clear address corresponding to 6 entries is generated.

The selection circuit 25 uses the set address of the request address register 15 as the set address of the ATB key unit 14 or the clear address registration register 23 according to an instruction from the all clear control circuit 20.
Either the value of is used.

Next, regarding the operation of the entry clearing device configured as described above, the data shown in FIG. 4A is registered in the ATB, the value of the count value register 12 becomes "255", and the ATB clearing is performed. A case will be described in which an instruction is issued and an ATB index request is issued to the same address "A0" as the data shown in FIG. 4A.

First, when the ATB clear instruction is generated, the value of the count value registration register 12 becomes "0", and the overflow detection circuit 19 detects the overflow and outputs "1". The all clear control circuit 20 thereby controls the clear address generation circuit 22 to generate clear set addresses "0" to "255" for clearing all the entries in the ATB. At the same time, the all clear control circuit 20 controls the selection circuit 25 to select the clear address generation circuit 22 and supply the value of the clear address registration register 23 to the ATB key unit 14. A
The TB key unit 14 is thereby allowed to change the V of all entries.
Reset the field 14b. At this point, ATB
The data registered in the key portion 14 is the data shown in FIG. 4A, that is, the count field 14a is "0", the V field 14b is "1", and the key address field 14c is "K0". 4 (b), that is, the count field 14a is changed to "0", the V field 14b is changed to "0", and the key address field 14c is changed to "K0".

In this state, the AT is again sent to the same address.
When a B index request is generated, the ATB index address is set in the request address register 15. AT
The B key portion 14 is indexed by the set address of the ATB index address. Since the set address at this time is the same as the above ATB index address,
It is "S0". Since the data shown in FIG. 4A is registered in the entry of the set address "S0" of the ATB key section 14, "0" is read from the count field 14a and "1" is written from the V field 14b. "K0" is output from the key address field 14c. The comparator 16 outputs "1" because both the value registered in the count value register 12 and the value in the count field 14a are "0". The comparator 17 is
Since the value of the key address of the request address register 15 and the value of the key address field 14c are both "K0", "1" is output. The ATB hit determination unit 18
Both the outputs of the comparator 16 and the comparator 17 are "1", but the output of the V field 14b of the ATB key section 14 is "0", so that it is judged to be an ATB mishit and "0" is output. To do.

As described above, when the value of the count value registration register 12 makes a round while a certain address is registered in the ATB and an ATB index request is issued to the same address in that state, the count value registration register 12 is All the old entries registered in the ATB must be invalidated before the value goes round, but this embodiment knows the timing of invalidating the old entries by detecting the overflow of the count value registration register 12, At that point all ATB entries can be invalidated,
When the count value registration register 12 overflows, no operational contradiction occurs.

FIG. 5 is a block diagram showing a third embodiment of the present invention, and FIG. 6 is a format diagram showing the contents of the ATB key portion of the embodiment of FIG.

The clear account section 31, count value registration register 32, +1 counter 33, ATB key section 34, count field 34a, V field 34b, key address field 34c, request address register 35, comparator 36 and comparison of this embodiment. Device 37 and ATB hit determination unit 3
8 and the clear address generation circuit 42, the clear address registration register 43, the +1 counter 44 and the selection circuit 45 have the same configurations and operations as those of the corresponding portions of the embodiment of FIG. It does not have an overflow detection circuit.

The all clear control circuit 40 resets the V fields 34b of all the entries in the ATB key section 34 when the ATB all clear instruction 80 is issued from the micro instruction, so that the clear address generation circuit 42 and the selection circuit 45 are reset. Take control.

Next, regarding the operation of the entry clearing device configured as described above, the data shown in FIG. 6A is registered in the ATB, the value of the count value register 32 becomes "255", and the ATB clearing is performed. A case will be described in which an instruction is issued, an ATB all clear instruction 80 is subsequently issued by a micro instruction, and an ATB index request is issued to the same address "A0" as the data shown in FIG. 6A.

When the ATB clear instruction is issued, the value of the count value registration register 32 becomes "0". Next, when the ATB all clear instruction 80 is issued by the microinstruction, the all clear control circuit 40 controls the clear address generation circuit 42 thereby, and clear set address "0" for clearing all the entries of the ATB. "~" 2
55 ". At the same time, the all clear control circuit 40 controls the selection circuit 45 to select the clear address generation circuit 42 and supply the value of the clear address registration register 43 to the ATB key section 34. ATB key Part 34
Causes the V field 34 of all entries to
Reset b. At this time, the data registered in the ATB key section 34 is the data shown in FIG. 6A, that is, the count field 34a is "0", the V field 34b is "1", and the key address field 34c is "K".
From the state of "0", the data shown in FIG. 6B, that is, the count field 34a is "0", the V field 34b
Is "0" and the key address field 34c has changed to "K0".

When an ATB index request is generated again for the same address "A0" in this state, the ATB index address is set in the request address register 35. The ATB key section 34 is indexed by the set address of the ATB index address. Since the set address at this time is the same as the above-mentioned ATB index address, it is "S0". Since the data shown in FIG. 6B is registered in the entry of the set address “S0” of the ATB key section 34, the count field 3
4a indicates "0", and V field 34b indicates "0".
However, "K0" is output from the key address field 34c. The comparator 36 uses the count value registration register 32.
Since both the value registered in 1) and the value in the count field 34a are "0", "1" is output. Comparator 37
Indicates that the value of the key address of the request address register 35 and the value of the key address field 34c are both "K0".
Therefore, “1” is output. ATB hit determination unit 3
In the case of 8, both the outputs of the comparator 16 and the comparator 17 are "1".
However, since the output of the V field 14b of the ATB key section 14 is "0", it is determined that the ATB mishit has occurred and "0" is output.

As described above, when the value of the count value registration register 32 makes a round while a certain address is registered in the ATB and an ATB index request is issued to the same address in that state, the count value registration register 32 of the count value registration register 32 is made. Although all the old entries registered in the ATB must be invalidated before the value has cycled, this embodiment manages the overflow of the count value registration register 32 by a microinstruction so that the AT can be used at an appropriate timing.
Since all the entries of B can be invalidated, no operational contradiction occurs even when the count value register 32 overflows.

FIG. 7 is a block diagram showing the fourth embodiment of the present invention, and FIG. 8 is a format diagram showing the contents of the ATB key portion of the embodiment of FIG.

The ATB key section 54, the count field 54a, the V field 54b, the key address field 54c, the request address register 55, the comparator 56, the comparator 57, the ATB hit determination section 58, and the selection circuit 65 of this embodiment are configured and The operation is the same as the configuration and operation of the corresponding parts in the embodiment of FIG. A clear address generation circuit and an all clear control circuit are not provided, but an ATB clear control circuit 66 is provided instead.

The clear account unit 51 has an 8-bit count value registration register 52 and an 8-bit cyclic +1 counter 53. The count value registration tester 52 is instructed by the ATB clear control circuit 66. The output signal of the +1 counter 53 is set. The data width of the count value registration register 52 is 8 bits, which is the same as the count field 54a of the ATB key section 54.

Upon receiving the ATB clear instruction, the ATB clear control circuit 66 controls the selection circuit 65 to select the clear account section 51 and supply the value of the count value registration register 52 to the ATB key section 54. ATB key section 54
Uses this as the set address for the V of the corresponding entry.
Reset the field 54b.

Next, regarding the operation of the entry clearing device configured as described above, the value of the count value register 52 is "0", the data shown in FIG. 8A is registered in the ATB, and The operation when the ATB clear instruction is issued will be described.

Upon receiving the ATB clear instruction, the ATB clear control circuit 66 controls the selection circuit 65 to select the clear account section 51 and supply the value "0" of the count value registration register 52 to the ATB key section 54. . The ATB key unit 54 has the value “0” in the count value registration register 52.
Is set as the set address, the V field 54b of the corresponding entry is reset, and the count value registration register 52
Do a count up. Therefore, the data shown in FIG. 8A, that is, the count field 54a is "0",
From the state in which the V field 54b is "1" and the key address field 54c is "K0", the data shown in FIG. 8B, that is, the count field 54a is "0", the V field 54b is "0", and the key address field 54 is shown.
c changes to the state of "K0", and the entry becomes invalid.

As described above, the entry whose set address of the ATB key section 54 is "0" is always invalid when the count value registration register 52 counts up from "0" to "1" by the ATB clear instruction. Be converted. Similarly, for an entry whose set address of the ATB key section 54 is “n” (n is an arbitrary integer of 0 ≦ n ≦ 255), the count value registration register 52 receives “n” according to the ATB clear instruction.
To “n + 1” (However, when n = 255, (n + 1)
Will be 0)) will always be invalidated.

In this way, when the count value registration register 52 returns from "0" to "0" again by 256 ATB clear instructions, all the entries in the ATB key section 54 are valid in the count field 54a. Value is not registered. Similarly, when the count value registration register 52 returns from "n" to "n" again by 256 ATB clear instructions, valid values are registered in the count field 54a for all the entries of the ATB key section 54. Will not be.

Therefore, when the value of the count value registration register 52 is "n", the ATB key section 54 has a valid entry when the value of the count value registration register 52 one cycle before is "n". Since it is not registered, no operational contradiction occurs.

[0045]

As described above, the entry clearing device for the address translation buffer of the present invention uses the ATB clear instruction count value as a part of the ATB key part and updates the ATB clear instruction count value by the ATB all entry clear instruction. Only by doing so, it is possible to invalidate all the entries in the ATB.
It is not necessary to reset the valid flag for the number of entries in B, and the time for ATB clearing processing can be greatly shortened.
There is an effect that the TB access performance can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a format diagram showing contents of an ATB key part in the embodiment of FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a format diagram showing contents of an ATB key part in the embodiment of FIG.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

6 is a format diagram showing the contents of an ATB key part in the embodiment of FIG.

FIG. 7 is a block diagram showing a fourth embodiment of the present invention.

8 is a format diagram showing the contents of an ATB key part in the embodiment of FIG.

[Explanation of symbols]

1.11.13.151 Clear Account Part 2.12.32.52 Count Value Register 3.13.33.53 +1 Counter 4.14.34.54 ATB Key Part 4a.14a.34a.54a Count Field 4b・ 14b ・ 34b ・ 54b V field 4c ・ 14c ・ 34c ・ 54c Key address field 5 ・ 15 ・ 35 ・ 55 Request address register 6 ・ 16 ・ 36 ・ 56 Comparator 7 ・ 17 ・ 37 ・ 57 Comparator 8 ・ 18 ・38/58 ATB hit determination unit 19 Overflow detection circuit 20 All clear control circuit 22/42 Clear address generation circuit 23/43 Clear address registration register 24/44 +1 counter 25/45/65 selection circuit 40 Clear control circuit 66 ATB clear control Circuit 80 ATB all clear instruction

Claims (4)

[Claims] 1. A clear instruction count unit for counting the number of clear instructions for an address translation buffer holding an address translation pair of a logical address and a real address, and a count value in the clear instruction count unit for each entry of the address translation buffer. A count value holding unit that holds the count value holding unit that holds the count value in the clear instruction counting unit in the count value holding unit when registering the address translation pair in the clear instruction counting unit; A determination unit that compares the count value registered in the entry of the address translation buffer with the count value of the clear instruction count unit when indexing the buffer and determines that the indexed entry is invalid when they do not match; An address translation bag characterized by Entry clearing device for FA. 2. The entry clearing device for an address translation buffer according to claim 1, further comprising an overflow reset unit which resets valid flags of all entries of the address translation buffer when the clear instruction counting unit overflows. 3. A microinstruction reset unit for resetting valid flags of all entries of the address translation buffer by a microinstruction.
Entry clearing device of the described address translation buffer. 4. A clear instruction counting unit that counts with the number of entries of the address translation buffer as a basic cycle,
2. The address translation buffer according to claim 1, further comprising a clear instruction reset unit that resets a valid flag of an entry of the address translation buffer whose address is a count value of the clear instruction counting unit according to an address translation buffer clear instruction. Entry clear device.