JP2621166B2 - Programmable logic array device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic array device, and more particularly to a programmable logic array device that operates with low power consumption.

[Conventional technology]

Conventionally, as a circuit of a programmable logic array device of this kind, there is a circuit shown in FIG.
= 1,2, ..., n) and the drains of the DMOS transistors 20i (i = 1,2, ..., m) are connected to the power supply VDD, and the gates of each are connected. Load transistor circuit with the load shorted to the source
20 and 30i (i = 1, 2,..., L) connect the drains of the DMOS transistors to the power supply VDD, short-circuit each gate and source, and load the load transistor circuit 30;
Sense amplifier 60 that outputs both inverted and positive outputs
i (i = 1, 2,..., l) and a sense amplifier circuit 60
The output signal line Wi (i = 1, 2,..., N) or i (i = 1, 2,..., N) of the next decoding circuit 10 and the output signal line Xj (j) connected to the output line of the load transistor 20 = 1, 2,... M), the gate is connected to the output signal line Wi or i, the source is connected to the output signal line Xj, and the drain is connected to the ground.
EMOS transistor 40ij (i = 1,2, ..., n, j = 1,2, ..., m)
Or 40j (i = 1, 2,..., N, j = 1, 2,..., M) connected according to a program, and an output signal line Xj
At the intersection of (j = 1, 2,..., M) and the output signal line Yi (i = 1, 2,..., L) connected to the output line of the load transistor circuit 30, the gate is connected to the output signal line Xi. Output the signal line Yi
And an OR plane section 50 in which EMOS transistors 50ij (i = 1, 2,..., M, j = 1, 2,..., L) whose drains are respectively connected to ground are connected according to a program.

In the example of FIG. 4, the transfer function represented by the following equation (1) is represented. Load transistor 20 of load transistor circuits 20 and 30
Table 1 shows that current flows through i (i = 1, 2,..., m) and 30j (j = 1, 2,..., l).

[Problems to be Solved by the Invention] However, in the above-described conventional programmable logic array, one load MOS transistor is always required for each term of a product term and a sum term in order to obtain one logic output. Therefore, even if one load current is small, a large power consumption is required as a whole.

It is an object of the present invention to provide a low power consumption programmable logic array device by reducing the number of MOS transistors serving as loads.

[Means for solving the problem]

The programmable logic array device of the present invention integrates one or more programmable logic arrays on a single semiconductor substrate, and the transfer function indicating the output of each of the programmable logic arrays has only a first-order product term or 1
In a programmable logic array including at least one sense amplifier that outputs both the output of the transfer function and the inverted output of the transfer function, The inverted signal of the product term is directly sent to the input of the next OR plane without using a load resistor or a load transistor, and the signal sent from the AND plane is used in the sum term creation part having only one sum term of the OR plane. Is sent to the sense amplifier as it is without using a load resistor or a load transistor, and its inverted output is used.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. The same primary decoding circuit 10, load transistor circuits 20, 30 and sense amplifier circuit 60 as the conventional circuit shown in FIG.
It is composed of an AND plane part 40 and an OR plane part 50 which are partially different from the conventional circuit. In FIG. 1, the same reference numerals as those in FIG. 4 indicate the same components. AND plane part 4
At 0, the output signal line Xi is the same as the AND plane portion 42 of FIG.
EMOS transistor 40ij (i = 1,2)
2, ..., n, j = 1,2, ..., m) or 40j (i = 1,2, ..., n,
j = 1,2, ..., m) are connected according to the program,
The connection ALi (i = 1, 2,..., M) between the output line of the load transistor circuit 20 and the output signal line Xj, and the connection Aij (i = 1, 2) between the output signal line Wi or i and the output signal line Xj. ,…, N, j = 1,2,…,
m) or Aj (i = 1, 2,..., n, j = 1, 2,..., m) can be configured by a program. Also OR
In the plane section 50, the output signal line is the same as the OR plane section 52 in FIG.
EMOS transistor 50ij (i = 1, 2,..., Xj, Yi and earth)
m, j = 1, 2,..., l) are connected in accordance with the program, and the connection Li (i = 1, 2,..., l) between the output line of the load transistor 30 and the output signal line Yi, and the output Signal line Xi and output signal line
The connection ij (i = 1, 2,..., M, j = 1, 2,..., L) to Yi can be configured by a program.

Hereinafter, description will be given of the realization of the transfer function corresponding to the above equation (1) in FIG. Since ▲ ▼ is the sum of two terms, one primary product term and one secondary product term,
The present invention is applied to the first-order product term. First, the second-order product term is Therefore, the connection of AL ₁ and EMOS transistors 4011 and 40
1 is enough. Since the first-order product term is ▲ ▼,
Although connection and EMOS transistors 4021 prior if AL ₂ is required, the present invention makes the connection of A1, the load transistor 202 of the DMOS is not used. This can be ORed with the OR plane part 50, so that the connection of OL1 and the EMOS transistor 5
011 and 5021 can be realized, and the transfer function of equation (2) is obtained.

_{Since 2} has only a second-order product term, there is only one sum term and the present invention can be applied.
Load transistor 302 need not be used. The output at this time is obtained from Z ₂ , and becomes the transfer function of equation (3).

▼ is also obtained by the same configuration, and the load transistor 20m of the DMOS need not be used, and the output is given by the transfer function of equation (4).

Thus, the same logic is obtained by comparing the expressions (2) to (4) and the expression (1). The current flows through the load transistor circuit as shown in Table 2.

Here, comparing Tables 1 and 2, if the ON current flowing through one load transistor is assumed to be I _L , the average of 3.5 I _{L in} the conventional example and the example of the present invention are required for realizing the expression (1). Then 2.25I
_It is understood that the power consumption becomes _{L and the} power consumption is reduced.

FIG. 2 is a circuit diagram of a second embodiment of the present invention. This circuit is a load transistor circuit according to the first embodiment of FIG.
20 and 30 are negative resistance circuits 21 and 31, respectively, and the DMOS transistors in the first embodiment are replaced with resistors, respectively. Other circuits are the same as those in the first embodiment, and are described in the same manner as in FIG.

FIG. 3 is a circuit diagram of a third embodiment of the present invention. This circuit is a load transistor circuit according to the first embodiment of FIG.
The DMOS transistors used in 20 and 30 are P-channel type MOS transistors, and the AND plane portion 40 and the OR plane portion 50
Is an N-channel MOS transistor. Other circuits are the same as those in the first embodiment, and are described in the same manner as in FIG.

It is clear that the power consumption can be further reduced by removing the connection of the unused sense amplifiers in the sense amplifier circuit 60 in FIGS.

〔The invention's effect〕

As described above, according to the present invention, when a transfer function including only a first-order product term or a single-term sum term is realized, in the case of a first-order product term, an inverted signal of the product term is directly sent to the OR plane unit. As a result, the load transistor or load resistor is not used, and the output from the AND plane is
It is sent directly to the sense amplifier having both inverted outputs, and the load transistor or load resistor is not used.
If the positive output of the sense amplifier is used, the number of loads can be reduced as a whole, and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram of the third embodiment, and FIG. 4 is a circuit diagram of a conventional example. 10: Primary decode circuit, 20, 30, Load transistor circuit, 40, 41, 42: AND plane part, 50, 51, 52 ... OR plane part, 60: Sense amplifier part.

Claims (1)

(57) [Claims] 1. The method of claim 1, wherein one or more programmable logic arrays are integrated on a single semiconductor substrate, and a transfer function indicating an output of each of the programmable logic arrays is one.
In a programmable logic array including at least one sense amplifier that includes only the next product term or only one sum term and outputs both the output of the transfer function and the inverted output of the transfer function, In the term creation part, the inverted signal of this product term is sent to the input of the next OR plane as it is, and in the sum term creation part having only one sum term, the signal sent from the AND plane is sent to the sense amplifier as it is. A programmable logic array device using the inverted output.