JPS58210716A - Schmitt trigger circuit - Google Patents

Abstract

PURPOSE:To eliminate back gate effect and to improve precision by using mutually independent inverters which are free of the back gate effect and have a low and a high transition voltage respectively. CONSTITUTION:The sources of the inverter I having the high transition level and the inverter II having the low transition level are held at the same potential with a substrate. Then, when an input 100 falls from H to L, N channel transistors (TR) 6 and 8 are on and the outputs 200 and 300 of the inverters I and IIare both at L. The output 400 of an inverter 12 is at H. When the input 100 approximates to L from H, the output 200 of the inverter 200 falls to L earlier, but the output 400 is at H, so a P channel TR9 is still off, so that the output L is not transmitted to an input 11. When the input 100 further approximates to L, the output 300 of the inverter II goes up to H and the source of an N channel TR10 and the substrate are short-circuited, so the substrate side is at H and the drain side is at L; and PN junction is biased forward, so that the input 11 is apt to rise to a potential VDD-VBE. The output of the inverter 12, however, falls to L earlier than that and the P channel TR9 turns on, holding the input 11 completely at H.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Schussat trigger circuit without backgate effect.

The configuration of a conventional Schmitt trigger circuit is shown in FIG.

(1) is the input of the Schmitt trigger circuit, (2).

(3) is the output, ■t (all (abbreviated as channel transistor), ■ is an inverter. Transistors (1), (21), (support), and t23 are connected in series from the high potential side to the low potential side, and all their gate inputs are shorted to input ( 1).

The P-channel transistor (2) is connected in parallel with the P-channel transistor (4), and the N-channel transistor (5) is connected in parallel with the N-channel transistor (2). Short-circuit and connect to the output (3) of inverter ■.

The connection point between the P-channel transistor and the N-channel transistor is connected to the input of the inverter.

Next, the operation will be explained. First, consider the case where the input (1) changes from a low potential level (hereinafter abbreviated as "A") to a high potential level (hereinafter abbreviated as "H"). Since input (1) has been entered, P
Channel transistor (1), (21J is ON,
Output (2) is H1 and output (3) is L. therefore.

The P-channel transistor (to) is ON, and the N-channel transistor (support), ■), and □□□ are all OFF. Next, as the input (1) approaches H, both the P channel and N channel become ON, and the main path of current is P channel transistor (to) (21) → N channel transistor (22) → (2) becomes.

If the gm of the P-channel transistor is increased, the inverter constructed at this time will be (21) on the P-channel side.
However, on the N-channel side, □□□ is connected in series, so the transition voltage is on the high potential side, and even if the input (1) approaches from L to H, the output (2 ) is L
Don't fall. However, if the input (1) becomes larger than the transition voltage value on the high potential side, the output (2) becomes L.

The above is shown in a graph in Figure 2 (A) → (B) → (
This is route c). At this time, since the potential of the P-channel transistor (21) is different from the substrate potential, the back gate effect works and effectively increases TP, which acts in the direction of lowering the transition level of the inverter, which should have a high transition level. .

Next, consider the case where input (1) approaches H and L.

Since the output (2) is L1 and the output (3) is H, the N-channel transistors (2), (2), and (25) are ON. As the input (1) approaches L, the P-channel transistors (1) and '(21) also turn on, and if the gm of the N-channel transistor (2) is increased, the main path of current is the P-channel transistor (21). 4) → (21
1-+N-channel transistor (support) → (2), the inverter configured at this time has the P-channel side (
A) and (2υ) are connected in series, whereas the N channel side is only (22), so the transition voltage of this inverter is on the low potential side. Therefore, the input (1) changes from H to L. Even if it approaches, the output (2) does not easily become H. The above is shown in the graph of (c)→)→
0) route. At this time, if the substrate of the N-channel transistor (support) is set to the yss level, the back gate effect will work, increasing the effective VTN and acting in the direction of increasing the transition level of the inverter, which should have a low transition level.

As described above, the Schmitt trigger circuit shown in FIG. 1 has the disadvantage that the back gate effect causes the inverter's transition level to be unstable, making it difficult to design.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and its purpose is to provide a first inverter with a high potential transition voltage without back gate effect, and a first inverter with high potential transition voltage without back gate effect. a second inverter having a low potential transition voltage; a first switch circuit that selects the output of the first inverter when the potential before the inputs of the first and second inverters change is a low potential; a second switch circuit that selects the output of the second inverter when the potential before the input of the first and second inverters changes is a high potential; and a memory that stores the potential before the input changes. The object of the present invention is to provide a Schmitt trigger circuit without back gate effect by configuring the circuit together.

An embodiment of the Schitt trigger circuit according to the present invention is shown in FIG.

(100) is the input, (200) is the output of the inverter with a transition level on the high potential side, (aOO) is the output of the inverter with a transition level on the low potential side, (400) is the output of the Schmitt trigger circuit, ( 5) , (71, (9
1 is a P-channel transistor, (61, <8>,
(10) is an N-channel transistor (ID is an output cap) (121 is an inverter).

An inverter is constructed of a P-channel transistor (5) with a large gm and an N-channel transistor (6) with a small gm (inverter I), and a P-channel transistor (7) with a small gm and an N-channel transistor (8) with a large gm. Configure the inverter (Inverter ■).

Connect the output of inverter ■ (200) and the source of P channel transistor (9), and connect the output of inverter R (8
00) and the source of the N-channel transistor are connected, and the drains of the transistors (9) and α0) are shorted and connected to the input ttU of the inverter @. The gates of transistors (9) and (10) are connected to the output of the inverter (
400).

Next, the operation of the Schmitt trigger circuit according to an embodiment of the present invention will be explained. First, the input (100) changes from L to H.
Think about when things change. At this time, the output (200), (
800) are both H and N channel transistors (1
0) is shorted to the source, so the board is H
Therefore, the drain side is also H (to be exact, VDD-VBE
), and the output (400) becomes L.

Now, when the input (100) approaches from L to H, the transition level of inverter ■ is on the low potential side, so the output (800) becomes L first, but at that time the output (400) remains at L. , N-channel transistor (10 is OFF and the L output is not transmitted to the drain side. Furthermore, the input (100
) approaches H, the output (200) of inverter I, which has a transition level on the high potential side, changes to L.

At this time, the input circle-output (400) threshold voltage of the inverter (2) is -VDD, and the P-channel transistor (9) is turned off.
In order to reduce (9) ONL instead of K, which causes input (
111 becomes completely L.

Next, consider when the input (100) changes from H to L. At this time, the N-channel transistors (61, +81 are ON and the output of impark ■ and inverter ■ (2oo
) and (aoo) are used together. Output of inverter (
400) is H. Now, when the input (100) approaches L from H, the output (200) of inverter I becomes L first, but since the output (400) is H, the P channel transistor (9) remains OFF and the L output is It is not transmitted to input 01). Furthermore, when the input (100) approaches L, the output (800) of inverter 2 becomes H, which indicates a short between the source and substrate of the N-channel transistor.
9. The substrate side is Hl and the drain side is L. The PN junction is forward biased and the input (1υ) tries to go to the potential of VDD-VBE.However, before that, the output of the inverter (2) becomes L, and the P channel transistor (9) turns on.
As a result, the input (11) becomes completely H.

Figure 4 is a graph of the above. 0)→←)→
What changes from there is the input/output characteristics of inverter I, (
What changes from C) to C) to C6) is the input/output characteristic of the inverter ■.

From the above description, it is clear that the circuit according to the above embodiment operates as a Schmitt trigger circuit. Also,
Since the sources and substrates of inverter I, which has a high transition level, and inverter II, which has a low transition level, are all at the same potential, the back gate effect does not work, and the hysteresis curve is determined by the VTR and transistor size ratio, which is accurately determined by the process parameters. It is easy to draw and design. In addition, since the inverter with a high transition level and the inverter with a low transition level are independently owned and operated at the same time, the Schmitt trigger circuit can be used to simultaneously control VDD, VDD/hVs S. It is also possible to use it as a three-level level detection circuit.

As described above, according to the present invention, since it is constructed using an inverter with a low transition voltage without a backgate effect and an inverter with a high transition voltage without a backgate effect, which are independent of each other, the accuracy is high. A Schmitt trigger circuit can be provided which can also operate as a value level detection circuit.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional Schmitt trigger circuit, Figure 2 is a circuit diagram of a conventional Schmitt trigger circuit;
The figure is an input/output characteristic diagram for explaining the operation of the circuit shown in Fig. 1, Fig. 8 is a circuit diagram showing an embodiment of the Schmitt trigger circuit of the present invention, and Fig. 4 shows the operation of the circuit shown in Fig. 8. It is an input-output characteristic diagram for explanation. (100)...Input, (200), (800)
, (400)...Debuha (5) , (7) ,
(9)...P channel transistor, (61, (8
1゜(1()...N channel transistor, (1B
...Inverter, I, ■...Inverter. Agent Makoto Kuzuno - (1 other person) Figure 1 Figure 21 I V7N (1) VDD 31st Tsukasa 4 to 41'' Vtu C1) VbD

Claims (1)

[Claims] (1) A first inverter with a high potential transition voltage without a backgate effect, a second inverter with a low potential transition voltage without a backgate effect, and the inputs of the first and second inverters change. a first switch circuit that selects the output of the first inverter when the previous positive potential is low; and a first switch circuit that selects the output of the first inverter when the previous positive potential is low; 1. A Schmitt trigger circuit comprising: a second switch circuit for selecting the output of the second inverter; and a memory circuit for storing a potential before the input changes.