JP2612166B2 - Programmable delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial application field) The present invention is effective when applied to an LSI test apparatus or the like.
The present invention relates to a programmable delay circuit suitable for increasing the number of channels.

(Prior Art) FIG. 9 shows a block diagram of a conventional programmable delay circuit. A conventional programmable delay circuit has been constituted by a register 1 'having a plurality of bits and a counter 2' having a corresponding number of bits. The operation is the tenth
The operation will be described with reference to the operation timing chart of FIG. A predetermined amount of delay is set to the data input terminal 4 '(in this example, 2; that is, "1" is set to the terminal b in FIG. 9, and the other is set to "0"), and the load is input to the load terminal 5'. The delay amount is set in the register 1 'by a signal. Next, the content of the register 1 'is set in the counter 2' by the periodic clock signal input to the periodic clock terminal 7 '. Counter 2 '
Decrements (-1) sequentially from the set value every time a count clock signal is input to the count clock terminal 6 'with respect to the loaded content, and when the content becomes 0, the delay output terminal 11' To generate a delay signal (carry down signal). In the example of FIG. 10, the delay amount is the delay set value +
1 times the cycle of the count clock signal.
This corresponds to the delay time t between the periodic clock signal and the delay output signal in the figure.

FIG. 11 shows a block diagram of a multi-channel programmable delay circuit used in an LSI test apparatus or the like. As shown in the figure, when the number of channels is increased, a plurality of programmable delay circuits shown in FIG. 9 are arranged in parallel. That is, a plurality of registers 1A 'to 1N'
It is composed of counters 2A 'to 2N' corresponding to A 'to 1N'. 4A 'to 4N' are data input terminals, 11A '
-11N 'are delay output terminals.

(Problems to be Solved by the Invention) A programmable delay circuit used in an LSI test apparatus or the like generally has a wide delay setting range and a large number of channels, so that the amount of hardware is enormous. In the programmable delay circuit of FIG. 9 described above, for example, if the rate of the count clock signal is 100 MHz and the delay setting range is 0 ns to 1 ms (resolution 10 ns), the number of bits of the register 1 'and the counter 2' is 17 bits. Become. Assuming that the number of gates constituting the register 1 'and the counter 2' per bit is 7 and 12, respectively, the number of gates per channel of the 17-bit programmable delay circuit is 17 × 19 = 323. Therefore, the number of channels generally provided in an LSI test apparatus, for example, 32 channels becomes 323 × 32 = 1,036 gates to be realized by the configuration as shown in FIG. 11, and there is a problem that the amount of hardware becomes enormous. . For this reason, there is a problem that it is not possible to reduce the size in mounting, and conversely, there is a problem that there are restrictions on increasing the number of channels and expanding a delay setting range due to mounting restrictions.

(Object of the Invention) The present invention has been proposed in view of the above points, and has been
The object of the present invention is to provide a programmable delay circuit that can significantly reduce the amount of hardware when realizing a programmable delay circuit used for a test apparatus, particularly when increasing the number of channels and expanding a delay setting range. And

(Means for Solving the Problems) The present invention has introduced the following new concept in order to solve the conventional problems, and has reduced the amount of hardware.

That is, a programmable delay circuit in an LSI test apparatus or the like has a function of giving various operation timings to a device under test. The method of setting the delay is basically such that each operation timing (delay amount) within one test cycle
Therefore, the delay setting range is a time corresponding to one test cycle at the maximum, and is about 1/100 or 1/1000 of the test cycle at the minimum. In other words, if the setting range of the delay amount is three digits (10 bits in binary), it does not hinder the normal test execution. The present invention reduces the amount of hardware by introducing such a concept into the circuit configuration.

(Operation) FIGS. 1 and 2 are diagrams for explaining the operation principle of the present invention, and FIG. 1 is a diagram showing a circuit diagram configuration thereof. The programmable delay circuit according to this example includes a register 1 having a plurality of data input terminals 4 and two counters, that is, a main counter 2 and a sub counter 3. As for the mutual connection, the output of the register 1 is
Divided into two groups, the group of data bits having the smallest weight of the two groups is connected to the sub-counter data input terminal 9, and the other group is connected to the main counter data input terminal 8. The sub-counter 3 receives a sub-counter data input terminal 9 according to a periodic clock signal input to the periodic clock terminal 7.
Data input terminal and count clock terminal 6
The counting operation is performed every time the count clock signal is input to the sub-counter, and the sub-counter output signal (clock signal for the main counter) is output to the sub-counter output terminal 10 each time the counting result satisfies a predetermined condition. Further, the main counter 2 captures the data of the main counter data input terminal 8 by the periodic clock signal, and performs the counting operation every time the clock signal from the sub counter output terminal 10 is executed.
An operation of outputting a delay signal to the delay output terminal 11 when the count result reaches a predetermined value is performed.

FIG. 2 is an operation timing diagram of the programmable delay circuit described above, and shows an operation example in which only the terminals a and c of the data input terminal 4 are set to "1" and the others are set to "0". Thus, the data at each data input terminal 4 is taken into the register 1 by a load signal. The main counter 2 and the sub counter 3 register 1
The value of each is taken. First, the sub-counter 3 performs a counting operation according to the count clock signal. Sub counter 3
Is set to 1 corresponding to "1" of the terminal a, so that a clock signal for the main counter is output to the sub-counter output terminal 10 every other clock of the count clock signal. Next, in the main counter 2, as in the sub-counter 3, data of 1 is set corresponding to “1” of the terminal c, so that the second counter of the clock signal of the sub-counter output terminal 10 supplies the delayed output terminal 11. Outputs a delay signal. In the figure, the timing difference t between the periodic clock signal and the delayed output signal is the set delay amount. The desired delay amount in the circuit example shown in FIG. 1 can be expressed by the following equation.

Delay amount = {(A + 1) × B} × (C + 1) A: Set value of sub-counter 3 B: Period of count clock signal C: Set value of main counter 2 In FIG. 2, A = C = 1, B = Δt So the delay amount is 4Δt
It is.

Here, the delay amount is a value obtained by adding 1 to each of the set values of the sub-counter 3 and the main counter 2, but a method of directly setting the set value as the delay amount depending on the configuration method of the counter is also conceivable.

(Example) Next, an example of the present invention will be described.

FIG. 3 shows the configuration of a circuit according to the present invention. The register 1 shown in FIG. 1 includes a main register 12 for setting data of a main counter 2 and a sub-counter 3
And a sub register 13 for setting the data. The main register 12 and the sub-register 13 have the same number of bits as the main counter 2 and the sub-counter 3, respectively. The operation is the same as that of the embodiment shown in FIG.

FIG. 4 shows a multi-channel configuration of the programmable delay circuit shown in FIG. The sub-register 13 for setting the data of the sub-counter and the sub-counter 3 having the same bit number as the bit number have one set in common, and
The sub-counter output signal, which is a clock signal of the main counter, is distributed to all the main counters 2A to 2N. Further, main registers 12A to 12N corresponding to the main counters 2A to 2N are provided.

As an operation, first, predetermined delay data is set to each of the data input terminals 4A to 4N and 4S, and delay data is set to each register (main registers 12A to 12N and sub register 13) by applying a load signal. . Next, the contents of each register are set in each counter (main counters 2A to 2N and sub-counter 3) by a periodic clock signal. The sub-counter 3 starts counting operation by the count clock signal, and repeatedly generates a clock signal for the main counter at a predetermined cycle. Each of the main counters 2A to 2N receives the output signal of the sub-counter 3 in common and executes a counting operation. When the count value satisfies a predetermined condition, each of the main counters 2A to 2N independently outputs the delayed signal to the delay output terminal 11A to 11N. Operate to output.

FIG. 5 shows an embodiment of the sub-counter 3. The sub-counter 3 takes in the data of the sub-counter data input terminal 9 with a counter load signal and counts (subtracts) each time a count clock signal is input to the count clock terminal 6, and the state of the counter output terminal. When all the clock signals have become "0" or when the clock signal has become all "0", a clock signal for the main counter is output to the sub-counter output terminal 10 with the next count clock signal. When a periodic clock signal is input to the sub-counter or when a clock signal for the main counter is output to the sub-counter output terminal 10, a comparison circuit 32 performs an operation of supplying a counter load signal to the counter 31.

In the operation, first, a counter load signal is supplied to the counter 31 by a periodic clock signal, and the counter 31 captures the state of the sub-counter data input terminal 9. Next, a subtraction (−1) operation is performed by the count clock signal, and when the state of the counter output terminal is all “0”, or when the next count clock signal after all the state becomes “0”, the comparison is performed. The operation of the circuit 32 outputs a clock signal for the main counter to the sub-counter output terminal 10. At this time, a counter load signal is also generated, causing the counter 31 to take in the state of the sub-counter data input terminal 9 again.
Hereinafter, the sub-counter data input terminal 9 is operated in the same manner.
The main counter clock signal is output to the sub-counter output terminal 10 in the state (counter initial set value) or the repetition of the value + 1.

FIG. 6 shows an embodiment of the comparison circuit 32 in FIG. Comparator circuit 32 applies the carry-down detection circuit 321 all counter output terminal applied to the terminal a ₀ ~a _n is to detect when a "0" at the same time, the output and the terminal C of the carry-down detection circuit 321 an aND logic gate 322 for taking an aND logic of the count clock signal, and a OR logic gate 323 for taking an OR logic of the periodic clock signal applied to the output and the terminal L ₁ of the aND logic gate 322 . Note that the AND logic gate 32
As second output sub-counter output signal from the terminal O _S, OR
The output of the logic gate 323 is a counter load signal output terminal L _0.
Each of them is extracted as a counter load signal.

This comparison circuit 32 operates as follows. Counter 31 performs a sequential subtraction operation, when the state of the counter output terminal given by comprising timing to the terminal a ₀ ~a _n becomes all "0", the output of the carry-down detection circuit 321 is switched from "0" to "1 Changes to " At this time, when the count clock signal is input to the count clock terminal 6 and applied to one end of the AND logic gate 322 via the terminal C, the AND logic gate 322 outputs “1”, and subsequently the OR logic gate 323 also. By outputting “1”,
Desired sub-counter output signals and counter load signals can be respectively obtained. Note that the carry-down detection circuit 321
It can be realized by taking the NOR logic of essentially the signal at the terminal a ₀ ~a _n. If the counter 31 includes a borrow detection function, the borrow detection circuit 321 in the comparison circuit 32
And the AND logic gate 322 can be omitted.

FIG. 7 shows another embodiment of the sub-counter 3. In FIG. The sub-counter 3 has a counter 33 having a plurality of bits, and one input terminal connected to the counter output terminal of each bit of the counter 33, and the other input terminal of the sub-counter data input terminal 9 having the same number of bits as the counter 33. And a comparison circuit 34 for comparing the two data.
The comparison circuit 34 performs an operation of comparing the count value of the counter 33 with the data of the sub-counter data input terminal 9 and outputting a clock signal for the main counter to the sub-counter output terminal 10 at a cycle satisfying a predetermined condition.

FIG. 8 shows an embodiment of the comparison circuit 34 in FIG. The comparison circuit 34 includes a plurality of NOT logic gates 341 for creating inverted contents of the plurality of sub-counter data input terminals 9 applied to the terminals b _{0 to} b _n , an output terminal of the NOT logic gate 341 and a terminal a.
₀ a plurality of OR logic gate 342 that takes the individual OR logic between corresponding bits of the output terminal of each bit of the counter 33 applied to ~a _n, from the OR logic result and the terminal C of the OR logic gate 342 And an AND logic gate 343 which performs an AND logic with a given counter clock signal. Therefore, the state of the output terminal of each bit of the terminal b ₀ ~b state and the terminal a of the sub-counter data input terminal 9 to be applied to _{n 0} counter 33 applied to ~a _n is when a predetermined condition is satisfied so that the output signal to the sub-counter output terminal 10 from the terminal O _S is output. That is, when m is smaller than n, the terminals b _{0 to} b _m =
When “0” and terminals b _{m + 1 to} b _{n are set to} “0”, the count of the counter 33 advances from the clear state, and when the terminal am _{+ 1} becomes “1”, the terminal C becomes “1”. signal of "1" to the terminal O _S is output by comprising timing.

(Effects of the Invention) As described above, in the present invention, each delay circuit is provided with the number of bits that covers the entire delay setting range. Therefore, hardware can be greatly reduced. For example, the count clock signal rate is 100 MHz, and the delay setting range is 0 ns to 1
Assuming ms (17-bit configuration), the number of gates of the programmable delay circuit of 32 channels is 10336 gates (register 7 gates / bit, counter 12 gates / bit) in the conventional system, but according to the present invention, it is 1 The number of gates per channel is the same as the conventional method with 323 gates, but when 32 channels are achieved, 6123 gates (main counter 10 bits, sub counter 7 bits).
It can be realized with 60% of hardware compared to the conventional method. Further, if both the number of channels and the delay setting range are expanded, there is an advantage that the effect of hardware reduction is further increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a programmable delay circuit of the present invention, FIG. 2 is an operation timing diagram of FIG. 1, FIG. 3 is a block diagram showing another embodiment of the present invention, FIG. FIG. 4 is a block diagram showing a multi-channel system according to the present invention. FIG. 5 is a diagram showing an embodiment of a sub-counter.
FIG. 5 is a block diagram showing an embodiment of the comparison circuit in FIG. 5, FIG. 7 is a block diagram showing another embodiment of the sub-counter, and FIG.
FIG. 9 is a block diagram showing a conventional programmable delay circuit, FIG. 10 is an operation timing diagram of FIG. 9, and FIG. 11 is a diagram showing a conventional multi-channel circuit. It is a block block diagram. 1 Register 2 Main counter 3 Sub-counter 4 Data input terminal 5 Load terminal 6 Count clock terminal 7 Periodic clock terminal 8 Main counter data input terminal 9 Sub-counter Data input terminal 10: Sub-counter output terminal 11: Delayed output terminal

Claims (7)

(57) [Claims] A register having a plurality of bits, having a plurality of data input terminals, and taking in and holding data of the data input terminal by a load signal inputted to a load terminal;
The output terminal of the register is divided into a plurality of groups by an arbitrary number of bits in the order of the weight of the bits of the held data, and a group of data bits having the smallest weight among the plurality of groups is input to a sub-counter data input terminal. Connected, captures the state of the sub-counter data input terminal according to the periodic clock signal input to the periodic clock terminal, performs a counting operation each time the count clock signal is input to the count clock terminal, and the count value satisfies a predetermined condition. A sub-counter consisting of a plurality of bits for repeatedly outputting a sub-counter output signal to a sub-counter output terminal, and connecting the remaining group of output terminals of the register to one or more main counter data input terminals, respectively, The state of the main counter data input terminal is captured by a signal, and the A main counter consisting of a plurality of bits, which performs a counting operation each time an output signal is output and outputs a delay signal to a delay output terminal when the count value satisfies a predetermined condition. A programmable delay circuit characterized by being configured. 2. A data group comprising a plurality of bits is divided into a plurality of groups by an arbitrary number of bits in the order of bit weights, and a group of data bits having the smallest weight among the plurality of groups is input to an input terminal. A sub-register for capturing and holding the state by a load signal input to the load terminal, outputting the data to the sub-counter data input terminal, and connecting the remaining plural groups of the data input terminals to the input terminals. Is captured and held by the load signal,
2. The programmable delay circuit according to claim 1, wherein the register is constituted by a plurality of main registers each outputting to a corresponding main counter data input terminal. 3. The programmable delay circuit according to claim 1, wherein at least one of the main counter and the sub counter includes a circuit having a carry down function. 4. A multi-bit counter that captures the state of a sub-counter data input terminal by a counter load signal and performs a counting operation each time a count clock signal is input to a count clock terminal, and states of a plurality of output terminals of the counter. And outputs a sub-counter output signal to a sub-counter output terminal when the content is in a predetermined input state, and when the sub-counter output signal is output or when a periodic clock signal is input to a periodic clock terminal. 2. The programmable delay circuit according to claim 1, wherein a sub-counter is constituted by a comparison circuit that outputs the counter load signal to a counter load signal output terminal. 5. The state of a plurality of counter output terminals is input,
A borrow detection circuit that outputs a detection signal when the content is in a predetermined input state, ANDs the detection signal with a count clock signal input to a count clock terminal, and outputs the AND logic output as a sub AND logic gate applied to the counter output terminal, and OR logic of the AND logic output and the periodic clock signal input to the periodic clock terminal,
OR for applying the OR logic output to the counter load signal output terminal
5. The programmable delay circuit according to claim 4, wherein a comparison circuit is constituted by the logic gate. 6. A multi-bit counter that clears contents by a periodic clock signal input to a periodic clock terminal and performs a counting operation each time a count clock signal is input to a count clock terminal, and an output terminal for each bit of the counter Is connected to a group of input terminals, the sub-counter data input terminal is connected to another group of input terminals, the state of both inputs is compared, and whenever a predetermined condition is satisfied, the sub-counter output terminal is connected to the sub-counter output signal. 2. The programmable delay circuit according to claim 1, wherein a sub-counter is configured by a comparison circuit that outputs the sub-counter. 7. A plurality of NOT logic gates for creating inverted contents of a plurality of sub-counter data input terminals, and a corresponding bit between an output terminal of the NOT logic gate and an output terminal of each bit of a multi-bit counter. A comparison circuit is constituted by a plurality of OR logic gates that individually take OR logic and AND logic gates that take AND logic of all OR logic results of the OR logic gates and the count clock signal input to the count clock terminal. 7. The programmable delay circuit according to claim 6, wherein: