JP2608915B2 - IC mounting equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an IC mounting device having a plurality of multi-terminal IC chips such as a memory card.

[Conventional technology]

In recent years, as semiconductor memories such as ROMs and RAMs have increased in capacity, memory cards in which a large number of IC chips for these semiconductor memories are mounted on a single substrate have been manufactured, and are widely used for games, process management, and the like. Used in application fields.

However, the IC chip for semiconductor memory has 30 to 50 connection terminals, and these connection terminals are common to data bus terminals and control bus terminals except for some individual terminals such as chip enable terminals. These are connection terminals, and the connection wiring of these common connection terminals and individual connection terminals on a narrow board has been a problem.

 The conventional wiring structure will be described below with reference to the drawings.

FIG. 7 is a plan view of a conventional memory card, FIG. 8 is a partial plan view showing connection wiring between IC chips, and FIG. 9 is a partial sectional view. The substrate 50 constituting the memory card 5 is a double-sided wiring board as shown in FIG. 9, the upper surface 50a A ₁ to A ₂₀
In addition to the 20 IC chips shown by the symbols, the top pattern a shown by a solid line, the bonding pattern n shown by a black circle,
A through hole m indicated by a white circle is provided, and a lower surface pattern b indicated by a dotted line is provided on the lower surface 50b, and is connected to the upper surface 50a by the through hole m.

As shown in FIG. 8, each IC chip A has a square shape,
Each of the opposing sides c and d is provided with 20 connection terminals, and the other opposing sides e and f are not provided with connection terminals. The connection terminals provided on the side c are all common connection terminals, and the other 19 connection terminals provided on the side d are common connection terminals except for one chip enable terminal. .

Connect the connection wiring between the above IC chips to IC chips A ₁ , A ₂ , A ₃
Will be described.

Provided on a side portion c ₂ of the IC chip A ₂ as shown in FIG. 8
Connect 20 connection terminals to each bonding pattern n ₂ and side d ₂
Respectively connected by a wire Bonn dengue twenty connecting terminals provided on the respective through holes m _2. IC in the same way
Also the side portion c ₃ of the connection terminals each Bonn Dengue patterns n _3, wire-Bonn dengue connection terminal side portion d ₃ in the through-hole m ₃ for chip A _3. As a result, half (10) of the bonding patterns n ₂ to which the connection terminals of the IC chip A ₂ are connected are formed by the ten upper surface patterns disposed on the left side of the IC chip A ₂ while avoiding the through hole m _2. are connected by a ₁ in the Bonn dengue pattern n ₃ of the common connection terminal is connected to the IC chip a _3, also the rest of the Bonn dengue pattern n ₂ 10 pieces of which are arranged on the right side of the IC chip a ₂ by the upper surface pattern a ₂ is connected to a corresponding Bonn dengue pattern of the IC chip a _3. Further, the through-hole m ₂ to which the connection terminal of the IC chip A ₂ is connected is directly formed by the lower surface pattern b provided on the lower surface side of the substrate 50.
It is connected to the through-hole m ₃ of the IC chip A _3.

That is, in the above configuration, the I
The connection terminals provided on one side of the C chip are connected, and the connection terminals provided on the other side are connected on the lower surface 50b where no IC chip is present, and the individual connection terminals are routed. Wiring is done.

The above is the connection structure between the IC chips. Next, the entire connection structure will be described with reference to FIG.

That is, 20 IC chips A _{1 to} A ₂₀ are arranged and bonded in four rows in the arrangement direction indicated by the arrow B on the substrate 50. At this time, by setting the direction of each IC chip to the opposite direction for each column as shown by the arrow, it is possible to perform the connection between the IC chips across each column in a planar manner without crossover.

[Problems to be solved by the invention]

As described above, in the conventional memory card, since a large number of IC chips are directly mounted on one circuit board, it is necessary to disperse the wiring between the common connection terminals on the upper and lower surfaces of the circuit board. As a result, a large number of through-holes and high-density wiring patterns are required for the circuit board, and there are problems such as an increase in cost due to a high manufacturing cost through-hole process and a decrease in yield due to high-density mounting of IC chips on the high-density wiring patterns. . It is also possible to use a single-sided printed circuit board to make all connections between the common connection terminals on the IC chip bonding surface.However, in this case, a considerably large wiring space is required on both sides of the IC chip. It is necessary to arrange them with a sufficiently large distance, and as a result, there is a problem that the number of IC chips that can be mounted on one card is limited.

The object of the present invention is to solve the above problems, to reduce the cost,
An object of the present invention is to provide a reliable and high-density IC mounting apparatus.

[Means for solving the problem]

In order to achieve the above object, in the configuration of the present invention, a large number of memory IC chips having a plurality of common connection terminals are mounted on a circuit board having an external connection terminal, and the common connection terminal of each IC chip is provided as described above. In an IC mounting apparatus connected to an external connection terminal of a circuit board, the plurality of IC chips are divided into a plurality of groups, and a plurality of chips are mounted by mounting a plurality of IC chips constituting each group on an auxiliary board. A unit is formed, a bonding pattern group for connecting the chip units having the same configuration is provided on the upper and lower surfaces of the circuit board, and a bonding pattern common to the upper and lower surfaces is connected by through holes. In addition, in each of the bonding pattern groups on the upper surface and the rear surface, chip units having the same configuration are mounted in opposite directions.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view of a memory card according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line XX of FIG. 1. A power supply device is housed in a circuit board 1 constituting the memory card 10. Notch 1a for
, A memory mounting section 1b and a decoder mounting section 1c, and a plurality of external connection terminals T are provided at an end of the memory mounting section 1b.

And memory mounting portion 1b of the circuit board 1, below four chips units B _1, B _2, B _3, with B ₄ are aligned disposed, a plurality of chip components on its periphery arranged Have been.

The decoder mounting section 1c has mounted thereon elements such as a decoder IC2 and a capacitor. As shown in FIG. 2, three chip units B ₅ , B ₆ , and B ₇ are arranged in the memory mounting portion 1b ′ on the back side of the circuit board 1.

FIGS. 3 and 4 is a plan view and a sectional view of a chip unit B ₁ shown in FIG. 1, the chip unit B ₁ represents an IC chip D ₁ to D ₄ for four memory on the auxiliary board 4 They are mounted as a group and sealed with a sealing resin 6. And wherein the long side direction of one side of the auxiliary substrate 4 has a plurality of unit connection terminals t are provided in four blocks of t ₁ ~t _4, each block t ₁ ~t ₄ of the unit connection terminal t Are the _four IC chips D _{1 to} D ₄ (each IC chip of this embodiment has 28
Common connection terminals having one common connection terminal and one chip enable terminal) are connected to each other after being commonly connected by a common connection pattern on the auxiliary substrate 4,
Also in each block (abbreviated as hereafter CE connection terminals) chip enable connection terminal te for connecting the chip enable terminals of each IC chip D ₁ to D ₄ are provided.

Ie, the number of unit connection terminal t of the chip unit B ₁ represents has 32 number of terminals which is the sum of the four enable terminal provided one by one to the common connection terminal 28 and the IC chip D ₁ to D ₄ Each of the 32 terminals is divided into eight blocks t _{1 to} t ₄ .

Each of the chip units B ₂ , B ₃ , B ₄ ,
B ₅ , B ₆ , B ₇ include the number and arrangement of unit connection terminals,
All have the same configuration as the chip unit B _1.

5 and 6 are a top view and a back view of the circuit board 1 shown in FIG. 1, respectively, showing a wiring pattern. As shown in FIG. 5, the memory mounting portion 1b on the upper surface of the circuit board 1 has chip units B ₁ , B ₂ ,
A bonding pattern P is formed corresponding to the position of each unit connection terminal t when B ₃ and B ₄ are aligned and arranged, and a common bonding pattern P for each chip unit and its bonding pattern. The external connection terminal T corresponding to P is commonly connected by a wiring pattern.

A decoder IC2 is mounted on the decoder mounting section 1c as shown by a dashed line, and each chip enable bonding pattern Pe of the bonding pattern P (hereinafter abbreviated as CE bonding pattern) is mounted on the decoder IC2. Is connected.

As shown in FIG. 6, the memory unit 1b 'on the back surface of the circuit board 1 also has chip units B ₅ ,
A bonding pattern P is formed corresponding to the position of each unit connection terminal t when B ₆ and B ₇ are arranged and aligned, and a common bond for each chip unit as in the memory mounting portion 1b on the upper surface. The dengue pattern P and the external connection terminal T corresponding to the bonding pattern P are commonly connected by a wiring pattern. Further, the external connection terminals T on the upper surface and the external connection terminals T on the rear surface are connected by through holes Pd, respectively, so that a common bonding pattern P for each chip unit on the upper surface and the rear surface is formed.
Are all connected in common. As described above, the bonding pattern P common to each chip unit on the upper surface and the lower surface is used.
Can be connected by at least one through hole.
Each CE bonding pattern Pe is connected to the back surface pattern of the decoder IC2 of the decoder mounting section 1c ', and further connected to an external connection terminal To.

Next, a description will be given of implementation and connection wiring in the chip unit memory mounting portion 1b and 1b 'of the chip unit B ₁ and B ₅ as a case. In FIG. 5, the unit connection terminals t ₁ , t ₂ , t ₃ , and t ₄ of the chip unit B ₁ , which is mounted as a unit connection terminal at the position indicated by the dashed line in FIG. Bonn dengue pattern above _{P 1, P 2, P 3} ,
P ₄ is positioned in, the mounting state of FIG. 1 by performing soldering in this state.

As a result, the chip unit is included in the CE bonding pattern Pe provided for each block of the bonding pattern.
CE connection terminal te provided for each block of the unit connection terminals B ₁ is, are respectively soldered.

Each of the bonding patterns P ₁ , P ₂ , P ₃ , and P ₄ except for the CE bonding pattern Pe are connected to the corresponding external connection terminal blocks T ₁ , T ₂ , T ₃ , and T ₄ as described above. Have been.

Similarly, by mounting the other chip units B ₂ , B ₃ and B ₄ , the common unit connection terminals of each chip unit are connected linearly by the wiring pattern, and the bonding pattern P ₁ , P ₂ , P ₃ , and P ₄ and the external connection terminals T ₁ , T ₂ , T ₃ , and T ₄ are arranged in the same order, thereby enabling planar connection without crossover wiring.

Then as indicated by a dashed line In Figure 6, the chip unit B ₅ .about.B ₇ is placed in the direction of connection terminal indicated by the arrow to the chip unit B ₁ .about.B ₅ of the top surface as a reverse direction .

In this state, the unit connection terminals t ₁ , t ₂ , t ₃ , and t ₄ of the chip unit B ₅ are positioned at the bonding patterns P ₁ , P ₂ , P ₃ , and P ₄ on the circuit board 1, respectively. 2 and the state shown in FIG. 2 is obtained by soldering.

That arrangement of the Bonn dengue pattern P connected to the memory mounting portion 1b and 1b of the circuit board 1 'by in the through hole and Pd, since just a sequence order of GyakuMuko, each chip unit B ₁ .about.B ₄ a chip unit B ₅ .about.B ₇
By placing them opposite to each other, a correct connection can be obtained. Also connected to the decoder IC2 by wiring pattern through all the CE connecting terminals t _e is CE Bonn dengue pattern P _e. Further, a decoder control signal is supplied to the decoder IC2 via the external connection terminal To to perform enable control of the IC chips mounted on each of the chip units.

By adopting a chip unit structure in which a plurality of IC chips are compactly packaged as described above, it is possible to reduce the wiring density on the circuit board 1.

Further, the same chip unit can be mounted on both sides of the circuit board 1 by forming the same wiring pattern on the upper and lower surfaces of the circuit board 1 and connecting the corresponding patterns by a series of through holes.

Also, by making the arrangement order of the unit connection terminals t of the chip unit and the external connection terminals T of the circuit board 1 coincide with each other on both sides of the circuit board, the wiring pattern can be made flat and straight, and soldering can be facilitated. ing.

Furthermore, by performing a reliability check on a chip unit basis, the mounting yield on the circuit board 1 can be greatly improved. The yield was improved. In this embodiment, the number of chip units on the rear surface is smaller than the number of chip units on the upper surface because the bonding patterns P are arranged at the same position on both surfaces of the circuit board 1. Pattern P on the wiring pattern that is arranged
Can be freely selected, it is possible to mount the same number of chip units by disposing them in consideration of the direction of the chip units.

〔The invention's effect〕

As described above, according to the present invention, a chip unit having the same configuration in which a plurality of IC chips are mounted on an auxiliary substrate, and a bonding pattern group for mounting the chip unit are provided on the upper and lower surfaces of the circuit board, A common IC that has connection terminals only on either the upper or lower surface by connecting the common bonding pattern on the upper and lower surfaces with through holes and mounting the chip units on the upper and lower surfaces in opposite directions. The use of chips makes it possible to flatten and straighten the wiring pattern of IC mounting equipment, lowering the wiring density on circuit boards, improving IC mounting density, and improving reliability by managing chip units. Since it is possible to achieve the above, there is a great effect in improving the product competitiveness of the IC mounting apparatus.

[Brief description of the drawings]

FIG. 1 is a plan view of a memory card of the present invention, and FIG.
3 and 4 are plan and sectional views of the chip unit of the present invention, and FIGS. 5 and 6 are top and rear views of the circuit board of the present invention. FIG. 1 is a plan view of a conventional memory card, and FIGS. 8 and 9 are a partial plan view and a partial cross-sectional view of a conventional memory card. 1 ...... circuit board, 10 ...... memory card, B ₁ .about.B ₇ ...... chip unit, D ₁ to D ₄ ...... IC chip.

Claims (1)

(57) [Claims] An IC chip for a memory having a plurality of common connection terminals is mounted on a circuit board having an external connection terminal, and a common connection terminal of each IC chip is connected to the external connection terminal of the circuit board. In an IC mounting device,
The IC chips are divided into a plurality of groups, and a plurality of IC units constituting each group are mounted on an auxiliary substrate to form a plurality of chip units.
A bonding pattern group for connecting the chip units having the same configuration is provided, and a common bonding pattern on the upper surface and the back surface is connected by through holes.
An IC mounting apparatus, wherein chip units having the same configuration are mounted on the respective bonding pattern groups on the upper surface and the rear surface in opposite directions.