JP2606174B2 - Mounting method of two-story electronic circuit package - Google Patents
Mounting method of two-story electronic circuit packageInfo
- Publication number
- JP2606174B2 JP2606174B2 JP7092218A JP9221895A JP2606174B2 JP 2606174 B2 JP2606174 B2 JP 2606174B2 JP 7092218 A JP7092218 A JP 7092218A JP 9221895 A JP9221895 A JP 9221895A JP 2606174 B2 JP2606174 B2 JP 2606174B2
- Authority
- JP
- Japan
- Prior art keywords
- sub
- board
- electronic circuit
- story
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
Landscapes
- Combinations Of Printed Boards (AREA)
Description
【0001】[0001]
【産業上の利用分野】電子回路パッケージの実装方式に
関し、特に2階建てパッケージの試験評価を容易に行う
ことができる実装方式に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting method of an electronic circuit package, and more particularly to a mounting method capable of easily performing a test evaluation of a two-story package.
【0002】[0002]
【従来の技術】従来、2階建て電子回路パッケージにお
ける1階部分を構成するマザー基板と2階建て部分を構
成するサブ基板とをコネクタで接続することにより2枚
1組で1つの機能を有する2階建て電子回路パッケージ
においては、マザー基板表面とサブ基板裏面の間は非常
に狭く、マザー基板表面またはサブ基板裏面の素子に試
験用測定器を直接接続することは不可能な為、試験器の
接続を要する素子にリード線を付けて引出し、その先に
測定器を接続することにより試験を行っていた。2. Description of the Related Art Conventionally, a two-story electronic circuit package has one function by connecting a mother board constituting a first-floor part and a sub-board constituting a two-story part by a connector. In a two-story electronic circuit package, the distance between the front surface of the mother board and the back surface of the sub-board is very narrow, and it is not possible to directly connect a test measuring instrument to the elements on the front surface of the mother board or the back surface of the sub-board. A test was performed by attaching a lead wire to an element requiring connection and extracting the lead, and then connecting a measuring instrument to the end.
【0003】[0003]
【発明が解決しようとする課題】従来、試験のため、基
板上の素子からリード線を引き出す場合は素子に不必要
な半田がついたり、リード線にノイズがのりやすい等の
問題があり、またパッケージの試験の際は、延長パッケ
ージを用いてパッケージを引き出して評価するため、2
階建てのパッケージで採用されることが多い強制空冷は
行われないことになり、そのため基板間に熱がこもり、
素子の誤動作をも引き起こす等の問題もあった。Conventionally, when a lead wire is drawn from a device on a substrate for testing, there are problems such as unnecessary soldering on the device and noise on the lead wire. When testing the package, the extension package is used to pull out the package for evaluation.
Forced air cooling, which is often used in multi-story packages, will not be performed, so heat will build up between the boards,
There were also problems such as causing malfunction of the element.
【0004】本発明の目的は、マザー基板表面とサブ基
板裏面の間の狭い空間からリード線を引出したり、熱が
こもることなどにより、正常な動作が妨げられることの
無い、2階建て電子回路パッケージの実装方式を提供す
ることである。An object of the present invention is to provide a two-story electronic circuit in which a normal operation is not hindered by drawing out a lead wire from a narrow space between the front surface of the mother substrate and the back surface of the sub-substrate, or by retaining heat. The purpose is to provide a package mounting method.
【0005】[0005]
【課題を解決するための手段】本発明の2階建て電子回
路パッケージの実装方式は、サブ基板の表面に、サブ基
板の裏面に搭載されたコネクタと同型のコネクタを搭載
し、2階建て電子回路の試験の際の必要に応じ、サブ基
板の表面をマザー基板の表面と向い合わせ、サブ基板の
表面に搭載されたコネクタをマザー基板の表面に搭載さ
れたコネクタと接続し、試験に供することができる。According to the present invention, a two-story electronic circuit package is mounted on a front surface of a sub-substrate by mounting a connector of the same type as a connector mounted on the back surface of the sub-substrate. When necessary for circuit testing, face the sub-board surface to the mother board surface, connect the connector mounted on the sub-board surface to the connector mounted on the mother board surface, and provide the test. Can be.
【0006】前述のコネクタは、それぞれマザー基板の
表面と、サブ基板の裏面および表面の端部に搭載される
ことが望ましい。It is desirable that the above-mentioned connectors are mounted on the front surface of the mother board and on the back and front ends of the sub-board, respectively.
【0007】[0007]
【作用】サブ基板の表面に、その裏面に搭載されたもの
と同型のコネクタを搭載し、2階建て電子回路パッケー
ジの試験に当り、必要に応じてサブ基板を180°回転
し、サブ基板の表面に搭載されたコネクタを用いてマザ
ー基板と接続すれば、マザー基板の表面またはサブ基板
の裏面に搭載された回路素子に、容易に試験用測定器を
接続することができる。A connector of the same type as that mounted on the back surface of the sub-board is mounted on the front surface of the sub-board, and when testing a two-story electronic circuit package, the sub-board is rotated by 180 ° as necessary to By connecting to the motherboard using the connector mounted on the front surface, the test measuring instrument can be easily connected to the circuit element mounted on the front surface of the motherboard or the rear surface of the sub-board.
【0008】[0008]
【実施例】次に本発明の実施例について、図面を用いて
説明する。Next, embodiments of the present invention will be described with reference to the drawings.
【0009】図1は本発明の実施例の2階建て電子回路
パッケージの説明用略図である。FIG. 1 is a schematic diagram illustrating a two-story electronic circuit package according to an embodiment of the present invention.
【0010】図1において、(a)は使用時におけるマ
ザー基板1とサブ基板2の相対位置関係を示しており、
マザー基板1の表面とサブ基板2の裏面が向いあってい
る。この向いあったマザー基板1の表面とサブ基板2の
裏面に搭載された電子回路素子(不図示)は、マザー基
板1の表面およびサブ基板2の裏面にそれぞれ搭載され
た対をなすコネクタ(11,21)によって接続される
(コネクタ21はサブ基板の裏面にあり、搭載位置が点
線で示されている)。またサブ基板2の表面に搭載され
ているコネクタ22はサブ基板2の裏面のコネクタ21
と同型であり、かつコネクタ21と並列に配線されてい
る。マザー基板1とサブ基板2はコネクタ11とコネク
タ21が接続される位置に接近して組立てられ、マザー
基板1の表面に搭載された電子回路素子とサブ基板2の
裏面に搭載された電子回路素子とは、極めて接近した位
置関係に置かれる。FIG. 1A shows a relative positional relationship between a mother board 1 and a sub-board 2 during use.
The front surface of the mother substrate 1 and the back surface of the sub substrate 2 face each other. The facing electronic circuit elements (not shown) mounted on the front surface of the mother substrate 1 and the back surface of the sub-substrate 2 are connected to a pair of connectors (11) mounted on the front surface of the mother substrate 1 and the back surface of the sub-substrate 2, respectively. , 21) (the connector 21 is on the back surface of the sub-board, and the mounting position is indicated by a dotted line). The connector 22 mounted on the front surface of the sub-board 2 is
And is wired in parallel with the connector 21. The mother board 1 and the sub-board 2 are assembled close to the position where the connector 11 and the connector 21 are connected, and the electronic circuit element mounted on the front surface of the mother board 1 and the electronic circuit element mounted on the back surface of the sub-board 2 Is located in a very close positional relationship.
【0011】図1(b)は試験時におけるマザー基板1
とサブ基板2の相対位置関係を示しており、サブ基板2
は使用時の位置から180°回転され、サブ基板2の表
面にあるコネクタ22がマザー基板1の表面にあるコネ
クタ11と接続される(コネクタ22はサブ基板2の表
面にあり、図1(b)においてはその位置が点線で示さ
れている)。この場合もマザー基板1とサブ基板2に搭
載されている電子回路素子による電子回路の構成は使用
時と全く変らず、2階建て電子回路パッケージの試験評
価を行うことができる。FIG. 1B shows a mother board 1 during a test.
And the relative positional relationship between the sub-substrate 2 and the sub-substrate 2.
Is rotated by 180 ° from the position at the time of use, and the connector 22 on the surface of the sub-board 2 is connected to the connector 11 on the surface of the mother board 1 (the connector 22 is on the surface of the sub-board 2, and FIG. )) Is indicated by a dotted line). Also in this case, the configuration of the electronic circuit using the electronic circuit elements mounted on the mother board 1 and the sub-board 2 is not different from that at the time of use, and the test evaluation of the two-story electronic circuit package can be performed.
【0012】今、図1(a),(b)に示すように各コ
ネクタ11,21,22はいずれもマザー基板1および
サブ基板2の端部、すなわち辺の近傍に位置しているた
め、マザー基板1の表面およびサブ基板2の裏面は、図
1(b)に示す試験時には、いずれもその大部分が他の
ものと接近する位置関係には無い状態になり、マザー基
板1の表面およびサブ基板2の裏面に搭載された電子回
路素子への試験用測定器の接続は極めて容易であり、ま
た熱がこもるおそれも無い。Now, as shown in FIGS. 1 (a) and 1 (b), each of the connectors 11, 21, 22 is located at the end of the mother board 1 and the sub-board 2, ie, near the side. At the time of the test shown in FIG. 1B, the front surface of the mother substrate 1 and the back surface of the sub-substrate 2 are not in a positional relationship in which most of them are close to other components. The connection of the test measuring device to the electronic circuit element mounted on the back surface of the sub-substrate 2 is extremely easy, and there is no possibility that heat will be trapped.
【0013】[0013]
【発明の効果】2階建て電子回路パッケージのサブ基板
を180°回転し、裏返し状にマザー基板に取付け、さ
らにコネクタ取付位置を基板の端部(辺の近傍)に設
け、マザー基板とサブ基板の重なる面積を小さくするこ
とにより、電子回路素子の接続を変更することなく、マ
ザー基板とサブ基板の間の極めて狭い空間に搭載された
電子回路素子を外部から見ることができるようにし、電
子回路素子に容易に試験用測定器を接続することができ
る効果がある。According to the present invention, the sub-board of the two-story electronic circuit package is rotated by 180 ° and mounted on the mother board in an upside-down manner. Further, the connector mounting position is provided at an end (near the side) of the board. The electronic circuit element mounted in an extremely narrow space between the mother board and the sub-board can be seen from the outside without changing the connection of the electronic circuit element by reducing the overlapping area of the electronic circuit element. There is an effect that a test measuring instrument can be easily connected to the element.
【図1】本発明の実施例の2階建て電子回路パッケージ
の説明用略図である。FIG. 1 is a schematic diagram illustrating a two-story electronic circuit package according to an embodiment of the present invention.
1 マザー基板 2 サブ基板 11,21,22 コネクタ 1 Mother board 2 Sub board 11, 21, 22 Connector
Claims (2)
階部分を構成するマザー基板の表面と2階部分を構成す
るサブ基板の裏面を向い合わせに組立て、マザー基板の
表面およびサブ基板の裏面にそれぞれ搭載する少くとも
1対のコネクタにより接続される2階建て電子回路パッ
ケージの実装方式において、 前記サブ基板の表面に、該サブ基板の裏面に搭載された
コネクタと同型のコネクタを搭載し、前記2階建て電子
回路の試験の際の必要に応じ、前記サブ基板の表面を前
記マザー基板の表面と向い合わせ、該サブ基板の表面に
搭載されたコネクタを該マザー基板の表面に搭載された
コネクタと接続し、該試験に供することを特徴とする2
階建て電子回路パッケージの実装方式。1. A two-story electronic circuit package comprising:
Assembling the front surface of the mother board constituting the floor portion and the back surface of the sub-board constituting the second floor portion face to face, and connecting by at least one pair of connectors mounted on the front surface of the mother board and the back surface of the sub-board, respectively. In the mounting method of the two-story electronic circuit package, a connector of the same type as the connector mounted on the back surface of the sub-substrate is mounted on the front surface of the sub-substrate. The surface of the sub-substrate faces the surface of the mother substrate, and a connector mounted on the surface of the sub-substrate is connected to a connector mounted on the surface of the mother substrate, and is subjected to the test.
Mounting method for multi-story electronic circuit packages.
板の表面と、前記サブ基板の裏面および表面の端部に搭
載される請求項1に記載の2階建て電子回路パッケージ
の実装方式。2. The method according to claim 1, wherein the connectors are mounted on the front surface of the mother board and the back and front edges of the sub-board, respectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7092218A JP2606174B2 (en) | 1995-04-18 | 1995-04-18 | Mounting method of two-story electronic circuit package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7092218A JP2606174B2 (en) | 1995-04-18 | 1995-04-18 | Mounting method of two-story electronic circuit package |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08288610A JPH08288610A (en) | 1996-11-01 |
JP2606174B2 true JP2606174B2 (en) | 1997-04-30 |
Family
ID=14048312
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7092218A Expired - Fee Related JP2606174B2 (en) | 1995-04-18 | 1995-04-18 | Mounting method of two-story electronic circuit package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2606174B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007081111A (en) * | 2005-09-14 | 2007-03-29 | Oki Comtec Ltd | Connector mounting board |
-
1995
- 1995-04-18 JP JP7092218A patent/JP2606174B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH08288610A (en) | 1996-11-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |