JPH05226800A - Board for sequence controller and sequence controller - Google Patents

Board for sequence controller and sequence controller

Info

Publication number
JPH05226800A
JPH05226800A JP2542492A JP2542492A JPH05226800A JP H05226800 A JPH05226800 A JP H05226800A JP 2542492 A JP2542492 A JP 2542492A JP 2542492 A JP2542492 A JP 2542492A JP H05226800 A JPH05226800 A JP H05226800A
Authority
JP
Japan
Prior art keywords
connector
sequence controller
board
bus
bus expansion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2542492A
Other languages
Japanese (ja)
Inventor
Mikio Kikko
幹雄 橘高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2542492A priority Critical patent/JPH05226800A/en
Publication of JPH05226800A publication Critical patent/JPH05226800A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits

Abstract

PURPOSE:To reduce the cost, and save the spacing, of a sequence controller by mounting a, first bus extension connector on one surface, and by mounting a second bus extension connector which is connectable with the first connector at a location corresponding to the first connector on another surface. CONSTITUTION:A plurality of elements 2 constituting an input/output circuit are arrayed at the center of a component surface of an I/O board 40, and a plurality of external interfaces 3 are arranged along both edges of that surface in a direction of X with the elements 2 sandwiched between them. An upper connector 11 constituting a bus extension connector 10 is mounted on one end of that surface in a direction of Y, and a lower connector 12 which also constitutes the connector 10 is mounted at the same position as the connector 11 on a soldered surface. Both the upper connector 11 and the lower connector 12 are disposed at a location where a reference position 13 of these connectors is defined by a distance I1 from a fixed hole D of the board 40 in the direction of X and a distance I2 from the hole in the direction of Y.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、シーケンスコントロー
ラ用基板およびシーケンスコントローラに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence controller board and a sequence controller.

【0002】[0002]

【従来の技術】従来のシーケンスコントローラ用基板に
は、図5に示すように、マザーボード50にCPUボー
ド51、I/Oボード52,53,54等をそれぞれ装
着してバス接続するものや、図6に示すように、CPU
ボード60とI/Oボード61,62,63をコネクタ
64,65とケーブル66によりバス接続するものがあ
る。
2. Description of the Related Art A conventional sequence controller board, as shown in FIG. 5, has a motherboard 50 on which a CPU board 51, I / O boards 52, 53, 54, etc. are mounted and connected by a bus. As shown in 6, CPU
There is one in which the board 60 and the I / O boards 61, 62 and 63 are bus-connected by the connectors 64 and 65 and the cable 66.

【0003】[0003]

【発明が解決しようとする課題】上述した従来のシーケ
ンスコントローラ用基板のうち、図5に示すものでは、
マザーボードが必要であり、しかもI/Oボード数ごと
に長さの異なるマザーボードを用意するか、不必要な長
さのマザーボードを設置することになるため、コストが
高く、大きなスペースが必要であるという欠点がある。
Among the above-mentioned conventional sequence controller substrates, the one shown in FIG.
Motherboards are needed, and different motherboards with different lengths are prepared for each number of I / O boards, or motherboards with unnecessary lengths are installed, resulting in high cost and large space. There are drawbacks.

【0004】また、図6に示すものでは、コネクタとケ
ーブルが必要であるため、コストが高く、大きなスペー
スが必要であるという欠点がある。
Further, the structure shown in FIG. 6 has the disadvantages that the cost is high and a large space is required because a connector and a cable are required.

【0005】本発明の目的は、コストが低く、スペース
を節約できるシーケンスコントローラ用基板およびシー
ケンスコントローラを提供することにある。
An object of the present invention is to provide a sequence controller substrate and a sequence controller which are low in cost and save space.

【0006】[0006]

【課題を解決するための手段】本発明のシーケンスコン
トローラ用基板は、一方の面には第1のバス拡張用コネ
クタが取り付けられ、他方の面の前記第1のバス拡張用
コネクタの取付位置に対する位置には前記第1のバス拡
張用コネクタと接続可能な第2のバス拡張用コネクタが
取り付けられていることを特徴とする。
A sequence controller board according to the present invention has a first bus expansion connector mounted on one surface thereof and a mounting position of the first bus expansion connector on the other surface thereof. A second bus expansion connector connectable to the first bus expansion connector is attached to the position.

【0007】このシーケンスコントローラ用基板には、
CPUボードまたはI/Oボードの回路を有するものが
ある。
This sequence controller substrate includes
Some have a circuit of a CPU board or an I / O board.

【0008】本発明のシーケンスコントローラは、シー
ケンスコントローラ用基板を少なくとも2枚有し、これ
らシーケンスコントローラ用基板が第1および第2のバ
ス拡張用コネクタで接続されていることを特徴とする。
The sequence controller of the present invention is characterized in that it has at least two sequence controller boards, and these sequence controller boards are connected by first and second bus expansion connectors.

【0009】[0009]

【作用】各シーケンスコントローラ用基板同士をバス拡
張用コネクタで直接接続するので、スペースが小さくな
るとともに、バス接続用のマザーボードやケーブルのコ
ストが不要となる。
Since the sequence controller boards are directly connected to each other by the bus expansion connector, the space is reduced, and the cost of the bus connecting mother board and cables is eliminated.

【0010】[0010]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0011】図1は本発明の一実施例を示す斜視図であ
る。
FIG. 1 is a perspective view showing an embodiment of the present invention.

【0012】I/Oボード40の部品面には、中央に入
出力回路を構成する複数の素子2が配置され、この素子
2を挾んでX方向の両端部には、外部インターフェース
3が複数配置されている。また、Y方向の一方の端部に
はバス拡張用コネクタ10を構成する上側接続用コネク
タ11が取り付けられ、半田面の同位置にはバス拡張用
コネクタ10を構成する下側接続用コネクタ12が取り
付けられている。上側接続用コネクタ11および下側接
続用コネクタ12は、いずれもその基準部位13がI/
Oボード40の固定穴Dから矢印X方向に距離l1 、矢
印Y方向に距離l2 の位置に配置されている。
On the component side of the I / O board 40, a plurality of elements 2 forming an input / output circuit are arranged in the center, and a plurality of external interfaces 3 are arranged at both ends in the X direction across the element 2. Has been done. An upper connection connector 11 that constitutes the bus extension connector 10 is attached to one end in the Y direction, and a lower connection connector 12 that constitutes the bus extension connector 10 is attached at the same position on the solder surface. It is installed. In both the upper connection connector 11 and the lower connection connector 12, the reference portion 13 is I / O.
It is located at a distance l 1 in the arrow X direction and a distance l 2 in the arrow Y direction from the fixing hole D of the O board 40.

【0013】図2(a),(b)は上側接続用コネクタ
11および下側接続用コネクタ12からなるバス拡張用
コネクタ10を示す詳細図である。
2 (a) and 2 (b) are detailed views showing a bus expansion connector 10 comprising an upper connecting connector 11 and a lower connecting connector 12. As shown in FIG.

【0014】上側接続用コネクタ11は、その下側には
複数のピン11bが設けられており、上側には各ピン1
1bとそれぞれ電気的に接続され、他の上側接続用コネ
クタ11の各ピン11bがそれぞれ挿入可能な穴11a
が設けられている。下側接続用コネクタ12は、上側に
上側接続用コネクタ11の各ピン11bがそれぞれ挿入
可能なやや大きめの穴12aを有し、上側接続用コネク
タ11が挿入、固定可能な形状に形成されている。
The upper connector 11 is provided with a plurality of pins 11b on its lower side, and each pin 1b is provided on the upper side.
Holes 11a which are electrically connected to the respective 1b and into which the pins 11b of the other upper side connecting connector 11 can be inserted respectively.
Is provided. The lower connector 12 has a slightly larger hole 12a into which each pin 11b of the upper connector 11 can be inserted, and is formed in a shape in which the upper connector 11 can be inserted and fixed. ..

【0015】図3は本実施例を用いた複数の基板の接続
例を示す斜視図である。
FIG. 3 is a perspective view showing an example of connection of a plurality of substrates using this embodiment.

【0016】この例では、CPUボード30、I/Oボ
ード41,42,43の各基板が順次積層され、4隅を
連結部材6,7を介してネジ止め固定されている。そし
て、それぞれ図2(a)に示すバス拡張用コネクタ10
により相互にバス接続されている。なお、連結部材6
は、両端部に雌ネジが形成され、連結部材7は一方の端
部に雄ネジが、他方の端部に雌ネジが形成され、順次連
結され両端がネジ止めされている。ただし、CPUボー
ド30からI/Oボード42までの距離が短い場合に
は、連結部材6,7を中空部材とし1個のネジで固定す
ることができる。
In this example, the boards of the CPU board 30 and the I / O boards 41, 42, 43 are sequentially laminated, and the four corners are fixed with screws via the connecting members 6, 7. Then, the bus expansion connector 10 shown in FIG.
Are connected to each other by a bus. The connecting member 6
Has female threads formed on both ends thereof, and the connecting member 7 has male threads formed on one end and female threads formed on the other end, which are sequentially connected and screwed at both ends. However, when the distance from the CPU board 30 to the I / O board 42 is short, the connecting members 6 and 7 can be hollow members and can be fixed with one screw.

【0017】図4はシーケンスコントローラの構成例を
示すブロック図である。
FIG. 4 is a block diagram showing a configuration example of the sequence controller.

【0018】このシーケンスコントローラは、CPUボ
ード30と、I/Oボード40,41,42からなり、
バス拡張用コネクタ10を介してバス31により相互に
接続されている。
This sequence controller comprises a CPU board 30 and I / O boards 40, 41, 42.
They are mutually connected by a bus 31 via the bus expansion connector 10.

【0019】[0019]

【発明の効果】以上説明したように本発明は、シーケン
スコントローラ用基板同士をバス拡張用コネクタで直接
接続することにより、スペースが節約できるとともに、
バス接続用のマザーボードやケーブルが不要となりコス
トを下げることができる効果がある。
As described above, according to the present invention, by directly connecting the sequence controller boards to each other with the bus expansion connector, space can be saved and
This eliminates the need for a bus connection motherboard and cables, and has the effect of reducing costs.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す斜視図である。FIG. 1 is a perspective view showing an embodiment of the present invention.

【図2】(a),(b)はバス拡張用コネクタを示す詳
細図である。
2A and 2B are detailed views showing a bus expansion connector.

【図3】複数の基板の接続例を示す斜視図である。FIG. 3 is a perspective view showing a connection example of a plurality of substrates.

【図4】シーケンスコントローラの構成例を示すブロッ
ク図である。
FIG. 4 is a block diagram showing a configuration example of a sequence controller.

【図5】従来例を示す図である。FIG. 5 is a diagram showing a conventional example.

【図6】従来例を示す図である。FIG. 6 is a diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

10 バス拡張用コネクタ 11 上側接続用コネクタ 12 下側接続用コネクタ 13 基準部位 30 CPUボード 31 バス 40,41,42 I/Oボード 10 Bus Expansion Connector 11 Upper Connection Connector 12 Lower Connection Connector 13 Reference Part 30 CPU Board 31 Bus 40, 41, 42 I / O Board

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 一方の面には第1のバス拡張用コネクタ
が取り付けられ、他方の面の前記第1のバス拡張用コネ
クタの取付位置に対する位置には前記第1のバス拡張用
コネクタと接続可能な第2のバス拡張用コネクタが取り
付けられていることを特徴とするシーケンスコントロー
ラ用基板。
1. A first bus expansion connector is mounted on one surface, and is connected to the first bus expansion connector at a position on the other surface with respect to a mounting position of the first bus expansion connector. A sequence controller board having a possible second bus expansion connector attached thereto.
【請求項2】 CPUボードの回路を有する請求項1記
載のシーケンスコントローラ用基板。
2. The sequence controller substrate according to claim 1, which has a circuit of a CPU board.
【請求項3】 I/Oボードの回路を有する請求項1記
載のシーケンスコントローラ用基板。
3. The sequence controller board according to claim 1, which has an I / O board circuit.
【請求項4】 請求項1記載のシーケンスコントローラ
用基板を少なくとも2枚有し、これらシーケンスコント
ローラ用基板が第1および第2のバス拡張用コネクタで
接続されていることを特徴とするシーケンスコントロー
ラ。
4. A sequence controller comprising at least two sequence controller boards according to claim 1, wherein the sequence controller boards are connected by first and second bus expansion connectors.
JP2542492A 1992-02-12 1992-02-12 Board for sequence controller and sequence controller Pending JPH05226800A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2542492A JPH05226800A (en) 1992-02-12 1992-02-12 Board for sequence controller and sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2542492A JPH05226800A (en) 1992-02-12 1992-02-12 Board for sequence controller and sequence controller

Publications (1)

Publication Number Publication Date
JPH05226800A true JPH05226800A (en) 1993-09-03

Family

ID=12165581

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2542492A Pending JPH05226800A (en) 1992-02-12 1992-02-12 Board for sequence controller and sequence controller

Country Status (1)

Country Link
JP (1) JPH05226800A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09222906A (en) * 1995-10-10 1997-08-26 Foxboro Co:The Field controller for control system
JP2002023811A (en) * 2000-07-11 2002-01-25 Mitsubishi Electric Corp Field equipment controller and method for connecting wiring of connector
JP2017103338A (en) * 2015-12-01 2017-06-08 株式会社安川電機 Electronic apparatus and method of manufacturing electronic apparatus
CN107613643A (en) * 2017-09-07 2018-01-19 贵州航天天马机电科技有限公司 A kind of communicating circuit plate universal architecture with principal and subordinate's identification function
JP2019215645A (en) * 2018-06-12 2019-12-19 株式会社デンソーウェーブ Programmable logic controller

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09222906A (en) * 1995-10-10 1997-08-26 Foxboro Co:The Field controller for control system
JP2002023811A (en) * 2000-07-11 2002-01-25 Mitsubishi Electric Corp Field equipment controller and method for connecting wiring of connector
JP2017103338A (en) * 2015-12-01 2017-06-08 株式会社安川電機 Electronic apparatus and method of manufacturing electronic apparatus
CN107613643A (en) * 2017-09-07 2018-01-19 贵州航天天马机电科技有限公司 A kind of communicating circuit plate universal architecture with principal and subordinate's identification function
JP2019215645A (en) * 2018-06-12 2019-12-19 株式会社デンソーウェーブ Programmable logic controller

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