JP2592164B2 - Protection circuit and protection device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection circuit and a protection device for protecting a semiconductor integrated circuit from damage caused by static electricity.

[Conventional technology]

In recent consumer products and industrial products, resins and chemical fibers are almost always used. One of the drawbacks of these products is that they tend to be charged with static electricity, and because offices and factories have low humidity due to complete air conditioning, static electricity is present everywhere.

On the other hand, in the field of semiconductor integrated circuits, in order to achieve higher performance and higher integration, as the miniaturization of elements progresses, the problem of destruction of elements due to static electricity is highlighted, and countermeasures have become an important issue. I have.

Semiconductor integrated circuits destroyed by static electricity often do not show traces of their destruction by observation with an optical microscope, or according to recent advanced analysis equipment such as scanning electron microscopes, It can be seen that the PN junction that constitutes is broken locally. The cause of this destruction is that an electrostatic surge is applied to the PN junction in the opposite direction, and charged particles are accelerated at this part, causing avalanche collapse, and this phenomenon generates heat by concentrating on the local part of the PN junction It is considered that this causes the semiconductor crystal lattice to be broken.

With reference to FIG. 4, a description will be given of a conventional technique used in a semiconductor integrated circuit as a countermeasure against such static electricity.

As shown in FIG. 4, a diode 34 and a diode 35 are connected in series between the power supply terminal 7 and the ground terminal 2 of the main circuit portion 6 of the semiconductor integrated circuit.
The anode of the diode 34 and the cathode of the diode 35 are connected to the terminal 1 of the main circuit portion 6.

In such a configuration, the positive electrostatic surge applied to the terminal 1 is absorbed by the power supply (not shown) from the power supply terminal 7 through the diode 34 or is absorbed by the main circuit portion 6 of the semiconductor integrated circuit. .

On the other hand, a negative electrostatic surge is absorbed by the ground terminal 2 through the diode 35.

Next, another conventional example will be described with reference to FIGS. 5 (a) and 5 (b).

This conventional example is a "semiconductor device having a safety circuit" (hereinafter referred to as "Document 1") disclosed in JP-A-52-102689.

As shown in FIG. 5 (a), the collector and the emitter of the NPN transistor are connected between the terminal of the main circuit portion 6 of the semiconductor integrated circuit and the ground terminal 2, and the resistor 5 is connected between the base and the emitter. Is done.

The conventional semiconductor device thus configured protects the main circuit portion 6 of the semiconductor integrated circuit from the electrostatic surge applied to the terminal 1 by the operation of the protection circuit including the transistor 3 and the resistor 5. . That the holding voltage V _B over voltage shown in FIG. 5 (b) is applied to the terminal, the transistor 3 is conductive, electrostatic surge is absorbed.

FIG. 5 (a) is a circuit diagram showing the embodiment.
A "semiconductor integrated circuit" (hereinafter referred to as "Document 2") similar to the above is disclosed in JP-A-62-8037.

The major difference between Documents 1 and 2 is that, in Document 1, an emitter, a base, and a collector are formed on a semiconductor surface, and thus a so-called lateral transistor is used, in which a current flows on the surface. Document 2 discloses that a so-called vertical transistor is used, in which an emitter, a base, and a collector are formed in the depth direction of a semiconductor, and thus a current flows in the depth direction.

Further, with respect to the formation of the resistor 5,
However, in Reference 2, they are formed separately in the collector region of the transistor 3.

In such a protection circuit, the selection of the value of the resistor 5 is important for the electrostatic breakdown resistance and operating characteristics of the elements constituting the protection circuit itself, and is described in detail in Reference 2 including the reason.

[Problems to be solved by the invention]

However, in the conventional example shown in FIG. 4, the diode 3 plays a sufficient role of a protection circuit against a negative electrostatic surge applied to the terminal 1 (with respect to the ground terminal 2). When a surge is applied, the diode 34 has the following problems.

In a semiconductor integrated circuit in which the voltage applied to the terminal 1 must guarantee the operation to a higher range than the power supply voltage, the voltage of the terminal 1 is clamped to the power supply voltage by the diode 34, so that the semiconductor integrated circuit operates normally. There was a problem that a proper operation could not be expected.

In recent years, a battery or the like is often used as a power supply for a semiconductor integrated circuit. Therefore, the main circuit portion 6 of the semiconductor integrated circuit is designed to operate with low power consumption. Therefore, the main circuit portion 6 necessarily has high impedance, and the electrostatic surge is hardly absorbed through the main circuit portion 6. In particular, when handling a semiconductor integrated circuit in which a power supply is not connected to the power supply terminal 7, the main circuit portion 6 is likely to be damaged by the electrostatic surge applied to the terminal 1.

Further, it is necessary to take out a power supply wiring (not shown) close to the terminal and connect the diodes 34 and 35. In a semiconductor integrated circuit, a large number of circuit elements are configured in a complicated pattern, a required number of bonding pads (not shown) serving as terminals are arranged on a chip, and ground wiring is provided. It is extremely difficult to draw the above-mentioned power supply wiring in terms of the arrangement of elements, and even if it can be realized, there is a problem that the size of a chip is increased.

In the conventional example shown in FIGS. 5 (a) and 5 (b), the protection element (transistor and resistor) can be arranged only in the vicinity of the bonding pad serving as the terminal of the semiconductor integrated circuit.

However, when the protection circuits described in the above-mentioned Documents 1 and 2 are used, it is considered that the main circuit portion 6 is not damaged because the wiring is connected from the terminal 1 to the protection circuit and the main circuit portion 6 in this order. But often destroyed.

The cause of this destruction is related to the operation speed of the protection circuit. That is, when an excessive voltage is applied in a short time such as an electrostatic surge, the applied electrostatic surge arrives at the protected circuit (that is, the main circuit portion 6) before the protection circuit starts operating. The main circuit part is destroyed.

5A, an avalanche collapse occurs at the base-collector junction of the transistor 3 due to an electrostatic surge applied to the terminal 1 shown in FIG. Since the transistor operates only when the potential difference of
It takes time for the transistor 3 to start absorbing the electrostatic surge.

In view of the above problems, an object of the present invention is to provide a protection circuit and a protection device which have an operation speed and resistance capable of absorbing an electrostatic surge, have a simple layout design, and have a small chip occupancy.

[Means for solving the problem]

The protection circuit according to claim 1 includes a transistor, a capacitor connected between a base and a collector of the transistor,
And a resistor connected between the base and the emitter of the transistor.

According to a second aspect of the present invention, there is provided a protection device, comprising: an N-type collector region serving as a collector of a transistor formed on a P-type semiconductor substrate; and a P-type base region serving as a base of the transistor formed in the collector region. A P-type resistance region formed in the collector region, an N-type emitter region formed in the base region as an emitter of the transistor, an insulating film formed on the base region as a capacitor, and an insulating film formed on the insulating film. An electrode of the formed capacitor is provided, the electrode is connected to the collector region, the resistance region is connected between the base region and the emitter region, and the emitter region is connected to the semiconductor substrate.

According to a third aspect of the present invention, there is provided a protection device including an N-type base region serving as a base of a transistor formed on a P-type semiconductor substrate, a semiconductor substrate, and a P-type isolation diffusion region formed on the semiconductor substrate. A collector region, a P-type emitter region formed in the base region as an emitter of a transistor, an N-type resistance region formed in the base region, an insulating film formed on the base region as a capacitor, And a capacitor electrode formed on the film, wherein the capacitor electrode is connected to the collector region, and a resistance region is connected between the base region and the emitter region.

[Action]

According to the configuration of the present invention, since the capacitor is connected between the base and the collector of the transistor and the resistor is connected between the base and the emitter of the transistor, the electrostatic surge applied to the terminal instantaneously changes the capacitance and the base and the emitter of the transistor. The high-speed operation of the protection circuit can be realized by flowing the current in the forward direction. Further, if such a protection circuit is employed in a semiconductor integrated circuit, the layout design and connection of the elements are simple, and no extra wiring is required, so that a protection device occupying a small area on a semiconductor chip can be obtained. it can.

〔Example〕

Figure 1 (a) is a circuit diagram showing a protection circuit of an embodiment of the present invention, FIG. 1 (b) the relationship between the operating voltage V _B of the resistor and the protection circuit constituting the protective circuit of the embodiment Figure showing the first
FIG. 3C is a circuit diagram showing an example in which a PNP transistor is used as the protection circuit of the embodiment.

As shown in FIG. 1 (a), a terminal 1 and a ground terminal 2
In between, the collector and the emitter of the NPN transistor 3 were connected respectively, the capacitor 4 was connected between the base and the collector of the transistor, and the resistor 5 was connected between the base and the emitter of the transistor.

The terminal 1 is connected to a main circuit portion 6 of the semiconductor integrated circuit, and 7 is a power supply terminal.

 The operation of the protection circuit thus configured will be described below.

When a positive electrostatic surge is applied to the terminal 1 with respect to the ground terminal 2, a sharp current flows in the forward direction from the base to the emitter of the transistor 3 through the capacitor 4, and the transistor conducts. Instantly absorbs electrostatic surges.

If an electrostatic surge still remains, avalanche collapse occurs between the collector and the base of the transistor 3 during the subsequent period, and this current flows through the resistor 5 to generate a potential difference at both ends of the resistor 5. Are conducted, the remaining electrostatic surge is absorbed.

As described above, the operation speed of the protection circuit can be improved by the capacitor 4 connected between the collector and the base of the transistor 3, and most of the electrostatic surge can be reduced by the forward operation between the capacitor 4 and the base and the emitter of the transistor 3. As a result, surge resistance can be improved.

The selection of the value of the resistor 5 is important in determining the characteristics of the protection circuit. Also in this protection circuit, the transistor 3
The characteristic of the voltage V and current I between the collector-emitter Figure 5 becomes a (b), the the resistor 5 wherein the operating voltage V _B of the protection circuit (a voltage V _B of the transistor 3 conducts)
Is as shown in FIG. 1 (b).

That is, if the value R of the resistor 5 is made sufficiently small, the operating voltage
V _B becomes equal to the value of the avalanche breakdown voltage V _CBO between the collector and the base of the transistor, and if the value R of the resistor 5 is made sufficiently large, the operating voltage V _B becomes the avalanche breakdown voltage V _CEO between the collector and the emitter of the transistor. Is equal to the value of

Thus it is possible to determine the operating voltage V _B the protection circuit starts to operate by the value R of the resistor 5, the selection of the value R of the resistor 5, do have to consider that described below.

If the value R of the resistor 5 is reduced, the transistor 3 does not operate unless the current flowing due to the avalanche collapse between the collector and the base of the transistor 3 does not operate. Therefore, the protection circuit does not operate sufficiently. If the current caused by the avalanche collapse is too large, the avalanche collapse is the dielectric breakdown of the PN junction, causing complete breakdown of the PN junction,
The function of the protection circuit itself is lost.

On the other hand, when the value R of the resistor 5 is increased, the transistor 3 operates with a small current flowing due to avalanche collapse between the collector and the base, and the protection circuit operates satisfactorily. The transistor 3 amplifies even a small leak current that enters. As a result, the transistor 3 is turned on even during the normal operation of the semiconductor integrated circuit, which causes a drawback that the current is drawn from the terminal 1.

In consideration of the above, the resistance value R is determined by the transistor 3
The operating voltage V _B depends on the avalanche breakdown voltage V
1 is the value R when transitioning from _CBO to avalanche breakdown voltage V _CEO
It is preferable to be about 0 kΩ.

On the other hand, selection of the value C of the capacitor 4 is preferably a large value in order to improve the operation speed of the protection circuit. However, an excessively large capacitance is not preferable because it reduces the input impedance of the semiconductor integrated circuit. In particular, large terminals are not suitable for terminals expected to operate at high frequencies. For example, a capacitance value C of 1PF reduces the input impedance of the semiconductor integrated circuit to 1.6 kΩ at a frequency of 100 MHz.

The operation of the protection circuit described above is a protection circuit composed of NPN transistors shown in FIG. 1A, but the protection circuit is a PNP transistor 3 'shown in FIG. 1C. Can also be configured.

In this case, when a positive electrostatic surge is applied to the terminal 2, a peak current flows from the emitter of the transistor to the base and the capacitor 4, and the transistor 3 ′
Conducts and instantaneously absorbs the electrostatic surge. If an electrostatic surge still remains, avalanche collapse occurs between the base and the collector of the transistor 3 'during a period subsequent to this, and the remaining electrostatic surge is absorbed by the conduction of the transistor 3'.

FIG. 2A is a plan view showing the protection device according to the first embodiment of the present invention, and FIG.
FIG. 2C is a cross-sectional view taken along the line A ', and FIG. 2C is a circuit diagram of the protection device.

As shown in FIGS. 2A and 2B, an N-type buried diffusion layer 9 of a high-concentration impurity is formed on a P-type semiconductor substrate 8, and this N-type buried diffusion layer is formed. An N-type epitaxial region 10 serving as a collector region was formed on 9, and a P-type isolation diffusion region 11 was formed in a region penetrating the N-type epitaxial region 10 and separating it into an island shape.

The N-type epitaxial region 10 includes an N-type diffusion region 12 for extracting an electrode from the N-type epitaxial region 1 (which serves as a collector region), a P-type diffusion region 13 serving as a base region and a lower electrode of a capacitor. Is further formed in the P-type diffusion region 13 as an N-type diffusion region serving as an emitter region.
14 formed.

The resistor 15 is formed by the P-type diffusion region 13 and formed in the same step as the P-type diffusion region 13 serving as the base region and the lower electrode of the capacitor. To simplify the layout design, these two regions are used. Are connected.

The insulating film 17 forming the capacitor 16 is formed on the P-type diffusion region 13 serving as a base region, and includes a silicon oxide film 18.

19 is an upper electrode of the capacitor, 20 is an emitter electrode, 21 is a collector electrode, and 22 is a silicon oxide film 18 for forming an electrode.
The opening formed in FIG.

The wiring 23 extends from the bonding pad 24 to form the upper electrode 19 of the capacitor 16, which is connected to the collector electrode 21 of the transistor 3, and then connected to a protected circuit (not shown) formed on the semiconductor substrate 8. Connected.

The wiring 25 connects the emitter electrode 20 and the resistor 15,
Furthermore, it was connected to the ground terminal 2.

FIG. 2 (c) is a circuit diagram of the protection device thus configured.
Shown in

As shown in FIG. 2 (c), when a positive electrostatic surge is applied to the terminal 1, a sudden current flows through the capacitor 4 through the transistor 3 instantaneously from the base to the emitter.
In addition, the transistor 3 is turned on by the forward operation of the transistor 3 to instantaneously absorb the electrostatic surge. In this case, in FIGS. 2 (a) and 2 (b),
The current flows to the wiring 23, the capacitor 16, the P-type diffusion region 13, and the N-type diffusion region 14. At this time, high-speed operation can be realized by the capacitor 4. If an electrostatic surge still remains, avalanche collapse occurs between the collector and the base of the transistor 3 during the subsequent period, and a current flows through the resistor 5 due to the avalanche collapse. When a current flows through the resistor 5, a potential difference occurs between both ends of the resistor 5. The potential difference between both ends of the resistor 5, that is, the potential difference between the base and the emitter of the transistor is caused to conduct the transistor 3, thereby absorbing the remaining electrostatic surge.

In order to realize a high-speed operation of the protection circuit, it is preferable to form a large capacitance. For example, the same film as the silicon oxide film 18 is used as the insulating film 17 constituting the capacitance, and the thickness is 0.2 [μm]. If the area is 2500 [μm ² ], a capacitance of 0.5 [pF] can be formed. However, it is dangerous to make the insulating film 17 extremely thin in order to obtain a large capacity in a small area, since the insulating film may be destroyed by an electrostatic surge. In such a case, by using, for example, a silicon nitride film having a large dielectric constant and a high withstand voltage as the insulating film, it is possible to obtain approximately twice the capacity of a silicon oxide film with the same geometric dimensions.

Further, in order to improve the surge resistance of the protection circuit, it is necessary to prevent thermal destruction due to current concentration locally on the element. In this sense, it is preferable to flow the current in a plane rather than in a line, and in a cross-sectional area rather than in a plane. As is well known, in a lateral transistor, current flows laterally near the surface of the semiconductor, whereas the protection device of the embodiment is a vertical transistor as shown in FIG. 2 (b). Basically, the current flows from the collector region (N-type epitaxial region 10 and N-type buried diffusion region 9) to the base region (P-type diffusion region 13) and the emitter region (N-type diffusion region 9).
Since it flows with a cross-sectional area in the vertical direction (arrow A) to 14),
Surge resistance can be improved. Further, the surge resistance can be improved by making the current easier to flow by the N-type buried diffusion region 9 having a high impurity concentration shown in FIG. 2 (b).

Further, the protection device of the embodiment absorbs most of the electrostatic surge by the forward operation of the transistor 3, so that the current due to avalanche collapse hardly flows between the collector and the base.
Therefore, surge resistance can be further improved.

An important point in the arrangement of the protection device is that the wiring 23 passes from the bonding pad 24 through the protection device and then to a protected circuit (not shown), thereby realizing a high-speed operation of the protection circuit. For this purpose, it is preferable that the upper electrode 19 of the capacitor 16 is connected next to the bonding pad 24.

In the above description, the case where a positive electrostatic surge is applied to the wiring 23 with respect to the wiring 25 connected to the ground terminal 2 has been described, but a negative electrostatic surge (for the wiring 25 connected to the ground terminal). As shown in FIG. 2 (a) and FIG.
A PN junction formed by an N-type buried diffusion region 9 and an N-type epitaxial region 10 serving as a collector region, and a P-type semiconductor substrate 8 and a P-type isolation diffusion region 11 shown in FIG. A diode X shown in c) is obtained, and the diode X is biased in the forward direction, so that a negative electrostatic surge can be absorbed.

FIG. 3 (a) is a plan view showing a protection device according to a second embodiment of the present invention, and FIG. 3 (b) is a sectional view taken along line A- of FIG. 3 (a).
FIG. 3 (c) is a sectional view taken along the line A ', and FIG. 3 (c) is a circuit diagram of the protection device.

An N-type epitaxial region 26 serving as a base region and a lower electrode of a capacitor is formed on a P-type semiconductor substrate 8.
In the epitaxial region 26, P serving as an emitter region is formed.
Forming an N-type diffusion region 27;
A P-type separation / diffusion region 28 is formed in a region where the islands are separated into islands.

The resistor 29 is formed in the N-type region, and is formed in the same process as the base region and the N-type epitaxial region 26 serving as the lower electrode of the capacitor. To simplify the layout design, these two regions are formed successively. I have.

The collector region was formed by the P-type semiconductor substrate 8 and the P-type isolation diffusion region 28.

The insulating film 17 forming the capacitance 16 is a silicon oxide film 18
Formed.

19 is the upper electrode of the capacitor 16, 20 is the emitter electrode, 21 is the collector electrode, and 22 is the silicon oxide film 1 for forming the electrode.
8 shows the opening formed.

The wiring 30 was extended from the bonding pad 24, connected to the resistor 29 and the emitter electrode 20 of the transistor 3 ', and then connected to a protected circuit (not shown) formed on the semiconductor substrate 1.

The wiring 32 formed the upper electrode 19 of the capacitor 16, connected the collector electrode 21, and further connected to the ground terminal 2.

The circuit diagram of the protection device thus configured is shown in FIG. 3 (c).
The operation and design considerations of the protection device are the same as those of the first embodiment except that the transistor of the first embodiment is replaced with a PNP type from an NPN type.

When a positive electrostatic surge is applied to the wiring 32 to the wiring 32, a current flows in a direction indicated by an arrow B in FIG.

When a negative electrostatic surge is applied to the terminal 1 with respect to the wiring 32 connected to the ground terminal 2, the P-type semiconductor substrate 8
And a PN junction formed by the P-type isolation diffusion region 28 and the N-type resistor 29 becomes a diode X shown in FIG.
This diode X can absorb a negative electrostatic surge.

〔The invention's effect〕

According to the protection circuit and the protection device of the present invention, the capacitance is connected between the base and the collector of the transistor,
By connecting a resistor between the emitters, it is possible to obtain a protection circuit which can operate at high speed against an electrostatic surge having a rapid and high voltage and has excellent surge resistance. In addition, by employing this protection circuit as a semiconductor integrated circuit, a protection device that protects the semiconductor integrated circuit from electrostatic surges with good operability can be obtained. Further, since the wiring design of the element is completed only around the terminals and no extra wiring is required, there is no complexity in the design, the capacitance is formed on the base region, and the resistor is formed in the collector region. Thus, the area occupied by the protection device on the semiconductor chip can be reduced, and its practical value is high.

[Brief description of the drawings]

Figure 1 (a) is a circuit diagram showing a protection circuit of an embodiment of the present invention, FIG. 1 (b) the relationship between the operating voltage V _B of the resistor and the protection circuit constituting the protective circuit of the embodiment FIG. 1C is a circuit diagram showing an example in which a PNP transistor is used as the protection circuit of the embodiment, and FIG. 2A is a protection device of the first embodiment of the present invention. FIG. 2 (b) is a cross-sectional view taken along the line AA 'shown in FIG. 2 (a), FIG. 2 (c) is a circuit diagram of the protection device, and FIG. 3 (a) is the present invention. FIG. 3 (b) is a cross-sectional view taken along line AA 'shown in FIG. 3 (a), and FIG. 3 (c).
4 is a circuit diagram of the protection device, FIG. 4 is a circuit diagram showing a conventional protection circuit, FIG. 5 (a) is a circuit diagram showing the protection circuit, FIG.
FIG. 2B is a diagram showing the relationship between the voltage V and the current I of the transistor. 3,3 '... transistor, 4,16 ... capacitance, 5,15,29 ... resistor, 8 ... semiconductor substrate, 10 ... N-type epitaxial region (collector region), 13 ... P-type diffusion region ( Base region), 14 N-type diffusion region (emitter region), 17 insulating film, 26 N-type epitaxial region (base region),
27 P-type diffusion region (emitter region), 28 P-type separation diffusion region

Claims (3)

(57) [Claims] 1. A protection circuit comprising a transistor, a capacitor connected between a base and a collector of the transistor, and a resistor connected between a base and an emitter of the transistor. 2. An N-type collector region serving as a collector of a transistor formed on a P-type semiconductor substrate; a P-type base region serving as a base of the transistor formed in the collector region; A P-type resistor region formed in the base region; an N-type emitter region formed in the base region as an emitter of the transistor; an insulating film serving as a capacitor formed on the base region; An electrode of the capacitor, connecting the electrode and the collector region, connecting the resistance region between the base region and the emitter region,
A protection device, wherein the emitter region is connected to the semiconductor substrate. 3. An N-type base region serving as a base of a transistor formed on a P-type semiconductor substrate; a collector region including the semiconductor substrate and a P-type isolation diffusion region formed on the semiconductor substrate; A P-type emitter region formed in the base region and serving as an emitter of the transistor; an N-type resistance region formed in the base region; an insulating film serving as a capacitor formed on the base region; A protection device comprising: an electrode of the capacitor formed thereon; connecting the electrode of the capacitor to the collector region; and connecting the resistance region between the base region and the emitter region.