JPH03289164A - Protective circuit and protective device - Google Patents

Abstract

PURPOSE:To enable execution of a high-speed operation against an electrostatic surge being rapid and having a high voltage and to improve resistance to the surge by connecting a capacitor between the base and the collector of a transistor and by connecting a resistor between the base and the emitter thereof. CONSTITUTION:When an electrostatic surge being positive to a ground terminal 2 is impressed on a terminal 1, a peak current flows forward from the base of a transistor 3 to the emitter thereof through a capacitor 4, and by the transistor being put in continuity, the electrostatic surge is absorbed instantaneously. When the electrostatic surge remains further, an avalanche phenomenon occurs between the collector and the base of the transistor 3 in a subsequent period and this current flows through a resistor 5. Consequently a potential difference occurs between the opposite ends of the resistor 5, the transistor 3 is put in continuity and thereby the remaining electrostatic surge is absorbed. Thus, the capacitor 4 provided in approximation between the collector and the base of the transistor 3, an operating speed of a protective circuit can be improved, and by most of the electrostatic surge being absorbed, resistance to the surge can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a protection circuit and a protection device for protecting semiconductor integrated circuits from damage caused by static electricity.

[Conventional technology]

Resins and chemical fibers are almost always used in recent consumer and industrial products. One of the drawbacks of these products is that they are easily charged with static electricity, and because offices and factories are fully air-conditioned and have low humidity, static electricity is present everywhere.

On the other hand, in the field of semiconductor integrated circuits, in order to achieve even higher performance and higher integration, the miniaturization of elements is progressing, and the risk of element breakdown due to static electricity has become a focus, and countermeasures have become an important issue. ing.

Semiconductor integrated circuits destroyed by static electricity often have no trace of destruction when observed using an optical microscope, but recent advanced analysis equipment such as scanning electron microscopes has shown that semiconductor integrated circuits can be damaged by static electricity. It can be seen that the PN junction constituting the structure is locally destroyed. The cause of this destruction is that an electrostatic surge is applied to the PN junction in the opposite direction, accelerating charged particles in this area, causing avalanche collapse, and this phenomenon concentrates locally on the PN junction, generating heat. It is thought that this leads to destruction of the semiconductor crystal lattice.

A conventional technique used in semiconductor integrated circuits as a countermeasure against static electricity will be explained with reference to FIG.

As shown in FIG. 4, the main circuit portion 6 of the semiconductor integrated circuit
A diode 34 and a diode 35 connected in series are connected between the power supply terminal 7 and the ground terminal 2 of. The anode of the diode 34 and the cathode of the diode 35 are connected to the terminal 1 of the main circuit portion 6.

In such a fi command, a positive electrostatic surge applied to the terminal 1 is absorbed from the power supply terminal 7 to the power supply (not shown) through the diode 34, or absorbed into the main circuit portion 6 of the semiconductor integrated circuit. Ru.

- Koga's electrostatic surge is absorbed into the ground terminal 2 through the diode 35.

Next, another conventional example will be explained using FIG. 5(a) and FIG. 5(b).

This conventional example is a semiconductor device J having an r safety circuit disclosed in Japanese Patent Application Laid-Open No. 52-102689 (hereinafter referred to as "Reference 1").
That's what it means. ).

As shown in FIG. 5(a), the collector-emitter of an NPN transistor is connected between the terminal of the main circuit portion 6 of the semiconductor integrated circuit and the ground terminal 2, and a resistor 5 is connected between the base and the terminal. is connected.

The conventional semiconductor device configured in this manner includes transistors 3. The main circuit portion 6 of the semiconductor integrated circuit is protected from electrostatic surge applied to the terminal 1 by the function of the protection circuit composed of the resistor 5. That is, the holding voltage V shown in FIG.

When the above voltage is applied to the terminal, the transistor 3 becomes conductive, thereby absorbing the electrostatic surge.

Furthermore, if shown as a circuit diagram, a "semiconductor integrated circuit J" (hereinafter referred to as "Document 2") which is similar to FIG.

The major difference between Documents 1 and 2 is that in Document 1, the emitter base collector of the transistor 3 is formed on the semiconductor surface, and therefore current flows on the surface.
While it uses so-called lateral transistors,
In Document 2, a so-called vertical transistor is used in which the base and collector are formed in the depth direction of the semiconductor, and therefore current flows in the depth direction.

Regarding the formation of the resistor 5, in Document 1, the base region of the transistor 3 is shared, but in Document 2, it is formed separately in the collector region of the transistor 3.

In such a protection circuit, the selection of the value of the resistor 5 is important for the electrostatic breakdown resistance and operating characteristics of the elements constituting the protection circuit, and the reason is described in detail in Document 2.

[Problem to be solved by the invention]

However, in the conventional example shown in FIG. 4, the diode 3 sufficiently plays the role of a protection circuit against the negative electrostatic surge applied to the terminal 1 (with respect to the ground terminal 2).
When a positive electrostatic surge is applied, the diode 34 has the following problems.

In a semiconductor integrated circuit where the voltage applied to terminal 1 must guarantee operation in a range higher than the power supply voltage, the voltage at terminal 1 is clamped to m voltage by the diode 34, so that the semiconductor integrated circuit There was a problem that normal operation could not be expected.

In addition, recently batteries are often used as a power source for semiconductor integrated circuits, so the main circuit parts of semiconductor integrated circuits are
is designed to operate with low power consumption. Therefore, the main circuit portion 6 inevitably becomes high impedance,
Electrostatic surges are difficult to absorb through this main circuit portion 6. Particularly when handling a semiconductor integrated circuit in which Tin is not connected to the power supply terminal 7, the main circuit portion 6 is likely to be destroyed by electrostatic surge applied to the terminal 1.

Also, take out the power wiring (not shown) close to the terminal,
Diodes 34.35 must be connected. In a semiconductor integrated circuit, a large number of circuit elements are configured in a complicated pattern, and a necessary number of bonding pads (not shown) that serve as terminals are placed on the chip, as well as a ground wiring. It is extremely difficult to draw the above-mentioned power supply wiring up to this point in terms of element arrangement, and even if it were possible, there would be problems such as an increase in the size of the chip.

Furthermore, in the conventional example shown in FIGS. 5(a) and 5(a), the protective elements (transistors and resistors) can be placed only in the vicinity of the bonding pads that serve as terminals of the semiconductor integrated circuit. And when using the protection circuit described in Document 2, the wiring is connected from terminal l to the protection circuit,
Since the main circuit parts 6 are connected in this order, it is thought that the main circuit parts 6 will not be destroyed, but they often are.

The cause of this destruction is related to the operating speed of the protection circuit.

In other words, if an excessive voltage is applied for a short period of time due to an electrostatic surge, the applied electrostatic surge may reach the protected circuit (i.e. the main circuit part 6) before the protection circuit starts operating. , leading to the destruction of the main circuit parts.

This is because an electrostatic surge applied to the terminal 1 shown in FIG. The transistor operates only when the potential difference between the two becomes a voltage that makes transistor 3 conductive, so
It takes time for this transistor 3 to start absorbing the electrostatic surge.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a protection circuit and a protection device that have operating speed and durability capable of absorbing electrostatic surges, are simple in layout design, and have a low chip occupancy rate.

[Means to solve the problem]

The protection circuit according to claim (1) includes a transistor, a capacitance connected between the base and collector of the transistor,
It is equipped with a resistor connected between the base and emitter of the transistor.

The protection device according to claim (2) includes: an N-type collector region that serves as a collector of a transistor formed on a P-type semiconductor substrate; and a P-type base region that serves as a base of a transistor formed in this collector region. , a P-type resistance region formed in the collector region, an N-type emitter region formed in the base region to serve as the emitter of the transistor, an insulating film formed on the base region to serve as a capacitor, and an insulating film formed on this insulating film. A capacitance electrode is formed, the electrode is connected to a collector region, a resistance region is connected between a base region and an emitter region, and an emitter region is connected to a semiconductor substrate. The protection device described in (3) includes an N-type base region which is formed on a P-type semiconductor substrate and serves as a base of a transistor, and a collector region consisting of a semiconductor substrate and a P-type isolation diffusion region formed on this semiconductor substrate. , a P-type emitter region formed in the base region to serve as a transistor emitter, an N-type resistance region formed in the Heath region, an insulating film to serve as a capacitor formed on the base region, and this insulating film. The capacitor electrode is connected to the collector region, and the resistor region is connected between the base region and the emitter/vine region.

[Effect]

According to the configuration of this invention, since a capacitor is connected between the base and collector of the transistor, and a resistor is connected between the base and the collector of the transistor, electrostatic surges applied to the terminals are instantly absorbed by the capacitor and the base of the transistor.・By flowing forward between the emitters, high-speed protection circuit operation can be achieved. Furthermore, if such a protection circuit is adopted in a semiconductor integrated circuit, the layout design and connection of elements will be easy, and extra wiring will be unnecessary, making it possible to obtain a protection device that occupies less space on the semiconductor chip. can.

〔Example〕

FIG. 1(a) is a circuit diagram showing a protection circuit according to an embodiment of the present invention, and FIG. Figure shown, 1st
Figure (C) is a circuit diagram showing an example in which a PNP type transistor is used as the protection circuit of the same embodiment.

As shown in FIG. 1(a), the collector and emitter of an NPN transistor 3 are connected between the terminal 1 and the ground terminal 2, and a capacitor 4 is connected between the heath and collector of the transistor. A resistor 5 was connected between the base and emitter of.

Note that the terminal 1 is connected to the main circuit portion 6 of the semiconductor integrated circuit, and 7 indicates a power supply terminal.

The operation of the protection circuit configured in this way will be explained below.

When a positive electrostatic surge is applied to the terminal 1 with respect to the ground terminal 2, a sharp current flows in the forward direction from the base of the transistor 3 to the emitter and the emitter through the capacitor 4, and the transistor becomes conductive. This instantly absorbs electrostatic surges.

Furthermore, if the electrostatic surge remains, an avalanche collapse occurs between the collector and base of the transistor 3 in the subsequent period, and this current flows through the resistor 5, creating a potential difference across the resistor 5, and the transistor 3 becomes conductive to absorb the remaining electrostatic surge.

In this way, the operation speed of the protection circuit can be improved by the capacitor I4 connected between the collector and base of the transistor 3, and most of the electrostatic surge can be absorbed by the forward direction operation between the capacitor 4 and the heath and emitter of the transistor 3. By absorbing it, surge resistance can be improved.

Note that the selection of the value of the resistor 5 is important in determining the characteristics of the protection circuit. In this protection circuit as well, the characteristics of the voltage ■ and current I between the collector and emitter of the transistor 3 are shown in Figure 5(b). vl) and the resistor 5 (the relationship with JR is shown in Fig. 1~).

That is, if the (I!R) of the resistor 5 is made sufficiently small, the operating voltage V becomes equal to the avalanche collapse voltage V CBO between the collector and base of the transistor, and if the value R of the resistor 5 is made sufficiently large, the operating voltage (2) 8 is equal to the avalanche collapse voltage v ctoO between the transistor collector and the metal ivy.

Therefore, the operating voltage Vll at which the protection circuit starts operating can be determined by the value R of the resistor 5.
When selecting the value R, the following must be considered.

If 4riR of the resistor 5 is made small, unless the current that flows due to the avalanche collapse between the collector and base of the transistor 3 is large, the transistor 3 will not operate, and therefore the protection circuit will not operate sufficiently; If the current due to the avalanche collapse is too large, the avalanche collapse will cause P
Since this is a dielectric breakdown of the N junction, the PN junction will be completely destroyed, and the protection circuit itself will lose its function.

On the other hand, if the (aR) of the resistor 5 is increased, a small current flowing due to the avalanche collapse between the collector and the base will cause the transistor 3 to
It works, and the protection circuit works for a minute, but the resistance 5
If the value R is increased, the transistor 3 will amplify even the slightest leakage current flowing into the base. As a result, the transistor 3 becomes conductive even during normal operation of the semiconductor integrated circuit, causing the inconvenience that current is drawn from the terminal 1.

Considering the above, the value R of the resistor 5 is determined by the value R of the transistor 3.
The operating voltage ■I varies from the avalanche collapse voltage V CMO to the avalanche collapse voltage V cffi, although it also depends on the characteristics of the .

It is preferable to set the value R to about 10 Ω when transitioning to .

On the other hand, the value C of the capacitor 4 is preferably selected to be a large value in order to improve the operating speed of the protection circuit. However, too large a capacitance is undesirable because it lowers the input impedance of the semiconductor integrated circuit. For example, the capacitance value C of an IPF reduces the human power impedance of a semiconductor integrated circuit to 1.6 Ω at a frequency of 100 MHz.

The operation of the above-mentioned protection circuit is explained as a protection circuit consisting of an NPN type transistor shown in FIG. It can also be configured by

In this case, when a positive electrostatic surge is applied to terminal 2, a sharp current flows from the emitter of the transistor to the base and capacitor 4, causing transistor 3 to conduct and instantly discharging the static electricity. Absorb surge. Furthermore, if the electrostatic surge remains, an avalanche collapse occurs between the base and emitter of the transistor 3° in the subsequent period, and the transistor 3'' becomes conductive to absorb the remaining electrostatic surge.

FIG. 2(a) is a plan view showing the protection device of the first embodiment of the present invention, FIG. C) shows the circuit diagram of the protection device.

As shown in FIGS. 2(a) and 2(b), on the P-type semiconductor substrate 8, there is an N-type buried diffusion layer 9 of high concentration impurity.
An N-type epitaxial region 10 is formed on this N-type buried diffusion layer 9 to serve as a collector region. A diffusion region 11 was formed.

In the N-type epitaxial region 10, there are an N-type diffusion region 12 for taking out an electrode from this N-type epitaxial region 10 (which becomes a collector region), and a P-type diffusion region which becomes a base region and a lower electrode of a capacitor]3. Further, in this P type diffusion region 13, an N type diffusion region 14 which becomes an emitter region was formed.

Furthermore, the resistor 15 is formed by the P-type diffusion region 13, and is formed in the same process as the P-type diffusion region 13 which becomes the base region and the lower electrode of the capacitor. are connected.

Further, the insulating film 17 constituting the capacitor 16 is formed on the P-type diffusion region 13 serving as the base region, and is made of a silicon oxide film J8.

19 is the upper electrode (or base electrode) of the capacitor.

20 is an emitter electrode, 21 is a collector electrode, and 22 is an opening formed in the silicon oxide film 18 for forming the electrode.

Further, the wiring 23 is extended from the bonding pad 24,
An upper electrode 19 of the capacitor ft16 was formed, connected to the collector electrode 21 of the transistor 3, and then connected to a protected circuit (not shown) formed on the same semiconductor substrate 8.

Further, the wiring 25 connected the emitter electrode 20 and the resistor 15, and was further connected to the ground terminal 2.

A circuit diagram of the protection device constructed in this manner is shown in FIG. 2(C).

As shown in FIG. 2(C), when a positive electrostatic surge is applied to terminal 1, a sudden current flows instantly from the base of transistor 3 to the terminal through capacitor 4, and this capacitor N4 The forward operation of the transistor 3 causes the transistor 3 to conduct, thereby instantly absorbing the electrostatic surge. In this case, in FIGS. 2(a) and 2(b), the current flows through the wiring 23. It flows to capacitor 16 , P-type diffusion region 13 and N-type diffusion region 14 . At this time, high-speed operation can be realized by using the capacitor 4. If the electrostatic surge still remains, an avalanche collapse occurs between the collector and base of the transistor 3 in the subsequent period, and current flows through the resistor 5 due to this avalanche collapse. When a current flows through the resistor 5, a potential difference is generated between both ends of the resistor 5. This resistance 5
The remaining electrostatic surge is absorbed by the transistor 3 becoming conductive due to the potential difference between the two ends of the transistor, that is, the potential difference between the base and emitter of the transistor.

Note that in order to realize high-speed operation of the protection circuit, it is preferable to form a large capacitor. For example, as the insulating film 17 constituting the capacitor, the same material as the silicon oxide film 18 is used, and the thickness is 0.2 [ μm〕5 area 2500 Cμbo〕
Then, a capacitance of 0.5 (PF) can be formed. However, in order to obtain large capacity in a small area, insulation @1
It is dangerous to make 1 extremely thin because it may lead to breakdown of the insulating film due to electrostatic surge. In such a case, by using, for example, a silicon nitride film, which has a large dielectric constant and high breakdown voltage, as the insulating film, it is possible to obtain a capacitance approximately twice that of a silicon oxide film using the same geometrical method.

Furthermore, in order to improve the surge resistance of the protection circuit, it is necessary to prevent thermal breakdown due to local concentration of current in the element.

In this sense, it is preferable to flow the current planarly rather than linearly, and with a cross-sectional area rather than planarly. As is well known, in a lateral transistor, the current flows laterally near the surface of the semiconductor, whereas the protection device of the embodiment is a vertical transistor, as shown in the second box), in which the current flows horizontally near the surface of the semiconductor. basically extends from the collector region (N-type epitaxial region 10 and N-type buried diffusion region 9) to the base region (P-type diffusion region 13) to the emitter region (N-type diffusion region 1).
4) with a cross-sectional area in the vertical direction (arrow A), the surge resistance can be improved. Furthermore, the N-type buried diffusion region 9 with a high impurity concentration shown in FIG. 2(b) makes it easier for current to flow, thereby improving surge resistance.

Further, in the protection device of the embodiment, most of the electrostatic surge is absorbed by the forward operation of the transistor 3, so that it is difficult for current to flow between the collector and the base due to avalanche collapse. Therefore, surge resistance can be further improved.

What is important in the arrangement of the protection device is that the wiring A23 passes from the bonding pad 24 through the protection device and is then connected to the protected circuit (not shown), which allows high-speed operation of the protection circuit. In order to realize this, it is preferable that the upper electrode 19 of the capacitor 16 is connected next to the bonding pad 24.

In addition, although the above explanation described the case where a positive electrostatic surge was applied to the wiring 23 with respect to the wiring 25 connected to the grounding terminal 2, a negative electrostatic surge (with respect to the wiring 25 connected to the grounding terminal) was applied to the wiring 23. is applied, the N-type buried diffusion region 9 and the N-type epitaxial region 10 serving as the collector region, the P-type semiconductor substrate 8 and the P-type isolation shown in FIGS. 2(a) and 2(b) The PN junction formed by the diffusion region 11 becomes a diode X shown in FIG. 2(C), and by forward biasing this diode X, it is possible to absorb negative electrostatic surges.

FIG. 3(a) is a plan view showing a protection device according to a second embodiment of the present invention, and FIG. 3(b) is a plan view showing a protection device according to a second embodiment of the present invention.
A cross-sectional view along the line, FIG. 3(C), shows a circuit diagram of the protection device.

An N-type epitaxial region 26 is formed on a P-type semiconductor substrate 8 to serve as a base region and a lower electrode of a capacitor.
In the epitaxial region 26, a P-type diffusion region 27 serving as an emitter region was formed, and in a region 6i'i separating the N-type epitaxial region 26 into islands, a P-type isolation diffusion region 28 was formed.

Furthermore, the resistor 29 is formed of an N-type diffusion region, and is formed in the same process as the base region and the N-type evixial region 26, which becomes the lower electrode of the capacitor, and in order to simplify the layout design, these two regions are formed in succession. are doing.

Further, the collector region was formed by a P-type semiconductor substrate 8 and a P-type isolation diffusion region 28.

The insulating film 17 constituting the capacitor 16 was formed by forming a silicon oxide film 18.

19 is the upper electrode and heath electrode of the capacitor M16; 20
21 is a collector electrode, and 22 is an opening formed in the silicon oxide film 18 for forming the electrode.

Further, the wiring 30 is extended from the bonding pad 24,
After being connected to the resistor 29 and the emitter electrode 20 of the transistor 3', it was connected to a protected circuit (not shown) formed on the same semiconductor substrate 1.

Further, the wiring 32 formed the upper electrode 19 of the capacitor 16, connected to the collector electrode 21, and further connected to the ground terminal 2.

The circuit diagram of the protection device configured in this way is shown in Figure 3 (C), and the operation and design considerations of the protection device are as follows: It will be replaced.

Note that when a positive electrostatic surge is applied to the wiring 32 to the wiring A31, the current flows in the direction indicated by the arrow B in FIG. 3) with a cross-sectional area.

Furthermore, if a negative electrostatic surge is applied to the terminal 1 with respect to the wiring 32 connected to the ground terminal 2, the P-type semiconductor substrate 8
The PN junction formed by the P-type isolation diffusion region 28 and the N-type resistor 29 becomes the diode X shown in FIG. 3(C), and this diode X can absorb negative electrostatic surges. .

[Effects of the Invention] According to the protection circuit and protection device of the present invention, a capacitor is connected between the base and collector of the transistor, and a resistor is connected between the base and the terminal, thereby preventing static electricity that has a sudden and high voltage. High-speed operation is possible against electric surges,
In addition, a protection circuit with excellent surge resistance can be obtained.

Furthermore, by employing this protection circuit as a semiconductor integrated circuit, it is possible to obtain a protection device that protects the semiconductor integrated circuit from electrostatic surges with good operability. Furthermore, since the element layout design can be completed only around the terminals, eliminating the need for extra wiring, there is no need for design complexity, and the capacitance can be formed on the heat shield, while the resistor can be formed in the collector area. By doing so, the area occupied by the protection device on the semiconductor chip can be reduced, and its practical value is high.

[Brief explanation of the drawing]

FIG. 1(a) is a circuit diagram showing a protection circuit according to an embodiment of the present invention, and FIG. 1(b) is a relationship between the resistors constituting the protection circuit of the same embodiment and the operating voltage 6 of the protection circuit. Figure 1 showing
Figure (C) is a circuit diagram showing an example in which a PNP transistor is used as the protection circuit of the same embodiment, and Figure 2 (a) is a plan view showing the protection device of the first embodiment of the present invention. (middle) is a cross-sectional view taken along line A-A' shown in Figure 2(a), Figure 2fc)
is a circuit diagram of the same protection device, and FIG. 3(a) is a second circuit diagram of this invention.
FIG. 3(b) is a plan view showing the protection device of the embodiment of FIG.
A cross-sectional view taken along the line A-A' shown in Figure (a),
) is a circuit diagram of the protection device, Fig. 4 is a circuit diagram showing a conventional protection circuit, Fig. 5(a) is a circuit diagram showing the same protection circuit, and Fig. 5(1)) is a circuit diagram showing the voltage V of the transistor. FIG. 3 is a diagram showing the relationship with current r. 3.3'...Transistor, 4.16...Capacitance, 5
゜15.29...Resistance, 8...Semiconductor substrate, 10.
...N-type epitaxial region (collector region), 13.
...P type diffusion region (base region), 14...N type diffusion region (emitter region), 17...insulating film, 26...
N-type epitaxial region (Heas wi region), 27...
P-type diffusion region [Work Q'7 region], 28... P-type isolation diffusion region Fig. 2 (C) 27... P-type diffusion g region (emitter region) 3 Fig. (b) (C) Figure 9

Claims (3)

[Claims] (1) A protection circuit comprising a transistor, a capacitor connected between the base and collector of the transistor, and a resistor connected between the base and emitter of the transistor. (2) an N-type collector region that becomes a collector of a transistor formed on a P-type semiconductor substrate; a P-type base region that becomes a base of the transistor formed in this collector region; and a P-type base region that becomes a base of the transistor formed in the collector region. an N-type emitter region formed in the base region and serving as an emitter of the transistor; an insulating film serving as a capacitor formed on the base region; and the resistor region formed on the insulating film. a capacitive electrode, connecting the electrode and the collector region, and connecting the resistive region between the base region and the emitter region;
A protection device characterized in that the emitter region is connected to the semiconductor substrate. (3) an N-type base region that serves as a base of a transistor formed on a P-type semiconductor substrate; a collector region consisting of the semiconductor substrate and a P-type isolation diffusion region formed on the semiconductor substrate; and the base region. a P-type emitter region formed in the base region to serve as the emitter of the transistor; an N-type resistance region formed in the base region; an insulating film to serve as a capacitor formed on the base region; A protection device comprising: an electrode of the capacitor formed therein; the electrode of the capacitor is connected to the collector region; and the resistor region is connected between the base region and the emitter region.