JP2537161B2 - MOS semiconductor device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a MOS semiconductor device in which a gate electrode is arranged on an insulating film and the potential of an underlying Si substrate is controlled.

[Technical background of the invention and its problems]

In this type of MOS semiconductor device, the input impedance is extremely high and the thickness of the insulating film (oxide film) is large.
Since it is as thin as 200 to 1000Å, the dielectric strength is low at 10 to 100V, and the oxide film (gate oxide film) in the gate part is easily destroyed by the static electricity generated by friction. Therefore MOS
The type semiconductor device is always provided with a circuit (gate protection circuit) that protects the gate oxide film by utilizing the forward characteristics or breakdown characteristics of the PN junction, and prevents the gate oxide film from being destroyed. However, in MOS type semiconductor devices, the degree of integration has been increasing in recent years, the gate oxide film has become thinner and the diffusion layer has become shallower, and conventional gate protection circuits cannot sufficiently protect against static electricity. It is in an inconvenient situation such as being destroyed.

A typical conventional gate protection circuit is shown in FIG. The high voltage pulse input from the external terminal has its voltage clamped by the breakdown or forward characteristic in the resistance portion R formed of the diffusion layer, and the resistance causes the steep waveform to be smoothed. Then enter the PN junction of the MOS transistor T ₁ ,
Further, the breakdown voltage is lowered and the capability of the gate protection circuit is increased. This is because the low-potential-side power supply voltage V _SS is applied to the gate electrode of the MOS transistor T ₁ , so that the electric field on the surface of the Si substrate increases and the breakdown voltage decreases. The gate electrode of the input MOS transistor T ₂ to be protected is connected to the tip of the MOS transistor T ₁ .

FIG. 2 shows an actual integrated circuit pattern layout. The Al wiring is led out from the bonding pad 1, connected to the input diffusion layer 2 through the input contact hole CH, and connected to the diffusion layer of the MOS transistor T ₁ after passing through the relatively long resistance diffusion layer 3 and beyond. It is connected to the gate electrode of the input MOS transistor T ₂ . Resistance part R is usually 500
A resistance of Ω to several KΩ is used to give a time constant of 1 to 5 ns to reduce the peak voltage of a pulse having a sharp rising edge.

However, in such a conventional technology, under the present circumstances where the gate oxide film and the diffusion layer are becoming smaller in depth as the miniaturization progresses, the gate protection circuit itself is destroyed by a low voltage, and it is necessary to improve the situation. is there. Further, in the conventional technology, since the destruction mechanism is unknown, the gate protection circuit itself to which a surge is applied has been improved, but no attention has been paid to the relationship with the peripheral diffusion layer. For this reason, even if the gate protection circuit is improved, the effect is small, and it is much lower than the original electrostatic withstand voltage.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and can significantly improve the electrostatic withstand voltage of the gate protection circuit and prevent the gate protection circuit itself from being damaged by static electricity or the like.
It is intended to provide a MOS type semiconductor device.

[Outline of Invention]

The present invention is based on the destruction mechanism clarified by the present inventor, and by providing a means for keeping the same potential as the substrate between the diffusion layer forming the gate protection circuit and the diffusion layer around the diffusion layer, It prevents the interaction between layers and significantly improves the function of the gate protection circuit.

Example of Invention

Embodiments of the present invention will be described below with reference to the drawings. First, before the description of the present invention, a mechanism leading to destruction will be described. The mechanism described below was first clarified by the present inventor and is the basis of the present invention. Fig. 3 is a schematic diagram explaining the destruction mechanism.
A cross section near the gate protection circuit is shown. In the figure, 11 is a diffusion layer of the gate protection circuit, 12 is a diffusion layer near the gate protection circuit and not directly related to the gate protection circuit, and 13 is
A Si substrate is shown. Positive voltage (surge) on diffusion layer 11
Is applied, the diffusion layer 11 breaks down,
A large current flows toward the ground point of the substrate 13. At this time, the substrate resistance increases the substrate potential near the diffusion layer 11 of the surge applying terminal, and the diffusion layer 12 is biased in the forward direction when the peripheral diffusion layer 12 is close. If the diffusion layer 12 is biased to a fixed potential or the capacitance is large, minority carriers are injected from the diffusion layer 12 into the substrate 13, and a part of the minority carriers reach the depletion layer 14 of the surge applying terminal 11, Accelerated in the depletion layer.
Since the electric field strength is high in this depletion layer, the minority carriers that have obtained a large energy collide with the Si crystal to generate an electron-hole pair, resulting in carrier multiplication. For this reason the diffusion layer
The breakdown current of 11 is greatly increased, the junction surface of the diffusion layer 11 is thermally destroyed, and the electrostatic withstand voltage of the gate protection circuit is greatly reduced.

FIG. 4 shows the case where the near diffusion layer 12 is wired to the far diffusion layer 15. That is, when a surge is applied to the surge applying terminal 11, breakdown occurs, the substrate potential rises, and the nearby peripheral diffusion layer 12 is forward biased, as in the case of FIG. However, in this case, even if the capacity of the diffusion layer 12 is small, if the diffusion layer 15 is connected to a distant diffusion layer 15, minority carriers are supplied. That is, when the potential of the diffusion layer 12 rises, this potential is transmitted to the diffusion layer 15 which is far away. However, since the substrate potential in the vicinity of the diffusion layer 15 does not change, the diffusion layer 15 breaks down and supplies the minority carriers to the diffusion layer 12, and the minority carriers are injected from the diffusion layer 12 into the substrate 13. Reaches the depletion layer of the surge applying diffusion layer 11 to cause carrier multiplication, and the electrostatic withstand voltage of the gate protection circuit decreases.

When a surge is applied, the bias state is reversed,
That is, the mechanism is the same except that the relationship between the diffusion layers 11 and 12 is reversed, and the surge diffusion terminal 11 is not destroyed, but the peripheral diffusion layer 12 in the reverse bias state is destroyed.

In this way, there is only another diffusion layer near the surge applying terminal (usually, the diffusion layer is connected to a distant diffusion layer to form a circuit, is connected to a power supply, or has a large capacitance. Therefore, the electrostatic withstand voltage drops significantly below the original value. As an example, the electrostatic withstand voltage was 800 to 1000 V when there was no diffusion layer nearby,
Just placing a diffusion layer nearby will drop it to 200-3000V, destroying the reverse biased diffusion layer. In particular, the portion of the input diffusion layer 2 that is directly connected to the external terminal is easily destroyed because the high voltage pulse is applied as it is.

5 to 7 are explanatory views of the principle of the present invention.
Since this is an example of a case corresponding to the above-mentioned conventional one, the corresponding portions are denoted by the same reference numerals and the description thereof will be omitted, and the characteristic points will be described. In the example shown in FIG. 5, a P ⁺ diffusion layer 21 of the same conductivity type as the substrate is formed between the N ⁺ diffusion layer 11 of the gate protection circuit and the N ⁺ type peripheral diffusion layer 12 near the gate protection circuit. It is newly provided and is kept at the same potential as the substrate by Al wiring or the like on the upper surface of the substrate.

As a result, even if a surge is applied to the diffusion layer 11 and a breakdown current flows, the peripheral diffusion layer 1 passes through the P ⁺ diffusion layer 21.
Since the substrate potential near 2 is kept at a normal value (ground potential), the substrate potential near the diffusion layer 12 does not rise and the diffusion layer 12 is not biased in the forward direction. Therefore, even if the peripheral diffusion layer 12 is near the diffusion layer 11 of the gate protection circuit, the electrostatic breakdown voltage triggered by the minority carrier injection does not decrease, and the high electrostatic breakdown voltage inherent to the gate protection circuit can be realized. The electrostatic breakdown voltage can be greatly improved.
Further, in this case, since the impurity concentration of the P ⁺ diffusion layer 21 is high, the diffusion length of the minority carriers is shortened in this portion, and even if the minority carriers are injected into the Si substrate 13, the depletion layer of the surge applying diffusion layer 11 is reduced. Most minority carriers recombine before reaching 14, further increasing safety.

FIG. 6 shows an embodiment in which the P ⁺ diffusion layer cannot be used in a process, and FIG. 6 shows a case where a P ′ impurity layer 22 having a higher impurity concentration than the Si substrate 13 such as an ion implantation layer for adjusting the threshold voltage is used. Is an example of. In FIG. 7, means 23 for supplying a substrate potential such as Al wiring from the upper surface of the substrate 13 is directly connected to the Si substrate 13. In the case of FIG. 7, the resistance at the contact surface between the substrate and the Al wiring is rather large, and the reduction of the minority carrier diffusion length due to the P-type diffusion layer cannot be expected, so the effect is inferior to the case of FIG. It does not belong to the present invention.

8 to 10 show the example of FIG. 5 in a top view, only FIG. 9 shows an embodiment of the present invention. In the figure, reference numerals 12 ₁ and 12 ₂ denote peripheral diffusion layers unrelated to the gate protection circuit, and 21 21 ₁ and 21 ₂ denote P ⁺ diffusion layers between the diffusion layers 11 and 12. Figure 8 shows the Si substrate 13 around the gate protection circuit.
When surrounded by same conductivity type P ⁺ diffusion layer 21 and, FIG. 9 shows a case that surrounds the peripheral diffusion layer 12 _1, 12 ₂ P ⁺ diffusion layer 21 _1, 21 ₂ reversed. Figure 10 shows the gate protection circuit and peripheral diffusion layer 12
_A P ⁺ diffusion layer 21 is provided in a part between ₁ and 12 ₂ .

In the case of FIG. 9, when a negative surge is applied to the N ⁺ diffusion layer 2, the diffusion layer 2 is forward biased and a large current flows, so that the substrate potential around the diffusion layer 12 ₁ becomes large. bias in the negative direction, the diffusion layer 12 ₁ is reverse biased, a depletion layer is generated around the junction of the diffusion layer 12 _1, diffusion layer 2, a substrate, and trigger the minority carrier flow diffusion layer 12 _1, between Due to the carrier multiplication, the diffusion layer 12 ₁ is easily broken. However, the diffusion layer 12 ₁ is the diffusion layer 1 to which the substrate potential is applied.
Because it is surrounded by the 2 _1, the diffusion layer 12 by the negative surge
Fluctuations in the substrate potential around ₁ are greatly reduced, so that the diffusion layer 12 ₁ is less likely to be destroyed. The safety, most of the minority carriers, by recombination with the diffusion layer 12 ₁ is further enhanced. Further, since the diffusion layer 21 ₁ is provided so as to surround the diffusion layer 12 ₁ , it is possible to prevent the influence of the potential and minority carriers from the circumferential direction around the diffusion layer 12 ₁ as a whole. is there. The same can be said for the diffusion layers 12 ₂ and 21 ₂ . This is a case where the diffusion layers 12 ₁ and 12 ₂ are surrounded by P ⁺ diffusion layers 21 ₁ and 21 ₂ . Figure 10 are those provided with P ⁺ diffusion layer 21 in a part between the gate protection circuit and the peripheral diffusion layer 12 _1, 12 _2, P between the surrounding diffusion layer 12 ₁ close to the gate protection circuit ⁺ A diffusion layer 21 is provided. In this case, the P ⁺ diffusion layer is provided in a place where the distance between the gate protection circuit and the peripheral diffusion layer is small, but the surge voltage remains unchanged in the input diffusion layer 2 (the diffusion layer around the contact hole CH) of the gate protection circuit. Since it is applied, it is in a particularly severe state, and it is preferable to provide the P ⁺ diffusion layer 21 between the input diffusion layer and the peripheral diffusion layer. This also applies to the case of FIGS. 8 and 9, and the P ⁺ diffusion layer is provided only between the input diffusion layer 2 and the peripheral diffusion layer 12 ₁ .
That is, in the case of FIG. 8, the input diffusion layer 2 of the gate protection circuit
9 (the P ⁺ diffusion layer 21 is not provided all around the diffusion layer of the gate protection circuit and cut in the middle to cover only the vicinity of the input diffusion layer 2; not shown). In the case, a peripheral diffusion layer close to the input diffusion layer 2.

〔The invention's effect〕

As described above, according to the present invention, an impurity layer having the same conductivity type as the substrate is provided at least at a part between the diffusion layer and the peripheral diffusion layer of the gate protection circuit to which the surge voltage can be applied, and the substrate is provided from the upper surface of the substrate. By supplying the potential or directly supplying the substrate potential to the substrate, the electrostatic withstand voltage of the gate protection circuit can be significantly improved, and the MOS type semiconductor device can be prevented from being damaged by static electricity or the like. .

[Brief description of drawings]

FIG. 1 is a gate protection circuit diagram, FIG. 2 is a pattern plan view of the same circuit, FIGS. 3 and 4 are sectional views for explaining the destruction mechanism, and FIGS. 5 to 7 are explanations of the principle of the present invention. FIG. 8, FIG. 10 and FIG. 10 are pattern plan views before improvement leading to the present invention,
FIG. 9 is a pattern plan view of an embodiment of the present invention. 11 …… Diffusion layer of gate protection circuit, 12 …… Peripheral diffusion layer, 13
...... Semiconductor substrate, 21 …… P ⁺ diffusion layer, 23 …… Substrate potential applying means.

Claims (2)

(57) [Claims] 1. A first-conductivity-type semiconductor substrate is provided with a gate protection circuit for a MOS element provided on the substrate, and the substrate is provided on the substrate in order to prevent fluctuation of the substrate potential due to surge to the gate protection circuit. And a first conductivity type diffusion layer is provided so as to surround the second conductivity type diffusion layer of the circuit around the gate protection circuit away from the second conductivity type diffusion layer of the gate protection circuit, and to the diffusion layer. Is provided with means for applying a substrate potential, and the gate protection circuit is a circuit for protecting the gate of the MOS element against a surge entering the signal input terminal from the outside of the substrate. MOS type semiconductor device. 2. The MOS type semiconductor device according to claim 1, wherein the second conductivity type diffusion layer of the gate protection circuit is an input diffusion layer of the gate protection circuit.