JP2588664B2 - Active matrix liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device, and more particularly to a large capacity TFT active matrix liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, many researches and developments have been made on an active matrix liquid crystal display device using a thin film transistor element (hereinafter abbreviated as TFT) as a switching element. An active matrix liquid crystal display device provided with a TFT has a liquid crystal material sandwiched between a first substrate and a second substrate opposed thereto. The first substrate has a plurality of scanning electrodes and a plurality of signal electrodes provided in a matrix on a glass substrate. Each pixel separated by the scanning electrodes and the signal electrodes has a TFT element and a display electrode. Are arranged respectively. The TFT element is connected to the scanning electrode, the signal electrode, and the display electrode, respectively. Further, a counter electrode is formed on the second substrate. A promising TFT is a p-Si TFT using polycrystalline silicon (hereinafter abbreviated as p-Si). p-Si
TFTs have a higher charge mobility of about 30 cm ² / V than amorphous Si thin film transistors, and thus are useful for realizing a large-area, high-resolution liquid crystal display. In addition, since the charge mobility is high, a peripheral circuit for driving the liquid crystal display panel can be formed on the same substrate using TFTs, which is effective in reducing the size and cost of the display.

A method of manufacturing such a p-Si TFT is reported in the Proceedings of 1988 International Display Research Conference, pp. 215-219. In this method, in order to form a p-Si thin film as an active layer, first, a film is formed at a substrate temperature of 500 ° C. using a low pressure CVD method,
By firing at 600 ° C. in a nitrogen atmosphere, a Si thin film with improved crystallinity is formed. Then, on the patterned p-Si layer, a gate insulating film, a gate Si layer,
An SiO ₂ layer for interlayer insulation, a scanning electrode, a signal electrode, a display electrode, and the like are sequentially formed. These formations are performed by atmospheric pressure CVD.
It can be formed by repeatedly performing film formation and patterning by a method, a low pressure CVD method, or the like. In this way, a high mobility p-Si TFT is manufactured, and a TFT-
An LCD can be realized.

As a method for manufacturing a large-sized display, a low-cost apparatus can be manufactured on a substrate having a diagonal size of 40 inches or more by applying printing technology to the Proceedings of 1991 International Display Research Conference, pp. 227-230. It is disclosed that a resist pattern can be formed with high productivity. Moreover, the thin line width of the pattern formed by this method is at least 3 μm. Attempts to fabricate a shift register circuit or an 8 × 8 matrix liquid crystal display device by combining this patterning technique with the above p-Si TFT manufacturing process. Has been made.

[0005]

However, the above-mentioned p
-The maximum temperature during the Si TFT manufacturing process is 60
The process temperature of about 0 ° C. using a glass substrate is high. It is known that the size of the glass substrate after firing at a high temperature changes from that before firing even when the temperature is lowered.With this change, the pattern size on the glass substrate is deformed, and the pixel size is reduced. There is a problem that the arrangement pitch changes. As a result, when the layers after the gate Si layer are superimposed on the patterned p-Si layer, the positions of the layers are shifted, especially on a large-area substrate, the shift becomes more remarkable. was there. Also, in a method of performing patterning by applying a printing technique,
Although a thin line of about 3 μm can be formed, the printing technique is different from the photomask technique, and the interlayer alignment technique for superimposing a large number of patterns has been a particular problem. In other words, if the superimposition is greatly deviated and, for example, any one of the gate electrode and the scanning electrode of the TFT, the drain electrode of the TFT and the signal electrode, or the source electrode of the TFT and the display electrode does not overlap, the pixel operates as a pixel due to poor connection. Can not
There was a risk of becoming a defect.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and when a large-area liquid crystal display device is constructed using p-Si TFTs, sufficient display characteristics can be obtained even if the interlayer alignment accuracy is low. It is an object of the present invention to provide an active matrix liquid crystal display device capable of performing the following.

[0007]

According to a first aspect of the present invention, there is provided an active matrix liquid crystal display device having a plurality of scanning electrodes and a plurality of signal electrodes arranged in a matrix on a transparent insulating substrate. And at least p-S is applied to each pixel separated by these scanning electrodes and signal electrodes.
TFT comprising an i-layer and a gate electrode orthogonal thereto
And a display electrode, the p-Si layer on one end and the signal electrode are connected with the gate electrode interposed therebetween, and the p-Si
A second substrate provided with a counter electrode on an insulating substrate is disposed so as to face a first substrate to which a layer and a display electrode are connected and a gate electrode and a scanning electrode are connected. An active matrix liquid crystal display device in which a liquid crystal material is sandwiched between the scanning electrodes, wherein the p-Si layer has a shape of a band parallel to the scanning electrodes, and the length of the scanning electrode in the scanning electrode direction forms one side of one pixel. greater than 5/7 of the length of the electrode
And can connect the p-Si layer and the signal electrode.
The size of the non-insulated part forms one side of one pixel in the matrix direction
The length of the scanning electrode to be formed is 2/7 or more . An active matrix liquid crystal display device according to claim 2 , wherein a plurality of scanning electrodes are provided on a transparent insulating substrate.
And a plurality of signal electrodes are arranged in a matrix direction.
And each pixel separated by the signal electrode, at least p
TF comprising a Si layer and a gate electrode orthogonal thereto
T, a display electrode is provided, and one end side of the gate electrode is interposed therebetween.
P-Si layer and the signal electrode are connected, and p-S
The i-layer and the display electrode are connected, and the gate electrode and the scanning electrode are connected.
For the first substrate to which the poles are connected, the pair on the insulating substrate
A second substrate provided with a counter electrode is disposed facing the second substrate.
Active matrix with liquid crystal material sandwiched between substrates
A liquid crystal display device, wherein the shape of the p-Si layer is
It is a strip parallel to the scanning electrode, and its length in the scanning electrode direction is one.
Greater than 5/7 of the length of the scan electrode forming one side of the pixel
And connect the gate electrode and the scan electrode.
The size of the non-insulated part forms one side of one pixel in the matrix direction
The length of the scanning electrode to be formed is 2/7 or more . An active matrix liquid crystal display device according to a third aspect is the device according to the second aspect, wherein the p-Si
The size of the non-insulating portion that can connect the layer and the signal electrode is two times the length of the scanning electrode forming one side of one pixel in the matrix direction.
/ 7 or more. An active matrix liquid crystal display device according to a fourth aspect of the present invention is the active matrix liquid crystal display device according to the first to third aspects, wherein the p-Si layer and the gate electrode
The length of the gate electrode outside the intersection with the pole is one
The length is set to be 1/7 or more of the length of the scanning electrode forming one side of the pixel . According to a fifth aspect of the present invention, in the active matrix liquid crystal display device according to the first to fourth aspects, the size of a non-insulating portion capable of connecting the p-Si layer and the display electrode is one side of one pixel in the matrix direction. The length of the scanning electrode to be formed is 2/7 or more.

[0008]

According to the active matrix liquid crystal display device of the present invention, the p-Si layer has a band shape parallel to the scanning electrode.
The length in the scanning electrode direction is larger than 5/7 of the length of the scanning electrode forming one side of one pixel. Therefore, in the manufacturing process of the liquid crystal display device, it is a pattern shift due to the deformation of the substrate or a shift that occurs when the pattern on the substrate and the pattern on the mask are overlapped, and forms one side of one pixel in the matrix direction. 1/7 of scanning electrode length
With respect to a dimensional change due to a smaller displacement, it is possible to secure the shape of the TFT or the connection between the TFT and each of the scanning electrode, the signal electrode, and the display electrode. This can prevent pixel defects due to poor connection.
By setting the length of the gate electrode outside the intersection of the p-Si layer and the gate electrode to be 1/7 or more of the length of the scanning electrode forming one side of one pixel, For the same dimensional change, the intersection between the p-Si layer of the TFT and the gate electrode can be ensured. Also, p-Si
The size of the non-insulating portion that can connect the layer and the signal electrode is two times the length of the scanning electrode forming one side of one pixel in the matrix direction.
By setting / 7 or more, the connection between the p-Si layer and the signal electrode can be secured against the same dimensional change as described above. In addition, by setting the size of the non-insulating portion that can connect the gate electrode and the scanning electrode to 2/7 or more of the length of the scanning electrode forming one side of one pixel in the matrix direction, the same dimensional change as described above can be obtained. In contrast, the connection between the gate electrode and the scanning electrode can be secured. Furthermore, p-S
By setting the size of the non-insulating portion that can connect the i-layer and the display electrode to ２ or more of the length of the scanning electrode forming one side of one pixel in the matrix direction, the same dimensional change as described above can be obtained. Thus, connection between the p-Si layer and the display electrode can be secured.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an active matrix liquid crystal display device according to the present invention will be described in detail with reference to the drawings. FIG. 1 shows a first substrate of a liquid crystal display device according to an embodiment of the present invention, and is a schematic plan view showing a portion corresponding to one pixel.
In the figure, reference numeral 1 denotes a transparent insulating substrate, 2 denotes a p-Si layer, 3 denotes a gate electrode, 5 denotes a scanning electrode, 6 denotes a signal electrode, and 7 denotes a display electrode. In the first substrate of this example, a plurality of scanning electrodes 5 and a plurality of signal electrodes 6 are arranged on a transparent insulating substrate 1 in a matrix direction (in the present embodiment, referred to as xy directions). Each pixel separated by the signal electrode 6 is provided with a p-Si layer 2 as a switch element and a T
The FT and the display electrode 7 are provided. In this pixel, the direction of the scanning electrode 5 is defined as the x direction, the direction of the signal electrode 6 is defined as the y direction, and the length of the scanning electrode 5 forming one side of one pixel is represented as Px.

The p-Si layer 2 is formed on the insulating substrate 1 by p-Si.
The layer is formed in a strip shape parallel to the x direction. The length in the x direction (indicated by L in the figure) is 5/5 of Px.
7 are formed. The width in the Y direction can be set arbitrarily. Further, one end of the p-Si layer 2 is located outside the center line of the signal electrode 6, and the outer portion 2
The length a in the x direction is formed so as to be approximately 1/7 of Px. A gate electrode 3 composed of a gate insulating film 3a and a gate Si layer 3b is formed on a central portion of the p-Si layer 2 so as to be orthogonal to the p-Si layer 2. The gate electrode 3 has a length in the Y direction Px
Is formed larger than 4/7, and one end is formed of Si.
The gate electrode is formed outside the intersection 3c with the layer 2 so that the length 3d of the gate electrode outside the intersection 3c is 1/7 or more of Px. The other end of the gate electrode 3 is located outside the center line of the scanning electrode 5, and the length of the outer portion 3e is 1/7 or more of Px.
On both sides of the p-Si layer 2 sandwiching the gate electrode 3, impurities such as phosphorus ions are doped, and impurity-doped layers 11a and 12a serving as a drain and a source are formed, respectively, to constitute a TFT. I have.

A first interlayer insulating film 4 is formed on the TFT formed on such a transparent insulating substrate 1. The first interlayer insulating film 4 has a gate electrode 3 and an impurity serving as a drain. The gate electrode connection opening 1 is formed on the doped layer 11a and on the impurity doped layer 12a serving as a source.
0, a drain electrode connection opening 11 and a source electrode connection opening 12 are opened. That is, these openings are non-insulating portions that can connect the electrodes formed in the openings. The gate electrode connection opening 10, the drain electrode connection opening 11, and the source electrode connection opening 12 are all in the x direction and the y direction.
Each width in the direction is formed to be at least 2/7 of Px. Also, these openings are preferably formed in a square shape. The gate electrode connection opening 10 is arranged so that the gate electrode 3 and the scan electrode 5 are connected at substantially the center thereof, and the drain electrode connection opening 11 is provided.
Are arranged such that the p-Si layer 2 and the signal electrode 6 are connected substantially at the center. Further, the source electrode connection opening 12 is formed at least P from the other end of the p-Si layer 2.
An inner portion 2b having a length of 1/7 of x is arranged so as to be located in the opening. Also, the opening 12
A display electrode 7 is formed at least at the end on the gate electrode side, where the p-Si layer 2 and the display electrode 7 are connected. Also, at the intersection of the scanning electrode 5 and the signal electrode 6, a second interlayer insulating film 13 is formed between these electrodes, thereby insulating both electrodes.

[0012] Such a first substrate can be manufactured, for example, as follows. 2 and 3 show the manufacturing process of this substrate in the order of steps.
3A to 3F are schematic plan views, and FIGS. 3A to 3F are cross-sectional views taken along line AA in FIG.

First, amorphous silicon is deposited on a transparent insulating substrate 1 such as a glass substrate at a substrate temperature of 550.degree.
A film is formed and subsequently fired at 600 ° C. for 5 hours or more to crystallize it. After a resist is applied on the obtained p-Si layer 2, exposure and resist development are performed using a mask to form a resist pattern, and the strip-shaped p-Si layer 2 is formed by dry etching. [FIG. 2 (a) and FIG. 3 (a)] Next, an SiO ₂ film is formed at normal pressure by CVD as the gate insulating film 3a.
The gate Si layer 3b is formed thereon by a low pressure CVD method. Subsequently, the gate insulating film 3a
The gate electrode 3 is formed by patterning the gate Si layer 3b by a photo and etch process. [Figure 2
(B) and FIG. 3 (b)] Next, phosphorus ions (P) are implanted by an ion implantation method, and heat treatment is performed to form phosphorus-doped layers 11a and 12a of a drain and a source, and the gate electrode 3 is formed. Lower the resistance. [FIG. 3 (c)]

Thereafter, a phosphide glass film is formed as the first interlayer insulating film 4, and is patterned by a photo-etching step to form a gate electrode connection opening 10, a drain electrode connection opening 11, and a source electrode connection. An opening 12 is formed. [FIG. 2 (c) and FIG. 3 (d)] Next, after forming a conductive material thin film such as Al, Ta or ITO by using a sputtering method or an electron beam evaporation method, patterning is performed to form the scanning electrode 5. To form [Figure 2
(D) Next, a second interlayer insulating film 13 is formed on the scanning electrode 5 at the intersection with the signal electrode 6 to be formed later, as S
TiO ₂ , glass arsenide, etc. are prepared by sputtering or CVD,
Or apply by SOG (spin on glass) method,
This is fired. At this time, when the SOG method is used, a thin film can be formed only in a necessary portion in advance by using a printing method at the time of application, so that patterning by etching is not required, and the process can be simplified.

Next, after forming a thin film of a conductive material such as Al, Ta, or ITO by using a sputtering method or an electron beam evaporation method, the signal electrode 6 is formed by patterning. [FIG. 2 (e) and FIG. 3 (e)] Thereafter, a transparent conductive thin film such as ITO is formed, and the display electrode 7 is formed by patterning. [FIG. 2 (f) and FIG. 3 (f)] Thus, the first substrate is obtained. The first substrate and the second substrate provided with a counter electrode on another insulating substrate are arranged to face each other, and a liquid crystal is sandwiched between these substrates to constitute an active matrix liquid crystal display device. it can. In the above process, in forming a resist pattern in patterning, in addition to a method of forming a combination of a photomask and a photoresist,
A resist pattern can be directly formed on a substrate by a printing method, and the printing method is advantageous in productivity of a patterning step.

The first substrate in this embodiment can be used even if the substrate is deformed during the manufacturing process or the pattern on the substrate is displaced from the pattern on the mask during patterning. TFT shape or TFT
And the scanning electrode 5, the signal electrode 6, and the display electrode 7 can be connected to each other. That is, the intersection between the p-Si layer 2 and the gate electrode 3 constituting the TFT is ensured in both the x and y directions with respect to a deviation within a range indicated by Mgd in FIG. The connection between the p-Si layer 2 and the signal electrode 6 is as follows.
It is ensured against the displacement in the drain electrode connection opening 11. That is, in the x-direction and the y-direction, a deviation within a range indicated by WSIO _x and WSIO _Y in FIG. 1 is ensured, respectively. Similarly, the connection between the gate electrode 3 and the scanning electrode 5 is ensured against the displacement in the gate electrode connection opening 10, and the connection between the p-Si layer 2 and the display electrode 7 is the source electrode connection opening 12 Is ensured against deviations within. And p
-Si layer 2 is formed of another p-Si layer provided in an adjacent pixel.
Although it is necessary to ensure the separation from the layer 2, the range of the shift of the p-Si layer 2 in which the separation is ensured is within the range indicated by Ms in FIG. 1 for each p-Si layer. Therefore,
When the length L of the p-Si layer 2 in the x direction is set to 5/7 of Px, since Ms = 1 / 2WSIO _x , L is set to 5 of Px.
When it is larger than / 7, the allowable range of each of the above-mentioned shifts can be maximized, and a connection failure can be prevented for a shift smaller than 1/7 of Px at each connection portion or intersection. Since the p-Si layer 2 of each pixel is formed at the same time by the same patterning step, the degree to which the p-Si layer 2 of the adjacent pixel approaches is smaller than the shift caused by another patterning step. It is small. Therefore, it is possible to Ms <1 / 2WSIO _x. In this case, L may be larger than 5/7 and smaller than Px.

[0017]

As described above, in the active matrix liquid crystal display device of the present invention, a plurality of scanning electrodes and a plurality of signal electrodes are arranged in a matrix on a transparent insulating substrate, and are separated by the scanning electrodes and the signal electrodes. For each pixel obtained, p
TF comprising a Si layer and a gate electrode orthogonal thereto
T, a display electrode is provided, a p-Si layer on one end is connected to the signal electrode with the gate electrode interposed, and a p-S
A second substrate provided with an opposing electrode on an insulating substrate is disposed so as to face a first substrate to which an i-layer and a display electrode are connected and a gate electrode and a scanning electrode are connected. An active matrix liquid crystal display device having a liquid crystal material interposed therebetween, wherein the shape of the p-Si layer is a band parallel to the scanning electrode, and the length in the scanning electrode direction forms one side of one pixel. greater than 5/7 of the length of the scanning electrodes
And can connect the p-Si layer and the signal electrode.
The size of the non-insulated part forms one side of one pixel in the matrix direction
The length of the scanning electrode to be formed is 2/7 or more.
It is.

Therefore, in the manufacturing process of the liquid crystal display device, it is a pattern shift due to the deformation of the substrate or a shift that occurs when the pattern on the substrate and the pattern on the mask are overlapped. The shape of the TFT or the connection between the TFT and each of the scanning electrode, the signal electrode and the display electrode , and the p-Si
The connection between the layer and the signal electrode can be ensured. Therefore, in the pixel portion of the active matrix liquid crystal display device, a highly reliable wiring to the display electrode and good display characteristics such as a high contrast ratio can be simultaneously realized.

The active matrix liquid crystal of the present invention
According to the display device, the gate electrode and the scanning electrode are connected.
The size of the non-insulated part is one side of one pixel in the matrix direction.
By making the length of the scanning electrode to be formed at least 2/7 or more,
And scan the gate electrode against the same dimensional change as above.
Connection with the electrode can be secured. Also, p-Si
The gate electrode outside the intersection of the layer and the gate electrode
Is the length of the scanning electrode forming one side of one pixel.
/ 7 or more, the same dimensional change as above
In contrast, check the intersection between the p-Si layer of the TFT and the gate electrode.
Connection between the p-Si layer and the display electrode
The size of the non-insulated part is one side of one pixel in the matrix direction.
By making the length of the scanning electrode to be formed at least 2/7 or more,
Therefore, for the same dimensional change as above, it is indicated as p-Si layer.
Connection with the electrode can be secured.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a first substrate of an embodiment of a liquid crystal display device of the present invention.

FIG. 2 is a schematic plan view showing steps of manufacturing the first substrate of FIG. 1 in the order of steps.

FIG. 3 is a schematic cross-sectional view showing a step of manufacturing the first substrate in FIG. 1 in the order of steps.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transparent insulating substrate 2 Polycrystalline silicon layer 3 Gate electrode 5 Scan electrode 6 Signal electrode 7 Display electrode 10 Gate electrode connection opening (non-insulated part) 11 Drain electrode connection opening (non-insulated part) 12 Source electrode connection opening ( Non-insulated part)

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-162771 (JP, A) JP-A-2-247619 (JP, A) JP-A-2-242229 (JP, A) JP-A-2- 245739 (JP, A) JP-A 1-243033 (JP, A) JP-A 64-68969 (JP, A) JP-A 64-51663 (JP, A)

Claims (5)

(57) [Claims] A plurality of scanning electrodes and a plurality of signal electrodes are arranged on a transparent insulating substrate in a matrix direction, and each pixel divided by the scanning electrodes and the signal electrodes is provided with at least a polycrystalline silicon layer and an orthogonal thereto. A thin-film transistor element comprising a gate electrode, and a display electrode are provided. The polycrystalline silicon layer on one end is connected to the signal electrode with the gate electrode interposed therebetween, and the polycrystalline silicon layer on the other end is connected to the display electrode. And a second substrate in which a counter electrode is provided on an insulating substrate with respect to the first substrate in which the gate electrode and the scanning electrode are connected.
An active matrix liquid crystal display device in which a liquid crystal material is sandwiched between these substrates, wherein the polycrystalline silicon layer has a belt-like shape parallel to the scanning electrodes and has a length in the scanning electrode direction. Is greater than 5/7 of the length of the scanning electrode forming one side of one pixel , and
Non-insulating part that can connect the crystal silicon layer and the signal electrode
Scan in which the size of one pixel forms one side in the matrix direction
An active matrix liquid crystal display device , wherein the length of the electrode is 2/7 or more . 2. A method according to claim 1, wherein a plurality of scanning electrodes are provided on a transparent insulating substrate.
The number of signal electrodes is arranged in the matrix direction,
At least polycrystalline
A thin layer consisting of a silicon layer and an orthogonal gate electrode
A film transistor element and a display electrode are provided, and a gate electrode is provided.
The polycrystalline silicon layer on one end and the signal electrode
Connected to the polycrystalline silicon layer on the other end and the display electrode
And a first electrode in which the gate electrode and the scanning electrode are connected.
A second substrate in which a counter electrode is provided on an insulating substrate;
Substrates are opposed to each other, and a liquid crystal material is sandwiched between these substrates.
Active matrix liquid crystal display device, The shape of the polycrystalline silicon layer is parallel to the scan electrode.
Band-shaped, the length in the scanning electrode direction forms one side of one pixel
Greater than 5/7 of the length of the scanning electrode to be
Size of the non-insulating part that can connect the scanning electrode and the scanning electrode
Of the scanning electrode that forms one side of one pixel in the matrix direction
An active mask characterized by being at least 2/7 of the length
Trix liquid crystal display device. 3. The size of a non-insulating portion capable of connecting the polycrystalline silicon layer and the signal electrode is at least 2/7 of the length of a scanning electrode forming one side of one pixel in the matrix direction. 3. The active matrix liquid crystal display device according to claim 2, wherein: 4. The polycrystalline silicon layer and the gate electrode
The length of the gate electrode outside the intersection with the
It is 1/7 or more of the length of the scanning electrode forming one side of the element
The active matrix liquid crystal display device according to claim 1, wherein: 5. The size of a non-insulating portion that can connect the polycrystalline silicon layer and the display electrode is at least 2/7 of the length of a scanning electrode forming one side of one pixel in the matrix direction. The active matrix liquid crystal display device according to claim 1, wherein: