JP2586455B2 - Solid-state imaging device - Google Patents
Solid-state imaging deviceInfo
- Publication number
- JP2586455B2 JP2586455B2 JP61159281A JP15928186A JP2586455B2 JP 2586455 B2 JP2586455 B2 JP 2586455B2 JP 61159281 A JP61159281 A JP 61159281A JP 15928186 A JP15928186 A JP 15928186A JP 2586455 B2 JP2586455 B2 JP 2586455B2
- Authority
- JP
- Japan
- Prior art keywords
- transfer
- imaging device
- state imaging
- channel
- light receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000003384 imaging method Methods 0.000 title claims description 15
- 230000005684 electric field Effects 0.000 claims description 16
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、インターライン型CCD固体撮像装置に関す
る。Description: TECHNICAL FIELD The present invention relates to an interline CCD solid-state imaging device.
本発明は、水平及び垂直方向に配列された複数の受光
部と垂直転送レジスタとを有するインターライン型CCD
固体撮像装置において、垂直転送レジスタは幅４μｍ以
下のチャンネル領域上に絶縁膜を介して設けられた複数
の転送電極とからなり、１つの受光部に一対の転送電極
が対応し、複数の転送電極に４層のクロック信号を与え
て、チャンネル領域に注入された電荷を順次転送するよ
うになされ、転送電極内でチャンネル幅を１段または複
数段に分けて転送方向に順次広げて転送方向の電界を生
じさせることによて、電荷の転送効率を改善するように
したものである。The present invention relates to an interline CCD having a plurality of light receiving units and a vertical transfer register arranged in the horizontal and vertical directions.
In the solid-state imaging device, the vertical transfer register includes a plurality of transfer electrodes provided on a channel region having a width of 4 μm or less via an insulating film, and a pair of transfer electrodes corresponds to one light receiving unit. Are supplied with clock signals of four layers to sequentially transfer the charges injected into the channel region. The channel width is divided into one or more stages in the transfer electrode, and the channel width is sequentially increased in the transfer direction to sequentially transfer the electric field in the transfer direction. Is caused to improve the charge transfer efficiency.
例えばインターライン型CCD固体撮像装置は、第３図
の原理的構成図に示すように、水平及び垂直方向に所定
ピッチで配列した画素となる複数の受光部（１）と、各
列の受光部（１）の一側に設けた垂直方向に延びるCCD
構造の垂直転送レジスタ（２）と、各垂直転送レジスタ
（２）の一端に設けたCCD構造の水平転送レジスタ
（３）とを有し、各受光部（１）にその受光量に応じて
生じた信号電荷を夫々対応する垂直転送レジスタ（２）
に転送し、これら各垂直転送レジスタ（２）の信号電荷
を水平転送レジスタ（３）へと転送し、１水平ライン毎
の信号電荷を読み出すように構成される。For example, as shown in the principle configuration diagram of FIG. 3, an interline type CCD solid-state imaging device includes a plurality of light receiving units (1) which are pixels arranged at a predetermined pitch in the horizontal and vertical directions, and a light receiving unit in each column. (1) Vertically extending CCD on one side
It has a vertical transfer register (2) having a structure, and a horizontal transfer register (3) having a CCD structure provided at one end of each vertical transfer register (2). Vertical transfer register (2) corresponding to each signal charge
, And transfers the signal charges of each of the vertical transfer registers (2) to the horizontal transfer register (3) to read out the signal charges for each horizontal line.
垂直転送レジスタ（２）は第４図に示すようにチャン
ネル領域（４）を形成した半導体基体上に絶縁膜を介し
て複数の転送電極（５）を形成して構成され、垂直方向
に同一幅Ｗで形成される。（６）はチャンネルストップ
領域、（７）は読み出しゲート部である。As shown in FIG. 4, the vertical transfer register (2) is formed by forming a plurality of transfer electrodes (5) via an insulating film on a semiconductor substrate on which a channel region (4) is formed, and has the same width in the vertical direction. W is formed. (6) is a channel stop area, and (7) is a read gate section.
上述の固体撮像装置においては、高解像度化に伴っ
て、単位画素寸法が小さくなり、従って垂直転送レジス
タ（２）の幅Ｗも狭く（例えば４μｍ以下）なる。この
ため狭チャンネル効果により、垂直転送レジスタ（２）
における電荷転送時のフリンジング電界が弱まり、転送
効率の劣化が生じるものであった。In the solid-state imaging device described above, the unit pixel size is reduced as the resolution is increased, and the width W of the vertical transfer register (2) is also reduced (for example, 4 μm or less). Therefore, due to the narrow channel effect, the vertical transfer register (2)
In this case, the fringing electric field at the time of charge transfer was weakened, and the transfer efficiency deteriorated.
通常、１つの電送電極内の転送方向の電界はその中央
部で最も弱くなる。その理由は、隣接する転送電極の近
傍では、これら隣接する転送電極からのフリンジング電
界を受けて転送方向の電界が十分得られるが、隣接する
転送電極から最も離れた電極中央部ではこのフリンジン
グ電界が弱くなるためである。これはチャンネル幅４μ
ｍ以下の装置において顕著となる。Usually, the electric field in the transfer direction within one transmission electrode is weakest at the center. The reason is that, in the vicinity of adjacent transfer electrodes, a fringing electric field from these adjacent transfer electrodes is received and a sufficient electric field in the transfer direction is obtained, but in the center of the electrode farthest from the adjacent transfer electrode, this fringing occurs. This is because the electric field becomes weak. This is channel width 4μ
m or less.
他方、固体撮像素子は小型化、高画素数化の要求が大
きく、感度、転送効率等の性能を維持または向上させつ
つチップサイズを縮小することが重要な課題となってい
る。On the other hand, there is a great demand for a solid-state imaging device to have a smaller size and a higher number of pixels, and reducing the chip size while maintaining or improving performance such as sensitivity and transfer efficiency has become an important issue.
本発明は、上述の点に鑑み、狭いチャンネル幅とした
場合においても、チャンネルサイズを抑制しつつ、電荷
転送効率を改善できるようにした固体撮像装置を提供す
るものである。In view of the above, the present invention provides a solid-state imaging device capable of improving the charge transfer efficiency while suppressing the channel size even when the channel width is narrow.
本発明は、水平及び垂直方向に配列された複数の受光
部（１）と、受光部（１）の電荷を垂直方向に転送する
ための垂直転送レジスタ（２）とを有するインターライ
ン型CCD固体撮像素子において、垂直転送レジスタ
（２）は幅４μｍ以下のチャンネル領域（４）とチャン
ネル領域（４）上に絶縁膜を介して設けられた複数の転
送電極（５）とからなり、１つの受光部（１）に一対の
転送電極（５）が対応してなり、複数の転送電極（５）
に４相のクロック信号を与えてチャンネル領域（４）に
注入された電荷を順次転送するようになされ、各転送電
極（５）内（すなわち各転送部（８）内）で、転送電極
（５）中央部の電界を強めるようチャンネル幅を１段ま
たは複数段に分けて転送方向に順次広げて構成する。The present invention relates to an interline CCD solid-state having a plurality of light receiving units (1) arranged in a horizontal direction and a vertical direction, and a vertical transfer register (2) for vertically transferring electric charges of the light receiving units (1). In the imaging device, the vertical transfer register (2) includes a channel region (4) having a width of 4 μm or less and a plurality of transfer electrodes (5) provided on the channel region (4) via an insulating film. A pair of transfer electrodes (5) correspond to the portion (1), and a plurality of transfer electrodes (5)
To transfer the charges injected into the channel region (4) sequentially by applying a four-phase clock signal to each of the transfer electrodes (5) (that is, in each transfer section (8)). (2) The channel width is divided into one or more stages so as to increase the electric field in the central portion and is sequentially widened in the transfer direction.
４μｍ以下の狭チャンネルの場合にはチャンネル幅の
少しの変化でもポテンシャルの深さが変化する。従っ
て、１つの転送電極内で、チャンネル幅を１段または複
数段に分けて転送方向に順次広げた場合、チャンネル幅
の大きい方がポテンシャルが深くなり、このためチャン
ネル幅の差によって１つの転送電極（５）内で電界が発
生し、その結果、転送電極中央部でのフリンジング電界
が強まり転送効率が向上する。また、チャンネル最大幅
の増加をできるだけ抑えることができチップサイズを抑
制できる。In the case of a narrow channel of 4 μm or less, even a small change in the channel width changes the potential depth. Therefore, in the case where the channel width is divided into one or a plurality of stages and sequentially expanded in the transfer direction within one transfer electrode, the larger the channel width, the deeper the potential. An electric field is generated in (5), and as a result, the fringing electric field at the center of the transfer electrode is strengthened, and the transfer efficiency is improved. Further, an increase in the maximum channel width can be suppressed as much as possible, and the chip size can be suppressed.
以下、図面を参照して本発明の実施例を説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図の本実施例はインターライン型CCD固体撮像装
置の要部を示すもので、水平及び垂直方向に所定ピッチ
をもって画素となる複数の受光部（１）が配列形成さ
れ、各列の受光部（１）の一側に受光部（１）の信号電
荷を垂直方向に転送するための垂直転送レジスタ（２）
が夫々配される。さらに図示でせざるも各垂直転送レジ
スタ（２）の端部に接して垂直転送レジスタ（２）から
の信号電荷を水平方向に転送する水平転送レジスタが配
される。FIG. 1 shows a main part of an interline type CCD solid-state imaging device, in which a plurality of light receiving portions (1) which become pixels at predetermined pitches in the horizontal and vertical directions are arranged and formed. A vertical transfer register (2) for vertically transferring the signal charge of the light receiving section (1) to one side of the section (1)
Are distributed respectively. Although not shown, a horizontal transfer register is provided in contact with an end of each vertical transfer register (2) to transfer the signal charge from the vertical transfer register (2) in the horizontal direction.
垂直転送レジスタ（２）は例えば第１導電形の半導体
基体に第２導電形の埋込みチャンネル領域（４）を形成
し、この上に絶縁膜を介して垂直方向に沿って複数の転
送電極（５）を被着してCCD構造の複数の転送部（８）
を形成して構成される。この場合垂直転送レジスタ
（２）は例えばクロック信号φ1,φ2,φ３及びφ４によ
る４相駆動を採用している。各受光部（１）はチャンネ
ルストップ領域（６）に区分され、受光部（１）垂直転
送レジスタ（２）間に読み出しゲート部（７）が形成さ
れる。この読み出しゲート部（７）は例えばチャンネル
ストップ領域（６）より低不純物濃度の領域上に絶縁膜
を介して転送電極（５）を延長して構成される。The vertical transfer register (2) forms, for example, a buried channel region (4) of the second conductivity type on a semiconductor substrate of the first conductivity type, and a plurality of transfer electrodes (5) on the buried channel region along the vertical direction via an insulating film. ) And multiple transfer units with CCD structure (8)
Is formed. In this case, the vertical transfer register (2) employs, for example, four-phase driving by clock signals φ 1 , φ 2 , φ 3 and φ 4 . Each light receiving section (1) is divided into a channel stop area (6), and a readout gate section (7) is formed between the light receiving sections (1) and the vertical transfer register (2). The read gate section (7) is formed by extending the transfer electrode (5) via an insulating film on a region having a lower impurity concentration than the channel stop region (6), for example.
そして本例では、特に垂直転送レジスタ（２）を、各
転送電極（５）内（すなわち各転送部（８）内）でチャ
ンネル幅（例えば４μｍ以下）が転送方向に向かって１
段で広がるように、即ち、転送電極内の中央部でチャン
ネル幅を広げるように形成する。即ち、チャンネル領域
（４）が転送方向の前半部の幅W1を小とし、後半部の幅
W2を大となるように形成される。In this example, in particular, the vertical transfer register (2) is set so that the channel width (for example, 4 μm or less) in each transfer electrode (5) (that is, in each transfer section (8)) is 1 in the transfer direction.
The channel is formed so as to spread in steps, that is, so as to widen the channel width in the central part in the transfer electrode. That is, the channel region (4) urban small width W 1 of the first half of the transfer direction, the width of the rear half portion
The W 2 is formed to be large.
この構成によれば、垂直転送レジスタ（２）におい
て、１つの転送部（８）内でチャンネル幅の異なる前半
部と後半部間でポテンシャル差が生じ転送方向のフリン
ジング電界、特に転送電極中央部付近のフリンジング電
界が強まる。このため、各転送部（８）内での電荷転送
がよくなり、全体として、狭チャンネルとした場合の垂
直転送レジスタ（２）の転送効率を上げることができ
る。特に各転送部（８）において、その中央部の電界を
強めるのが最も効果がある。According to this configuration, in the vertical transfer register (2), a potential difference is generated between the first half and the second half having different channel widths in one transfer section (8), and the fringing electric field in the transfer direction, particularly the center of the transfer electrode. The fringing electric field in the vicinity increases. For this reason, the charge transfer in each transfer section (8) is improved, and the transfer efficiency of the vertical transfer register (2) when the channel is narrow as a whole can be increased. In particular, in each transfer section (8), it is most effective to increase the electric field at the center.
転送電極の中央部付近のみに対応するチャンネル領域
（４）に段差を設けて、隣接する転送電極近傍のチャン
ネル領域には段差を設けないので、チャンネル最大幅の
増加をできるだけ抑えることができ、チップサイズを抑
制できる。Since a step is provided in the channel region (4) corresponding only to the vicinity of the center of the transfer electrode and no step is provided in the channel region near the adjacent transfer electrode, an increase in the maximum channel width can be suppressed as much as possible. Size can be suppressed.
垂直転送レジスタのチャンネル領域の形状としては、
上例の他、例えば第２図に示す形状としてもよい。第２
図は１つの転送部（８）内で複数段に分けてチャンネル
幅を順次広げるように構成した場合である。なお、第１
図及び第２図の例では垂直転送レジスタ（２）のチャン
ネル領域（４）の片側のみ形状を変えたが、両側を変え
るようにしてもよい。斯る構成とした場合においても、
第１図の例と同様に転送効率が上がる。As the shape of the channel area of the vertical transfer register,
In addition to the above example, for example, the shape shown in FIG. Second
The figure shows a case where the configuration is such that the channel width is sequentially increased in a plurality of stages within one transfer unit (8). The first
Although the shape of only one side of the channel area (4) of the vertical transfer register (2) is changed in the example of FIG. 2 and FIG. 2, both sides may be changed. Even in such a configuration,
The transfer efficiency increases as in the example of FIG.
本発明によれば、固体撮像装置において、その各転送
電極即ち各転送部内でチャンネル幅を転送方向に向かっ
て１段または複数段に分けて順次広げ、各転送部内で電
界を生じさせることによって、転送方向のフリンジング
電界、特に転送電極の中央部付近のフリンジング電界が
強まり、転送効率が改善される。According to the present invention, in the solid-state imaging device, the channel width in each transfer electrode, that is, in each transfer portion, is sequentially increased in one or more stages in the transfer direction, and an electric field is generated in each transfer portion. The fringing electric field in the transfer direction, in particular, the fringing electric field near the center of the transfer electrode is increased, and the transfer efficiency is improved.
また、チャンネル最大幅の増加をできるだけ抑えるこ
とができ、チップサイズを抑制できる。In addition, an increase in the maximum channel width can be suppressed as much as possible, and the chip size can be suppressed.
従って、例えば高解像度化のために垂直転送レジスタ
を狭チャンネルとしたインターライン型CCD固体撮像装
置に適用して好適ならしめるものである。Therefore, the present invention can be suitably applied to, for example, an interline type CCD solid-state imaging device having a narrow vertical transfer register for high resolution.
第１図及び第２図は夫々本発明の固体撮像装置の実施例
の要部の平面図、第３図はインターライン型CCD固体撮
像装置の原理的構成図、第４図は従来の固体撮像装置の
要部の平面図である。 （１）は受光部、（２）は垂直転送レジスタ、（３）は
水平転送レジスタ、（４）はチャンネル領域である。1 and 2 are plan views of the main parts of an embodiment of a solid-state imaging device according to the present invention, FIG. 3 is a diagram showing the basic configuration of an interline CCD solid-state imaging device, and FIG. It is a top view of the principal part of an apparatus. (1) is a light receiving section, (2) is a vertical transfer register, (3) is a horizontal transfer register, and (4) is a channel area.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴木 智行 東京都品川区北品川６丁目７番35号 ソ ニー株式会社内 (72)発明者 石川 貴久枝 東京都品川区北品川６丁目７番35号 ソ ニー株式会社内 (56)参考文献 特開 昭49−69090（ＪＰ，Ａ) 特開 昭62−39061（ＪＰ，Ａ) 特開 昭62−242363（ＪＰ，Ａ) 実開 昭51−81069（ＪＰ，Ｕ) ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Tomoyuki Suzuki 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Takahisa Ishikawa 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo No. Sony Corporation (56) References JP-A-49-69090 (JP, A) JP-A-62-39061 (JP, A) JP-A-62-242363 (JP, A) (JP, U)
Claims (1)
部と、該受光部の電荷を垂直方向に転送するための垂直
転送レジスタとを有するインターライン型CCD固体撮像
素子において、 上記垂直転送レジスタは幅４μｍ以下のチャンネル領域
と該チャンネル領域上に絶縁膜を介して設けられた複数
の転送電極とからなり、１つの受光部に一対の上記転送
電極が対応してなり、該複数の転送電極に４相のクロッ
ク信号を与えて上記チャンネル領域に注入された電荷を
順次転送するようになされ、上記各転送電極内で、該転
送電極中央部の電界を強めるようチャンネル幅を１段ま
たは複数段に分けて転送方向に順次広げてなる固体撮像
装置。1. An interline CCD solid-state imaging device having a plurality of light receiving units arranged in a horizontal direction and a vertical direction, and a vertical transfer register for vertically transferring electric charges of the light receiving units. The register includes a channel region having a width of 4 μm or less and a plurality of transfer electrodes provided on the channel region via an insulating film. One pair of the transfer electrodes corresponds to one light receiving portion. A four-phase clock signal is applied to the electrodes to sequentially transfer the charges injected into the channel region. In each of the transfer electrodes, the channel width is increased by one or more steps so as to increase the electric field at the center of the transfer electrode. A solid-state imaging device that is divided into stages and sequentially expanded in the transfer direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61159281A JP2586455B2 (en) | 1986-07-07 | 1986-07-07 | Solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61159281A JP2586455B2 (en) | 1986-07-07 | 1986-07-07 | Solid-state imaging device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8053520A Division JP2595924B2 (en) | 1996-03-11 | 1996-03-11 | Solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6315459A JPS6315459A (en) | 1988-01-22 |
| JP2586455B2 true JP2586455B2 (en) | 1997-02-26 |
Family
ID=15690367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61159281A Expired - Lifetime JP2586455B2 (en) | 1986-07-07 | 1986-07-07 | Solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2586455B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FI20051236A0 (en) | 2005-12-01 | 2005-12-01 | Artto Mikael Aurola | Semiconductor gadget |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4969090A (en) * | 1972-11-08 | 1974-07-04 | ||
| JPS5181069U (en) * | 1974-12-20 | 1976-06-28 | ||
| JPS6239061A (en) * | 1985-08-13 | 1987-02-20 | Mitsubishi Electric Corp | Solid-state image pickup element |
| JPS62242363A (en) * | 1986-04-14 | 1987-10-22 | Mitsubishi Electric Corp | Charge transfer device |
-
1986
- 1986-07-07 JP JP61159281A patent/JP2586455B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6315459A (en) | 1988-01-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |