JP2584836Y2 - Thermal head substrate - Google Patents
Thermal head substrateInfo
- Publication number
- JP2584836Y2 JP2584836Y2 JP2376092U JP2376092U JP2584836Y2 JP 2584836 Y2 JP2584836 Y2 JP 2584836Y2 JP 2376092 U JP2376092 U JP 2376092U JP 2376092 U JP2376092 U JP 2376092U JP 2584836 Y2 JP2584836 Y2 JP 2584836Y2
- Authority
- JP
- Japan
- Prior art keywords
- pads
- row
- electrode
- chip
- signal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
Landscapes
- Electronic Switches (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本考案は、ファクシミリやビデオ
プリンタ等に用いられるサーマルヘッド基板に関し、特
にサーマルヘッド配線の高密度化に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal head substrate used for a facsimile, a video printer, and the like, and more particularly, to a high density thermal head wiring.
【０００２】[0002]
【従来の技術】従来、サーマルヘッド基板は図２にその
一例を示す如く、絶縁性基板表面にグレーズ層１を焼成
し、その上に発熱抵抗体に信号を送る電極配線の電極パ
ッド２とＩＣチップ３を設け、前記電極パッド２はＩＣ
パッド４と平行に２列に並ぶように形成されている。そ
の列順をＩＣパッド側から第１列、第２列とすると、第
１列と第２列の電極パッドはＩＣチップと結線する方向
に対して交互に隣合うように配置されている。そして、
このＩＣパッド４と電極パッド２はワイヤーボンディン
グ法によって金線ワイヤ５で結線されている。2. Description of the Related Art Conventionally, as shown in FIG. 2, a thermal head substrate has a glaze layer 1 baked on an insulating substrate surface, and an electrode pad 2 of an electrode wiring for sending a signal to a heating resistor and an IC. A chip 3 is provided, and the electrode pad 2 is an IC.
The pads are formed so as to be arranged in two rows in parallel with the pads 4. Assuming that the order of the rows is the first row and the second row from the IC pad side, the first row and the second row of electrode pads are arranged so as to be alternately adjacent to each other in the direction of connection with the IC chip. And
The IC pad 4 and the electrode pad 2 are connected by a gold wire 5 by a wire bonding method.
【０００３】[0003]
【考案が解決しようとする課題】近年、サーマルヘッド
は印字の高密度化に伴い金線ワイヤ５で結線して平行に
配置した多数の電極がますます接近するようになってき
ている。しかし、従来のサーマルヘッド基板上に形成さ
れた電極を用いて高密度なワイヤーボンディングを行う
と、第２列の電極パッド２を結線するとき、図２に点線
で示すように電極パッド２上に形成される二次ボンディ
ング形状６が第１列の電極パッド２から延びた信号線電
極７に接触して回路がショートし不良となってしまう。
信号線電極７の幅を細くすることによっても二次ボンデ
ィング形状６との接触を回避することができると思われ
るが、信号線電極７を細くすることは電極の配線抵抗を
上昇させ、印字において濃度むらを発生させる原因とな
ってしまうのであまり細くできない。[Problems to be Solved by the Invention] In recent years, as the density of printing has been increased, a large number of electrodes connected in parallel by gold wire 5 have been increasingly approached. However, when high-density wire bonding is performed using the electrodes formed on the conventional thermal head substrate, when the electrode pads 2 in the second row are connected, as shown by the dotted lines in FIG. The formed secondary bonding shape 6 comes into contact with the signal line electrode 7 extending from the electrode pad 2 in the first row, causing a short circuit and a failure.
It is thought that the contact with the secondary bonding shape 6 can be avoided by reducing the width of the signal line electrode 7. However, reducing the signal line electrode 7 increases the wiring resistance of the electrode and reduces the printing quality. Since it causes density unevenness, it cannot be made very thin.
【０００４】従って、電極の幅を細くすることなしにワ
イヤーボンディングを行っても二次ボンディング形状６
による第１列の信号電極線７はショート不良を無くする
ことが課題であった。Accordingly, even if wire bonding is performed without reducing the width of the electrode, the secondary bonding shape 6 can be reduced.
Therefore, the problem was to eliminate short-circuit defects in the signal electrode lines 7 in the first column.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
に、この考案では電極パッドをＩＣのパッドと平行に３
列設け、その列順をＩＣパッド側から第１列、第２列、
第３列とすると、第１列に設けられた隣接する２個のパ
ッドの間に第２列のパッドを設けて、これら３個のパッ
ドを１組としたときに隣接する２組のパッド群の間に第
３列のパッドを設けた。そして、第１列に設けられた隣
接する２個のパッドから延びる信号線電極はその間に設
けられた第２列のパッドを両側から距離をおいて囲むよ
うに設置し、さらに、この第１列のパッドの２本の信号
線電極と第２列のパッドの信号線電極を合わせた３本の
信号線電極は第３列のパッドの隣接するパッド間を通
り、第３列のパッドに最も近い第１列のパッドから延び
た信号線電極が第３列のパッドと一定の距離をおいて囲
むように設けた。In order to solve the above-mentioned problems, in the present invention, the electrode pads are arranged in parallel with the IC pads.
Columns, and the order of the columns is from the IC pad side to the first column, the second column,
Assuming that the third row is, a second row of pads is provided between two adjacent pads provided in the first row, and when these three pads constitute one set, two sets of adjacent pad groups The third row of pads was provided between the pads. The signal line electrodes extending from two adjacent pads provided in the first row are disposed so as to surround the second row of pads provided therebetween at a distance from both sides, and further, the first row The three signal line electrodes including the two signal line electrodes of the second pad and the signal line electrode of the second column pad pass between adjacent pads of the third column pad and are closest to the third column pad. The signal line electrodes extending from the pads in the first row were provided so as to surround the pads in the third row at a fixed distance.
【０００６】[0006]
【作用】上記のような特徴をもったサーマルヘッド基板
は２列配置の従来の電極パッドと比較して第２列目の電
極パッド間を広くとることができる。従って、第１列か
ら延びる信号線電極は第２列目のパッドに打たれたワイ
ヤーボンディングの二次ボンディング形状に接触しない
十分な距離をおいて配線することができる。さらに、第
３列目の電極パッド間も第２列目と同様に十分な距離を
おいて配線することができるので、第２列目から延びる
信号線電極を第３列目のパッドの間を通しても第１列目
のパッドから延びる２本の信号線電極を第３列目のパッ
ドに打たれたワイヤーボンディングの二次ボンディング
形状に接触する事がなくなる。In the thermal head substrate having the above-described features, the space between the electrode pads in the second row can be made wider than that of the conventional electrode pads in two rows. Therefore, the signal line electrodes extending from the first row can be wired at a sufficient distance so as not to contact the secondary bonding shape of the wire bonding hit on the second row pad. Furthermore, since the wiring can be wired with a sufficient distance between the electrode pads of the third row as in the second row, the signal line electrodes extending from the second row pass through the pads of the third row. Also, the two signal line electrodes extending from the pads in the first row do not come into contact with the secondary bonding shape of the wire bonding hit on the pads in the third row.
【０００７】[0007]
【実施例】以下に、本考案の実施例を図１に基づいて説
明する。アルミナ等の絶縁基板上には、ガラスペースト
を印刷焼成したグレーズ層１が一定の厚みで形成されて
おり、このグレーズ層１の上面には信号線電極７、電極
パッド２が形成されると共に、これら信号線電極７、電
極パッド２に相対する同一基板平面上にはＩＣパッド４
を有するＩＣチップ３が載置されている。前記信号線電
極７の端部は図示しない発熱抵抗体に接続されており、
該発熱抵抗体は前記ＩＣチップ３からの通電制御信号を
受けて選択的に発熱し、記録紙に印字を行う。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. On an insulating substrate such as alumina, a glaze layer 1 formed by printing and firing a glass paste is formed with a certain thickness. On the upper surface of the glaze layer 1, signal line electrodes 7 and electrode pads 2 are formed. An IC pad 4 is provided on the same substrate plane facing the signal line electrode 7 and the electrode pad 2.
Is mounted. An end of the signal line electrode 7 is connected to a heating resistor (not shown).
The heating resistor selectively receives heat from the IC chip 3 to generate heat and prints on recording paper.
【０００８】前記電極パッド２は前記信号線電極の端部
に前記ＩＣとの間でワイヤーボンディングによる電気的
接続を行うために設けられており、これら電極パッド２
は前記ＩＣチップのＩＣパッドの数に応じて複数設けら
れており、各電極パッド２は前記ＩＣチップに対し、前
後に位置するよう例えば千鳥状に配列されている。この
配列をさらに詳述すれば、各電極パッド２は、前記ＩＣ
チップのＩＣパッド４との接合のために金線ワイヤ５を
ワイヤボンドした時に生ずる前記金線ワイヤ５のつぶ
れ、溶着等による二次ボンディング形状６が隣接して設
けた他の電極パッド及び信号線電極に接触しないよう、
各電極パッド２との間に充分な隙間を持って配置する必
要があり、このため、前記ＩＣパッド４側に最も接近し
た位置に第１列目の電極パッドを形成し、この第１列目
の電極パッドの後方に前記第１列目の電極パッドの信号
線電極に囲まれた第２列目の電極パッドを形成し、さら
に前記第２列目の電極パッドの後方に前記第１列目およ
び第２列目の信号線電極に囲まれて第３列目の電極パッ
ドを形成している。即ち、このような電極パッドの配列
により各電極パッド、および各信号線電極との間に充分
な間隔を確保することができ、その結果、前記二次ボン
ディング形状による電極間ショートが防止できる。The electrode pads 2 are provided at the ends of the signal line electrodes for making an electrical connection with the IC by wire bonding.
Are provided in accordance with the number of IC pads of the IC chip, and the electrode pads 2 are arranged, for example, in a staggered manner so as to be located in front of and behind the IC chip. To describe this arrangement in more detail, each electrode pad 2 is
Other electrode pads and signal lines adjacent to the secondary bonding shape 6 formed by crushing, welding, etc. of the gold wire 5 generated when the gold wire 5 is wire-bonded for bonding with the IC pad 4 of the chip. Do not touch the electrodes
It is necessary to arrange a sufficient gap between each of the electrode pads 2. Therefore, a first row of electrode pads is formed at a position closest to the IC pad 4 side, and the first row of electrode pads is formed. A second row of electrode pads surrounded by signal line electrodes of the first row of electrode pads is formed behind the first row of electrode pads, and the first row of electrode pads is further formed behind the second row of electrode pads. And a third column electrode pad surrounded by the signal line electrodes of the second column. That is, such an arrangement of the electrode pads can secure a sufficient interval between each electrode pad and each signal line electrode, and as a result, a short circuit between the electrodes due to the secondary bonding shape can be prevented.
【０００９】[0009]
【考案の効果】以上のように本考案によれば、電極パッ
ドとＩＣパッドを結線しているワイヤーボンディングの
電極パッド上の二次ボンディング形状が隣接して配置さ
れた電極パッドから延びる信号線電極に接触することを
防止し、ショート不良の無いサーマルヘッド基板を提供
することができる。As described above, according to the present invention, the signal line electrode extending from the adjacently arranged electrode pad has a secondary bonding shape on the electrode pad for wire bonding connecting the electrode pad and the IC pad. And a thermal head substrate free from short-circuit failure can be provided.
【図１】本考案のサーマルヘッド基板である。FIG. 1 is a thermal head substrate of the present invention.
【図２】従来のサーマルヘッド基板である。FIG. 2 is a conventional thermal head substrate.
１ グレーズ層 ２ 電極パッド ３ ＩＣチップ ４ ＩＣパッド ５ 金線ワイヤ ６ 二次ボンディング形状 ７ 信号線電極 DESCRIPTION OF SYMBOLS 1 Glaze layer 2 Electrode pad 3 IC chip 4 IC pad 5 Gold wire 6 Secondary bonding shape 7 Signal line electrode
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) B41J 2/345 H01L 21/60 301──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) B41J 2/345 H01L 21/60 301
Claims (2)
グレーズ層と、前記グレーズ層上に形成された発熱抵抗
体と、前記発熱抵抗体に電力を供給するために前記グレ
ーズ層上に設けられた複数の信号線電極と、前記発熱抵
抗体を駆動するために前記基板上に設けられたＩＣチッ
プと、前記ＩＣチップのＩＣパッドとワイヤーボンディ
ングにより電気的に接続するために前記信号線電極の端
部に設けられた複数の電極パッドと、を備えるととも
に、 前記電極パッドは前記ＩＣパッドに対して平行に３列で
構成され、 前記ＩＣチップに最も近接する第１列の電極パッドの信
号線電極が、第１列の電極パッドよりもＩＣチップと遠
い側に設けられた第２列及び第３列の電極パッドを避け
るために囲んで配線され、 第１列の電極パッドの隣接する信号線電極の間に、第２
列または第３列の電極パッドのうちいずれか一方の電極
パッドを配置する ことを特徴とするサーマルヘッド基
板。1. An insulating substrate, and an insulating substrate formed on the substrate.
A glaze layer, and a heating resistor formed on the glaze layer
Body and the grate for supplying power to the heating resistor.
A plurality of signal line electrodes provided on the fuse layer and the heating resistor.
An IC chip provided on the substrate for driving the antibody
And the IC pad and wire bonder of the IC chip.
End of the signal line electrode for electrical connection by
A plurality of electrode pads provided in the
The electrode pads are arranged in three rows in parallel with the IC pads.
Configured, or receive the first column electrode pad which is closest to the IC chip
Line electrode is farther from the IC chip than the first row of electrode pads
Avoid the second and third rows of electrode pads
Between the adjacent signal line electrodes of the first row of electrode pads.
Either of the row or third row of electrode pads
A thermal head substrate on which pads are arranged .
のＩＣパッドのうちＩＣチップ外形に近い側のＩＣパッ
ドと前記第２列または第３列の電極パッドとをワイヤで
接続し、２列のＩＣパッドのうちＩＣチップ外形に遠い
側のＩＣパッドと前記第１列の電極パッドとをワイヤで
接続したことを特徴とする請求項１に記載のサーマルヘ
ッド基板。2. The semiconductor device according to claim 2, wherein the IC pads are formed in two rows.
Of the IC pads on the side closer to the outer shape of the IC chip.
And the second row or the third row of electrode pads with wires.
Connected, far from the IC chip outline of the two rows of IC pads
Side IC pads and the first row of electrode pads with wires
The thermal head substrate according to claim 1, characterized in that connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2376092U JP2584836Y2 (en) | 1992-04-14 | 1992-04-14 | Thermal head substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2376092U JP2584836Y2 (en) | 1992-04-14 | 1992-04-14 | Thermal head substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0582550U JPH0582550U (en) | 1993-11-09 |
| JP2584836Y2 true JP2584836Y2 (en) | 1998-11-11 |
Family
ID=12119293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2376092U Expired - Lifetime JP2584836Y2 (en) | 1992-04-14 | 1992-04-14 | Thermal head substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2584836Y2 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58107844U (en) * | 1982-01-13 | 1983-07-22 | 株式会社東芝 | thermal head |
| JPS6013767U (en) * | 1983-07-06 | 1985-01-30 | セイコーインスツルメンツ株式会社 | Electrode structure in line thermal head |
| JPS62162858U (en) * | 1986-04-04 | 1987-10-16 | ||
| JP3112936U (en) * | 2005-04-04 | 2005-09-02 | 株式会社田原屋 | Flat curtain |
-
1992
- 1992-04-14 JP JP2376092U patent/JP2584836Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0582550U (en) | 1993-11-09 |
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