JP2759730B2 - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JP2759730B2 JP2759730B2 JP4307592A JP30759292A JP2759730B2 JP 2759730 B2 JP2759730 B2 JP 2759730B2 JP 4307592 A JP4307592 A JP 4307592A JP 30759292 A JP30759292 A JP 30759292A JP 2759730 B2 JP2759730 B2 JP 2759730B2
- Authority
- JP
- Japan
- Prior art keywords
- gold
- bonding pad
- paste
- gold paste
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
- H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
- H01L2224/4848—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
- H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Electronic Switches (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は、サーマルプリントヘッ
ド等に適用される、金ペーストにて導体パターンを形成
する印刷回路基板において、金ペーストをワイヤボンデ
ィング強度を落とさずに、その使用量の削減を可能にし
た印刷回路基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board for forming a conductive pattern with a gold paste, which is applied to a thermal print head or the like, and reduces the amount of the gold paste used without reducing wire bonding strength. The present invention relates to a printed circuit board which enables the above.
【０００２】[0002]
【従来の技術及びその問題点】金ペーストにて導体パタ
ーンを形成する印刷回路基板は、例えば厚膜サーマルプ
リントヘッドに適用されている。この厚膜サーマルプリ
ントヘッドは、図５に示すように絶縁基板１に金ペース
トを印刷焼成して導体膜を形成する。さらにエッチング
法により共通電極５、個別電極２、その他の配線パター
ンが形成される。そしてこれらの上層には、発熱抵抗体
７、保護膜等が印刷焼成される。さらに絶縁基板１上に
は駆動用のドライバーＩＣチップ１１がダイボンディン
グされており、該ＩＣチップ１１のワイヤボンディング
パッド１２と前記印刷配線基板のボンディングパッド４
が金ワイヤ９にて接続される。2. Description of the Related Art A printed circuit board on which a conductive pattern is formed by using a gold paste is applied to, for example, a thick-film thermal printhead. In this thick film thermal print head, as shown in FIG. 5, a gold paste is printed and baked on the insulating substrate 1 to form a conductor film. Further, the common electrode 5, the individual electrode 2, and other wiring patterns are formed by the etching method. The heating resistor 7, the protective film, and the like are printed and fired on these upper layers. Further, a driver IC chip 11 for driving is die-bonded on the insulating substrate 1, and a wire bonding pad 12 of the IC chip 11 and a bonding pad 4 of the printed wiring board are bonded.
Are connected by a gold wire 9.
【０００３】前記導体パターンを形成する金ペースト
は、有機金ペーストと無機金ペーストとが知られている
が、前記厚膜サーマルプリントヘッドの場合、発熱抵抗
体７の発熱エネルギーを効率良く感熱紙に伝えるため
に、有機金ペーストを使用した金導体膜厚を薄く形成
し、個別電極（金導体）２からの放熱を防ぐことが一般
的である。しかしながら、このままでは金ワイヤボンデ
ィング部４でのワイヤボンディング強度が低く信頼性が
確保されない。これを改善するためにサーマルプリント
ヘッドのボンディング部の金導体の膜厚を厚く形成する
ことによりボンディング強度を高めている。As the gold paste for forming the conductor pattern, an organic gold paste and an inorganic gold paste are known. In the case of the thick film thermal print head, the heat generated by the heat generating resistor 7 is efficiently transferred to the thermal paper. In general, it is common to form a thin gold conductor film using an organic gold paste to prevent heat radiation from the individual electrodes (gold conductors) 2 for transmission. However, in this state, the wire bonding strength at the gold wire bonding portion 4 is low, and reliability cannot be secured. In order to improve this, the bonding strength is increased by forming a thick film of the gold conductor in the bonding portion of the thermal print head.
【０００４】この方法の一例として図３に示すようなサ
ーマルプリントヘッドにおいて、絶縁基板１上に有機金
ペースト層によって形成された個別電極用金導体２の上
部に無機金ペースト層にて導体パターン３を形成した２
層構造のボンディングパッド４が知られているが（特公
平４ー２６７８２号公報）、無機金ペーストは金含有量
が７０％以上と有機金ペーストの金含有量３０％以下に
比べ非常に高い。このため、無機金ペーストは印刷法に
て形成する場合、１回の印刷で形成される膜厚が１μｍ
前後が下限であり、これ以上に膜厚を薄く形成すること
は困難である。そして、前記ワイヤボンディングの際、
実際に使用される前記ボンディングパッド４の前記金導
体２の膜厚は１μｍ前後であり、この方法では下層の前
記金導体２との膜厚総和が１μｍを大きく上回ってしま
い、余分に金ペーストを使用することになり、製品コス
トが高くなる。As an example of this method, in a thermal print head as shown in FIG. 3, a conductor pattern 3 is formed by an inorganic gold paste layer on an individual electrode gold conductor 2 formed by an organic gold paste layer on an insulating substrate 1. Formed 2
Although a bonding pad 4 having a layered structure is known (Japanese Patent Publication No. Hei 4-26782), the inorganic gold paste has a gold content of 70% or more, which is much higher than that of an organic gold paste of 30% or less. For this reason, when the inorganic gold paste is formed by a printing method, the film thickness formed by one printing is 1 μm.
The lower limit is before and after, and it is difficult to form a thinner film than this. And, at the time of the wire bonding,
The thickness of the gold conductor 2 of the bonding pad 4 actually used is about 1 μm, and in this method, the total thickness of the gold conductor 2 and the lower layer of the gold conductor 2 greatly exceeds 1 μm. Use, which increases the product cost.
【０００５】さらに、ボンディングパッド４のみに無機
金ペーストの印刷パターンを小さく形成すると、印刷時
のサイドエッジ効果によって印刷パターンの外周部に盛
り上がり３Ａが生じて、平坦なボンディングパッドが得
られなくなるのでボンディング強度の低下を招く。尚、
前記サーマルプリントヘッドは、絶縁基板１上に共通電
極５、発熱抵抗体７、保護膜８、ドライバーＩＣ１１を
備えてなり、無機ペースト層３のボンディングパッド４
において、金ワイヤ９でドライバーＩＣ１１のワイヤボ
ンデングパッド（図示せず）とワイヤボンディングされ
る。Further, if a small printed pattern of the inorganic gold paste is formed only on the bonding pad 4, a bulge 3A occurs on the outer peripheral portion of the printed pattern due to a side edge effect at the time of printing, and a flat bonding pad cannot be obtained. This leads to a decrease in strength. still,
The thermal print head includes a common electrode 5, a heating resistor 7, a protective film 8, and a driver IC 11 on an insulating substrate 1, and a bonding pad 4 of an inorganic paste layer 3.
Then, the gold wire 9 is wire-bonded to a wire bonding pad (not shown) of the driver IC 11.
【０００６】また、他の例として図４に示す方法が知ら
れている。この例は、絶縁基板上１に有機金ペーストに
て金電極（個別電極）２を形成し、さらにボンディング
パッド４の上層に同じく有機金ペーストにて金導体２Ａ
を形成して、前記ボンディングパッド４の金電極の膜厚
総和を上げることによって、ワイヤボンディング強度を
確保している。この例の場合は、有機金ペーストはペー
スト中の金含有量が低いため、１回の印刷で形成できる
金導体の膜厚が０．２μｍ程度と薄い。このため、ワイ
ヤボンディング強度確保のために必要な１μｍ前後を形
成するために、下層の金電極の上に、さらに数回の印刷
が必要となり、製造工程数が増えるという問題がある。As another example, a method shown in FIG. 4 is known. In this example, a gold electrode (individual electrode) 2 is formed on an insulating substrate 1 with an organic gold paste, and a gold conductor 2A is formed on the bonding pad 4 with the same organic gold paste.
Is formed to increase the total thickness of the gold electrodes of the bonding pads 4 to secure the wire bonding strength. In this case, since the organic gold paste has a low gold content in the paste, the thickness of the gold conductor that can be formed by one printing is as thin as about 0.2 μm. For this reason, in order to form about 1 μm necessary for securing the wire bonding strength, several times of printing are required on the lower gold electrode, and the number of manufacturing steps is increased.
【０００７】[0007]
【発明が解決しようとする課題】本発明は、前記問題点
に鑑み、前記有機金ペースト、無機金ペーストを使用し
た場合の、それぞれの問題点を解決し、製造工程を増や
すことなく、金ペーストも必要以上に使用しなくてもボ
ンディングパッドの形成可能な印刷回路基板を提供する
ものである。SUMMARY OF THE INVENTION In view of the above problems, the present invention solves each of the problems when the organic gold paste and the inorganic gold paste are used. The present invention also provides a printed circuit board on which a bonding pad can be formed without using it more than necessary.
【０００８】[0008]
【課題を解決するための手段】本発明は、前記課題を解
決するために、絶縁基板上に、有機金ペーストを用いて
導体パターンを形成してなる印刷回路基板において、前
記導体パターンのボンディングパッドに、有機金ペース
トと無機金ペーストとを混合した混合ペーストを用いて
ボンディングパッドパターンを形成することを特徴とす
る。According to the present invention, there is provided a printed circuit board having a conductive pattern formed on an insulating substrate by using an organic gold paste. In addition, a bonding pad pattern is formed using a mixed paste obtained by mixing an organic gold paste and an inorganic gold paste.
【０００９】[0009]
【実施例】図１は、本発明ボンディングパッド形成の実
施例を示している。絶縁基板１上に、有機金ペーストを
使用し、印刷焼成を数回繰り返し、所定の膜厚の有機金
ペースト層による金電極（個別電極）２を形成する。ボ
ンディングパッド４には、有機金ペーストと無機金ペー
ストとを混合した混合ペースト１０Ａを１回の印刷焼成
にて形成する。FIG. 1 shows an embodiment of forming a bonding pad according to the present invention. Using an organic gold paste, printing and baking are repeated several times on the insulating substrate 1 to form a gold electrode (individual electrode) 2 of an organic gold paste layer having a predetermined thickness. On the bonding pad 4, a mixed paste 10A obtained by mixing an organic gold paste and an inorganic gold paste is formed by one printing firing.
【００１０】この時、下層の有機金ペースト層２の膜厚
は、発熱抵抗体７に流れる電流値に応じて膜厚を決定す
れば良い。そして、上層の有機金ペーストと無機金ペー
スト層との混合ペースト層１０Ａの膜厚は、下層の有機
金ペースト層２との総和が１μｍ程度になるように設定
すれば良く、上層の膜厚としては１回の印刷焼成で十分
に必要とする膜厚を得ることができる。At this time, the thickness of the lower organic gold paste layer 2 may be determined according to the value of the current flowing through the heating resistor 7. The thickness of the mixed paste layer 10A of the upper organic gold paste and the inorganic gold paste layer may be set so that the sum of the lower organic gold paste layer 2 and the lower organic gold paste layer 2 is about 1 μm. Can sufficiently obtain a required film thickness by one printing and firing.
【００１１】この時に必要とする膜厚に応じて、有機金
ペーストと無機金ペーストの混合比を選べば、最適の膜
厚が得られ、品質の安定化が図れる。また他の実施例と
して、図２に示すように、図１に示す実施例のボンディ
ングパッド４の下層の有機金ペースト層を削除し、前記
混合ペースト層１０Ｂを絶縁基板１上に直接形成しても
良い。If the mixing ratio of the organic gold paste and the inorganic gold paste is selected according to the required film thickness at this time, the optimum film thickness can be obtained and the quality can be stabilized. As another embodiment, as shown in FIG. 2, the organic gold paste layer below the bonding pad 4 of the embodiment shown in FIG. 1 is deleted, and the mixed paste layer 10B is formed directly on the insulating substrate 1. Is also good.
【００１２】前記どちらの方法を用いても、有機金ペー
ストの１回当たりの膜厚の薄さと印刷焼成後の表面の平
坦性と、無機金ペーストの１回当たりの膜厚の厚さと、
金含有量の高さによりボンディング強度の高さの相乗効
果が得られ、必要最低膜厚にて、ボンディング強度を確
保することができる。In either method, the thinness of the thickness of the organic gold paste per one time, the flatness of the surface after printing and firing, the thickness of the inorganic gold paste per one time,
The synergistic effect of the high bonding strength is obtained by the high gold content, and the bonding strength can be ensured at the minimum necessary film thickness.
【００１３】前記前記混合ペーストにてボンディングパ
ッドが形成された後、共通電極５と個別電極２のパター
ン上層に発熱抵抗体７、保護膜８を同じく印刷焼成にて
形成した後、ヘッド基板１上にドライバーＩＣ１１をダ
イボンディングし、該ドライバーＩＣ１１のボンディン
グパッドと個別電極２の本発明ボンディングパッドを金
ワイヤ９にて接続する。After the bonding pad is formed from the mixed paste, the heating resistor 7 and the protective film 8 are formed on the pattern of the common electrode 5 and the individual electrode 2 by printing and sintering. Then, the driver IC 11 is die-bonded to the bonding pad of the driver IC 11 and the bonding pad of the present invention of the individual electrode 2 by the gold wire 9.
【００１４】[0014]
【発明の効果】以上説明したように、本発明印刷回路基
板は、金ワイヤボンディング強度に必要な金電極膜厚を
必要最低限度に押えることが可能であり、且つボンディ
ングパッドについて１回の印刷焼成回数で必要な膜厚を
得ることができるため、コストの安い製品を供給するこ
とが可能となる。また、表面の平坦なボンディングパッ
ドパターンを得ることができるので、ボンディングの信
頼性も向上する。As described above, according to the printed circuit board of the present invention, the thickness of the gold electrode required for the gold wire bonding strength can be suppressed to the minimum necessary, and the printing of the bonding pad is performed once. Since the required film thickness can be obtained by the number of times, it is possible to supply a low-cost product. Further, since a bonding pad pattern having a flat surface can be obtained, the reliability of bonding is also improved.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明第１実施例の要部断面図である。FIG. 1 is a sectional view of a main part of a first embodiment of the present invention.
【図２】本発明第２実施例の要部断面図である。FIG. 2 is a sectional view of a main part of a second embodiment of the present invention.
【図３】第１の従来例の要部断面図である。FIG. 3 is a sectional view of a main part of a first conventional example.
【図４】第２の従来例の要部断面図である。FIG. 4 is a sectional view of a main part of a second conventional example.
【図５】一般的なサーマルプリントヘッドの要部平面図
である。FIG. 5 is a plan view of a main part of a general thermal print head.
１ 絶縁基板 ２ 有機金ペーストで形成した金電極 ４ ボンディングパッド ９ 金ワイヤ １０Ａ、１０Ｂ 有機金ペーストと無機金ペーストとを
混合した混合ペースト層 １１ ドライバーＩＣREFERENCE SIGNS LIST 1 insulating substrate 2 gold electrode formed of organic gold paste 4 bonding pad 9 gold wire 10A, 10B mixed paste layer obtained by mixing organic gold paste and inorganic gold paste 11 driver IC
フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 301 H05K 1/09Continuation of front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60 301 H05K 1/09
Claims (3)
導体パターンを形成してなる印刷回路基板において、前
記導体パターンのボンディングパッドに、有機金ペース
トと無機金ペーストとを混合した混合ペーストを用いて
ボンディングパッドパターンを形成したことを特徴とす
る印刷回路基板。1. A printed circuit board having a conductive pattern formed on an insulating substrate using an organic gold paste, wherein a mixed paste obtained by mixing an organic gold paste and an inorganic gold paste is applied to a bonding pad of the conductive pattern. A printed circuit board, wherein a bonding pad pattern is formed using the same.
導体パターン上に形成したことを特徴とする請求項１記
載の印刷回路基板。2. The printed circuit board according to claim 1, wherein said bonding pad pattern is formed on said conductor pattern.
ボンディングパッドの前記導体パターンを削除して前記
絶縁基板に直接形成したことを特徴とする請求項１記載
の印刷回路基板。3. The printed circuit board according to claim 1, wherein the bonding pad pattern is formed directly on the insulating substrate by removing the conductor pattern of the bonding pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4307592A JP2759730B2 (en) | 1992-10-21 | 1992-10-21 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4307592A JP2759730B2 (en) | 1992-10-21 | 1992-10-21 | Printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06132338A JPH06132338A (en) | 1994-05-13 |
| JP2759730B2 true JP2759730B2 (en) | 1998-05-28 |
Family
ID=17970925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4307592A Expired - Lifetime JP2759730B2 (en) | 1992-10-21 | 1992-10-21 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2759730B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6202721B2 (en) | 2013-04-08 | 2017-09-27 | アオイ電子株式会社 | Circuit board and thermal print head using the same |
-
1992
- 1992-10-21 JP JP4307592A patent/JP2759730B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06132338A (en) | 1994-05-13 |
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