JP2576274B2 - Frame synchronization circuit - Google Patents
Frame synchronization circuitInfo
- Publication number
- JP2576274B2 JP2576274B2 JP2213882A JP21388290A JP2576274B2 JP 2576274 B2 JP2576274 B2 JP 2576274B2 JP 2213882 A JP2213882 A JP 2213882A JP 21388290 A JP21388290 A JP 21388290A JP 2576274 B2 JP2576274 B2 JP 2576274B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frame synchronization
- circuit
- synchronization circuit
- determination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Mobile Radio Communication Systems (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はフレーム同期回路に関し、特に無線ディジタ
ル伝送における主ディジタル信号に補助信号を多重化し
た場合のフレーム同期回路に関する。Description: BACKGROUND OF THE INVENTION The present invention relates to a frame synchronization circuit, and more particularly to a frame synchronization circuit in which an auxiliary signal is multiplexed on a main digital signal in wireless digital transmission.
従来、この種のフレーム同期回路は、第２図のブロッ
ク図に示すように、第１のフレーム同期回路101、補助
信号分離用の分離化回路102、第２のフレーム同期回路1
04から構成される。次に従来例の動作を説明すると、第
１のフレーム同期回路101は、復調後の多重化信号11か
らフレーム同期を確立している旨の判定結果信号16を出
力するとともに、無線フレームの基準を示すフレームパ
ルス12を分離化回路102へ送出する。分離化回路102は、
フレームパルス12に基づき、復調後の多重化信号11から
補助信号14を分離して主ディジタル信号13を出力する。
第２のフレーム同期回路104は、この補助信号14のフレ
ーム同期を確立してその判定結果信号15を出力する。Conventionally, this type of frame synchronization circuit includes a first frame synchronization circuit 101, a separation circuit 102 for separating auxiliary signals, and a second frame synchronization circuit 1 as shown in the block diagram of FIG.
Consists of 04. Next, the operation of the conventional example will be described. The first frame synchronization circuit 101 outputs a determination result signal 16 indicating that frame synchronization has been established from the multiplexed signal 11 after demodulation, and determines the reference of the radio frame. The indicated frame pulse 12 is transmitted to the separation circuit 102. The separation circuit 102
Based on the frame pulse 12, the auxiliary signal 14 is separated from the multiplexed signal 11 after demodulation, and the main digital signal 13 is output.
The second frame synchronization circuit 104 establishes frame synchronization of the auxiliary signal 14 and outputs the determination result signal 15.
上述した従来のフレーム同期回路は、補助信号のフレ
ーム同期の判定を第２のフレーム同期回路において行っ
ているが、主信号に比較して低速な補助信号のフレーム
同期パターンの監視によってのみ行っているので、補助
信号のフレーム同期の判定に長い時間を要する欠点があ
る。In the above-described conventional frame synchronization circuit, the frame synchronization of the auxiliary signal is determined in the second frame synchronization circuit, but is determined only by monitoring the frame synchronization pattern of the auxiliary signal which is slower than the main signal. Therefore, there is a disadvantage that it takes a long time to determine the frame synchronization of the auxiliary signal.
本発明のフレーム同期回路は、無線ディジタル伝送に
おけるディジタル信号に補助信号を多重化した多重化信
号の同期確認を行うフレーム同期回路において、前記多
重化信号のフレーム同期を判定し第１の判定信号を出力
する第１のフレーム同期回路と、前記多重化信号から補
助信号を分離する分離化回路と、前記分離化回路で分離
された補助信号と前記第１の判定信号とを入力し、前記
第１の判定信号同期外れの判定結果を出力した場合に
は、通常行われている補助信号の同期判定動作を中止し
て同期外れを報知する第２の判定信号を出力する第２の
フレーム同期回路とを有する。A frame synchronization circuit according to the present invention is a frame synchronization circuit for confirming synchronization of a multiplexed signal obtained by multiplexing an auxiliary signal with a digital signal in wireless digital transmission, wherein the frame synchronization of the multiplexed signal is determined, and a first determination signal is determined. A first frame synchronization circuit for outputting, a separation circuit for separating an auxiliary signal from the multiplexed signal, an auxiliary signal separated by the separation circuit and the first determination signal, When the determination result of the determination signal is out of synchronization, the second frame synchronization circuit that stops the synchronization determination operation of the auxiliary signal that is normally performed and outputs a second determination signal for notifying the loss of synchronization is output. Having.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例のブロック図である。本実
施例は従来例と同様の第１のフレーム同期回路101、分
離化回路102に、本発明の第２のフレーム同期回路103を
備えて構成される。FIG. 1 is a block diagram of one embodiment of the present invention. In this embodiment, a first frame synchronization circuit 101 and a demultiplexing circuit 102 similar to the conventional example are provided with a second frame synchronization circuit 103 of the present invention.
次に、本実施例の動作を説明する。第２のフレーム同
期判定回路103は、補助信号14のフレーム同期を確立
し、その判定結果信号15を送出するが、第１のフレーム
同期回路101の判定結果信号16をも入力して判定結果信
号16がフレーム同期外れの場合に、第２のフレーム同期
回路103の判定結果信号15を強制的にフレーム同期外れ
とする。すなわち、主ディジタル信号のフレーム同期が
外れた場合には、補助信号のフレーム同期を確認するま
でもなく同期外れとなるので、判定結果信号15を強制的
に同期外れとする。Next, the operation of this embodiment will be described. The second frame synchronization determination circuit 103 establishes frame synchronization of the auxiliary signal 14 and sends out the determination result signal 15, but also receives the determination result signal 16 of the first frame synchronization circuit 101 and outputs the determination result signal. When 16 is out of frame synchronization, the determination result signal 15 of the second frame synchronization circuit 103 is forcibly made out of frame synchronization. That is, when the frame synchronization of the main digital signal is lost, the synchronization is lost without confirming the frame synchronization of the auxiliary signal, so that the determination result signal 15 is forcibly out of synchronization.
以上説明したように本発明は、第１のフレーム同期回
路の主ディジタル信号の同期判定結果信号を第２のフレ
ーム同期回路にも入力することにより、補助信号のフレ
ーム同期判定結果信号を主ディジタル信号がフレーム同
期外れの場合に強制的に非同期の判定を行っているの
で、補助信号フレーム同期外れの判定時間を短縮できる
結果がある。As described above, according to the present invention, the synchronization determination result signal of the main digital signal of the first frame synchronization circuit is also input to the second frame synchronization circuit, so that the frame synchronization determination result signal of the auxiliary signal is converted to the main digital signal. Is forcibly determined to be asynchronous when the frame is out of frame, so that there is a result that the determination time of the auxiliary signal frame out of synchronization can be reduced.
第１図は本発明の一実施例のブロック図、第２図は従来
のフレーム同期回路のブロック図である。 101……第１のフレーム同期回路、102……分離化回路、
103,104……第２のフレーム同期回路。FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of a conventional frame synchronization circuit. 101: first frame synchronization circuit, 102: separation circuit,
103, 104... Second frame synchronization circuit.
Claims (1)
号に補助信号を多重化した多重化信号の同期確認を行う
フレーム同期回路において、前記多重化信号のフレーム
同期を判定し第１の判定信号を出力する第１のフレーム
同期回路と、前記多重化信号から補助信号を分離する分
離化回路と、前記分離化回路で分離された補助信号と前
記第１の判定信号とを入力し、前記第１の判定信号が同
期外れの判定結果を出力した場合には、通常行われてい
る補助信号の同期判定動作を中止して同期外れを報知す
る第２の判定信号を出力する第２のフレーム同期回路と
を有することを特徴とするフレーム同期回路。1. A frame synchronization circuit for confirming synchronization of a multiplexed signal obtained by multiplexing an auxiliary signal with a digital signal in wireless digital transmission, wherein a frame synchronization of the multiplexed signal is determined and a first determination signal is output. A frame synchronization circuit, a separation circuit for separating an auxiliary signal from the multiplexed signal, an auxiliary signal separated by the separation circuit and the first determination signal, and a first determination signal A second frame synchronization circuit that outputs a second determination signal for notifying the out-of-synchronization by suspending the synchronization determination operation of the auxiliary signal that is normally performed when the out-of-synchronization determination result is output. A frame synchronization circuit characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2213882A JP2576274B2 (en) | 1990-08-13 | 1990-08-13 | Frame synchronization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2213882A JP2576274B2 (en) | 1990-08-13 | 1990-08-13 | Frame synchronization circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0496536A JPH0496536A (en) | 1992-03-27 |
| JP2576274B2 true JP2576274B2 (en) | 1997-01-29 |
Family
ID=16646583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2213882A Expired - Fee Related JP2576274B2 (en) | 1990-08-13 | 1990-08-13 | Frame synchronization circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2576274B2 (en) |
-
1990
- 1990-08-13 JP JP2213882A patent/JP2576274B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0496536A (en) | 1992-03-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |