JP2572458Y2 - Shock noise reduction circuit - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shock noise reduction circuit, and more particularly to a shock noise reduction circuit suitable for reducing shock noise due to irregular time constants generated when power is turned on.

[0002]

2. Description of the Related Art Conventional shock noise reduction circuits include:
For example, the one shown in FIG. 3 has been provided.

In FIG. 1, reference numeral 1 denotes an amplifier, R _{1 to} R ₆ are resistors, and C _{1 to} C ₄ are capacitors.

[0004] The non-inverting input terminal of amplifier 1 as a configuration of the circuit is connected to the INPUT terminal through a capacitor C _1, further comprising: a resistor R ₂ and the resistor R ₃ in order to apply a bias voltage + power supply and to earth resistor R ₄ from the connection point between the connected resistor R ₂ and the resistor R ₃ are capacitor C ₂ is connected between the connected to the non-inverting input terminal of the amplifier 1 grounded.

Power is supplied to the amplifier 1 via a decoupling circuit including a resistor R ₁ and a capacitor C ₃ .

[0006] The output of the amplifier 1 is fed back via a resistor R ₅ to the inverting input terminal of the amplifier 1, further, a resistor R ₆ and the capacitor C ₄ of the DC cut is grounded is connected in series to the inverting input terminal ing.

When the power supply is turned on, the single power supply amplifier circuit configured as described above operates as follows. When the power supply is turned on, the bias circuit including the resistors R ₂ , R ₃ , R ₄ and the capacitor C ₂ is connected to the resistor R ₂ . the non-inverting but applied to the input terminals other resistors R ₁ of the capacitor C ₂ and the amplifier bias potential via a capacitor C ₂ is charged resistor R ₄ with a time constant by 1, the capacitor C ₃ and resistor R _6, a capacitor C ₄ Since the speed up to the establishment of the potential differs depending on the time constant, a shock noise as shown in FIG.

In order to reduce the above-mentioned shock noise, the timing is set so that the shock noise is minimized by changing the constant of each resistor and capacitor.

[0009]

But [devised It is an object of the husband in the conventional single-supply amplifier circuit, the resistance value near to charge the capacitance value and the potential to that of the capacitor C ₁ -C ₄ when the power is turned on as shown in FIG. 3 s Since the speeds at which the potentials reach the potentials are different, a shock noise as shown in FIG. 4 is generated from the output of the amplifier 1, and it is difficult to determine a constant for taking the timing of the rise of each potential to reduce the shock noise. However, there is a drawback that the variation of the shock noise occurs due to the variation of the constant of each component.

The present invention has been made in view of the above points, and has as its object to solve the drawbacks of the prior art and to improve the shock noise due to the troublesome setting of the constant and the variation in the constant. It is to provide a noise reduction circuit.

[0011]

A shock noise reduction circuit according to the present invention comprises a bias circuit for a first input terminal and a second input terminal.
The decoupling circuit between the input terminal bias circuit and the power supply
In a single-supply amplifier operating on a single power supply having a coupling circuit , one end is connected to a power supply and the other end is a capacitor.
The bias circuit of the first input terminal grounded through
A transistor having a collector and an emitter connected to both ends of a resistor to be formed, a capacitor connected to a power supply at the base of the transistor, and a circuit connected to a resistor between the emitter and the emitter. With the transistor turned on, the bias potential of only the first input terminal is immediately increased in the power supply voltage direction, and the decoupling is performed.
Time constants of the bias circuit and the bias circuit of the second input terminal.
By setting to a fixed value, the voltage of each terminal of the amplifier can be confirmed.
In the meantime, the voltage of the second input terminal of the amplifier becomes
It is configured to be lower than the voltage of the first input terminal .

[0012]

According to the invention, the bias of the first input terminal is provided.
Between the circuit, the bias circuit of the second input terminal, and the power supply
A single power supply amplifier having a decoupling circuit provided at a single power supply and having one end connected to a power supply and the other end connected to a power supply.
Is the bypass of the first input terminal that is grounded via the capacitor.
A transistor having a collector and an emitter connected to both ends of a resistor constituting a ground circuit, a capacitor connected to a power supply at a base of the transistor, and a circuit connected to a resistor between the emitter and a power supply are provided. the transistor is turned oN at the time of turn-on, both when pulling a bias potential only the first input terminal to quickly supply voltage direction, the
Decoupling circuit and bias circuit for second input terminal
By setting the time constant of
A second input of the amplifier until the voltage of the
Since the voltage at the terminal is lower than the voltage at the first input terminal ,
It is possible to reduce shock noise caused by irregularity in the speed of increasing the potential of the resistance value and the capacitance value constituting the amplifier when the power is turned on.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a shock noise reduction circuit according to the present invention will be described with reference to FIGS.

The same parts as those in the conventional example are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram showing shock noise.

In the figure, Q ₁ is a transistor, R ₇ is a resistor, and C ₅ is a capacitor.

[0017] The + power source side end of the resistor R ₂ is a configuration of the circuit, the collector of the transistor Q ₁ is connected resistors R
The ₂ on the other end and the resistor R ₇ between the capacitor C ₅ to the base is connected to the + power source of the transistor to Q ₁ transistor Q ₁ and the emitter is connected emitters are connected.

The base potential of the power source is turned on the transistor Q ₁ is as an operation of the circuit configured as described above applied the potential of through the + power capacitor C _5, the transistor Q ₁ is rendered conductive a resistor R ₂ are short-circuited.

Therefore, the capacitor C ₂ is forcibly charged to the + power supply potential immediately and raises the potential of the non-inverting input terminal of the amplifier 1 to the + power supply potential via the resistor R _4. Operates only in the plus direction, and the waveform of the shock noise occurs only in the plus direction as shown by the solid line in FIG.

In order to lower the level of the shock noise, the power supply voltage of the amplifier 1 is slowly raised by changing the time constant of the resistor R ₁ and the capacitor C ₃ , as shown by a dotted line in FIG. Level.

According to the circuit configured as described above,
The constant setting for taking the timing at power-on
Since it can be performed without affecting the performance, circuit design can be easily performed.
Shock noise due to variations in component constants
Raw variability can be reduced.

[0022]

[Effect of the invention] The shock noise reduction circuit according to the invention
According to the configuration described above, there is an effect that a circuit design for obtaining a timing at the time of power-on can be easily designed .

[0023]

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram showing shock noise.

FIG. 3 is a circuit diagram of a conventional example.

FIG. 4 is a waveform diagram of a shock noise generated from a conventional circuit diagram.

[Explanation of symbols]

1 amplifier Q ₁ transistor R ₁ to R ₇ resistor C ₁ -C ₅ capacitor

Claims (1)

(57) [Scope of request for utility model registration] A first input terminal bias circuit; a second input terminal bias circuit;
The decoupling circuit between the input terminal bias circuit and the power supply
In a single-supply amplifier operating on a single power supply having a coupling circuit , one end is connected to a power supply and the other end is grounded via a capacitor.
A transistor having a collector and an emitter connected to both ends of a resistor constituting a bias circuit of a first input terminal, a capacitor connected to a power supply at a base of the transistor, and a resistor connected between the emitter and the emitter. And the transistor is turned on when the power is turned on.
The bias potential of only the first input terminal is quickly raised in the direction of the power supply voltage , and the decoupling circuit and the second
Set the time constant of the bias circuit of the input terminal to a predetermined value
This allows the voltage at each terminal of the amplifier to
While the voltage at the second input terminal of the amplifier is at the first input terminal
A shock noise reduction circuit, which is configured to be lower than a voltage of a child .