JP2570030B2 - Color signal demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color signal demodulator for demodulating a carrier color signal of an NTSC television signal into a color difference signal.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a configuration of a conventional color signal demodulator. In FIG. 5, 1 is NTSC
It is an input terminal for a carrier color signal (hereinafter abbreviated as C signal) of a television signal, and is hereinafter referred to as a C signal input terminal.
This signal input terminal 1 is grounded through an amplitude adjustment volume 11.

A C signal input to the C signal input terminal 1 is passed through an amplitude adjustment volume 11 to a PLL (Phase Locked Loop) clock generator 2 as a clock generator and an analog / digital (hereinafter, A / D) converter 3.
To be entered.

The PLL clock generator 2 has a continuous signal wave f _sc 7 and a continuous signal wave 2 f phase-locked to the burst of the C signal.
_sc 8 and a continuous signal wave 4f _sc 9 are respectively output. The continuous signal wave 4f _sc 9 is input to the A / D converter 3 as a clock, and the continuous signal wave
f _sc 8 is input as a B (blue) / R (red) identification signal as a clock for the latch 6 via the latch 5 and the inverter 15. Continuous signal wave f _sc
7 is input to the encoding device 4.

[0005] The output of the A / D converter 3 is output to the encoding device 4 as n-bit data.
The output of the encoding device 4 is sent to the latches 5 and 6 as input data of the latches 5 and 6.
The output of the latch 5 is a BY output, and the output of the latch 6 is an RY output, which are final outputs. Reference numeral 10 denotes a PLL lock angle adjustment volume.
The lock phase of the LL clock generator 2 is adjusted. 12 is a unit.

Next, the operation will be described. The C signal of the NTSC television signal is composed of color difference signals RY and BY.
Are modulated by the following equation (1). C = In (R-Y) × cos ( 2πf SC t) + (B-Y) × sin (2πf SC t) ... (1) Equation (1), f _sc is a color subcarrier, 3.579
545 MHz.

FIG. 6A shows an input waveform diagram in which the color difference data represented by the respective functions of cos and sin are synthesized. Now, the phase of the continuous wave signal 4f _sc 9 serving as the clock of the A / D converter 3, the continuous wave signal f _sc 7 serving as the code signal of the encoder 4, and the continuous wave signal 2f _sc 8 serving as the B / R identification signal are obtained. By appropriately determining each phase with the PLL lock angle adjustment volume 10, a of FIG.
The output data of the A / D converter 3 at the point is (RY) itself, the data at the point c is-(RY), the data at the point b is (BY) itself, and d Point data is-
(BY).

[0008] When the output data of the A / D converter 3 is input to the encoding device 4, the encoding device 4 performs decoding using a continuous wave signal f _sc 7 which is a code signal. The signal decoded by the encoding device 4 is output to the latches 5 and 6, and the continuous wave signal 2 as the identification signal input to the latches 5 and 6
The f _sc 8, by latching alternately latch 5,6, demodulation waveform shown in FIG. 6 (b), i.e., (B-
Output signals 13 and 14 of (Y) and (RY) are obtained, and their combined vectors are as shown in FIG.

The output signals 13,
Since the amplitude of the signal 14 varies depending on the amplitude level of the C signal, the amplitude adjustment volume 11 is adjusted for each input C signal.

[0010]

Since the conventional chrominance signal demodulator is constructed as described above, the phase is adjusted by the PLL lock angle adjustment volume 10 and the amplitude of the C signal is adjusted by the amplitude adjustment volume 11. Must be done, which is troublesome. In addition, adjustment jigs are required and costly, and thus have become a major obstacle in manufacturing. Further, even after the adjustment is once completed, there is a problem that an external factor such as a temperature shows a temporal change.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to operate without adjustment, to obtain high-precision demodulation even with disturbances, and to eliminate the need for an adjusting jig. An object of the present invention is to provide a color signal demodulation device that can be expected to reduce costs.

[0012]

A chrominance signal demodulator according to the present invention comprises a continuous wave signal which is input with a carrier chrominance signal of an NTSC television signal and is phase-locked to a burst signal; A clock generator for generating a multiplied continuous wave signal, a coding device for performing code conversion of a carrier chrominance signal into a continuous wave signal phase-locked to a burst signal, and a continuous wave signal obtained by multiplying the signal of the code conversion device by two. Two first latch means for latching at different timings, and
Two second latch means for latching a portion corresponding to the burst of the output of the first latch means, and outputs A and B of the first latch means and outputs a and b of the second latch means are inputted. And an arithmetic unit that outputs X and Y from the arithmetic result of Formula 1.

[0013]

A clock generator according to the present invention receives a carrier color signal of an NTSC television signal, locks the phase with a burst signal, and outputs a continuous wave signal and a double or quadruple continuous wave signal. A code converter converts and decodes the color signal based on the continuous wave signal obtained by phase-locking the color signal to the burst signal, and converts the code-converted signal into two first latch means at a timing of a doubled continuous wave signal. And the burst equivalent portion of the output of the first latch means is
And the outputs of the first latch means are A and B, and the outputs of the second latch means are a and b. (R
−Y) and (B−Y) are obtained.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a color signal demodulator according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment. In FIG. 1, portions denoted by reference numerals 1, 13, and 14 are the same as those in the conventional example of FIG.

The portion indicated by reference numeral 12 in FIG.
This is the unit shown in FIG. This unit 12 is shown in FIG.
In FIG. 1, the outputs 13 and 14 are the uncorrected color differences output from the unit 12 because the internal configuration of the unit is the same as that of FIG. 5 except for the amplitude adjustment volume 11 and the PLL clock angle adjustment volume 10. A signal is partially held by latches 32 and 33 as latch means by a burst extraction pulse 20.

The unit 60 receives the outputs 13 and 14 of the unit 12 and the outputs 33 and 34 of the latches 31 and 32 and performs calculations of the following equations (2) and (3).

Output 61 = − (Signal 33) × (Signal 13) − (Signal 34) × (Signal 14)... (2) Output 62 = (Signal 34) × (Signal 13) − (Signal 33) × (Signal 14)… (3)

The internal structure of the unit 60 is shown in FIG. That is, FIG. 2 is a block diagram showing a detailed configuration of this embodiment. In FIG. 2, the description of the same components as those in FIG. 1 will be omitted, and the configuration of the unit 6 will be described.

In FIG. 2, the output 33 of the latch 31 is output to multipliers 40 and 43 via a complementer 35, and the output 34 of the latch 32 is similarly output via a complementer 36 Output to the multiplier 41 and output directly to the multiplier 42.

The multiplier 40 multiplies the output 33 of the unit 13 by the output 33 of the latch 31 through the complementer 35, and sends the output to the adder 50. The multiplier 41 multiplies the output 12 of the unit 12 by the output 34 of the latch 32 through the complementer 36 to obtain an output of 50.
To be sent.

The multiplier 42 multiplies the output 13 of the unit 12 by the output of the latch 32 and sends the output to the adder 51. Multiplier 43 is unit 12
And the output 33 of the latch 31 through the complementer 35
, And outputs the output to the adder 51.

The adder 50 adds the outputs of the multipliers 40 and 41 to obtain an output 61. Similarly, the adder 51 adds the outputs of the multipliers 42 and 43 to obtain an output 62. The outputs of the adders 61 and 62 are output to the unit 80 of FIG.

Here, the description returns to FIG. The unit 70 in FIG.
Is input, the following equation 2 is calculated, and the signal 71 is output to the unit 80.

[0024]

(Signal 71) = (signal 33) ² + (signal 34) ²

The unit 80 receives the outputs 61 and 62 of the unit 60 and the signal 71 of the unit 70,
By calculating the following equations (4) and (5), the signal 81 (B
−Y) and an arithmetic unit that outputs a signal 82 (R−Y).

(Signal 81) = (signal 61) / (signal 71) (4) (signal 82) = (signal 62) / (signal 71) (5)

Thus, the unit 90 is constituted by the units 60, 70, and 80, and is configured to obtain a corrected color difference signal from the unit 90.

Next, the operation will be described with reference to the color difference signal correction vector diagram of FIG. Now, C signal input terminal 1
Is represented by a vector A shown in FIG.
It is assumed that the burst signal is the vector B shown in FIG.
Originally, since the (RY) component of the burst is 0, in FIG. 3, the PLL lock angle is shifted, and the burst rotates by θ, and appears at the outputs 13 and 14 of the unit 12. As a result, the unit 12 outputs the burst components B _ba and B _ra and the components A _ba and A _{ra of} the C signal A.

As described above, since the (RY) component is originally 0 in the burst, the correct color difference component of the C signal A is (A _bb , A _rb ). In order to obtain this signal, the following equation 4 may be finally calculated. In order to perform the calculation of the equation 4, the following process is performed.

That is, the original burst positions are B _bb = cos π = −1, B _rb = sin π = 0 (6) Since the burst is observed rotated by θ, B _ba = -cos theta, a _{B ra = -sin θ ... (7} ), the color difference value of the correct C signal a, it is sufficient correction rotated by - [theta], to obtain the calculation of the number 3.

[0031]

(Equation 3)

Further, since the components A _ba and A _ra and the burst components B _ba and _Bra of the C signal A are obtained from the unit 12 as data, the above equation (7) is substituted into the equation (3) to obtain the equation (4). Is obtained.

[0033]

(Equation 4)

As a verification of the above equation (5), if equation (4) is substituted into equation (5), it can be confirmed from the fact that equation (2) matches. Further, the implementation example of the expression (6) is the unit 60 in FIG.
become. The variables in Equation 4 correspond to the following equations (8) to (13).

Signal (13) = A _ba (8) Signal (14) = A _ra (9) Signal (33) = B _ba (10) Signal (34) = B _ra (11) Signal (61) ) = A _bb (12) Signal (62) = A _rb (13)

That is, a circuit for realizing the relations of the above equations (2) and (3) from the equations (4), (8) to (13) is a unit 60, and this unit 60 is a circuit shown in FIG. As shown, four multipliers 40 to 43 and two adders 5
0, 51, and two complementers 35, 36.

Here, consider the case where the level of the C signal changes. Consider the case where | B | = | αB _N | and | A | = | αA _N | in the color difference signal correction vector diagram of FIG. B _N and A _N are reference levels, each of which has a variation of α times, and the color difference components are B = (αB _Nba , αB _Nra ), A = (αA _Nba , αA _Nra ) (14) ).

Here, substituting equation (14) into equation (4) gives
The output of the unit 60 is as shown in the following Expression 5.

[0039]

(Equation 5)

Therefore, in order to add the level correction of the color difference signal, it suffices to divide each of the signals 61 and 62 by the square of α.

On the other hand, considering only the burst component,
The following equation 6 is obtained.

[0042]

(Equation 6)

Since B _N is a reference burst signal, its magnitude is 1, so the parentheses on the right side of Equation 6 are as shown in Equation 7 below.

[0044]

[ _Formula 7] B _Nba ² + B _Nra ² = 1

Therefore, the following equation (8) is obtained from the equation (7).

[0046]

Α ² = B _ba ² + B _Nra ²

As described above, the standardized color signal A _N is obtained by the following equation (9).

[0048]

(Equation 9)

The following equation 10 in the above equations 6 to 9 is calculated by the unit 70, and the output signal 71 output from the unit 70 is the calculation result. The unit 80 is a unit that divides the output signals 61 and 62 of the unit 60 by the output signal 71 of the unit 70, respectively, and thus can obtain the signals 81 and 82, that is, the color difference signals corrected in both phase and level. .

[0050]

## _EQU10 ## B _ba ² + B _ra ²

In the above embodiment, the units 60 are the complementers 35 and 36, the multipliers 40 to 43, and the adder 5
Although the case where a plurality is used as shown in FIGS. 0 and 51 has been described as an example, in order to reduce the circuit scale, for example, as shown in FIG.

That is, the latch 31 via the complementer 35
The output 101 of the latch 32 and the output 34 of the latch 32 are switched by the output of the time-division controller 100 to switch 101.
In addition to the switching input, the switch 102 is switched by the output of the time division controller 100, and the output of the complementer 35 or the output of the complementer 36 is switched and input to the multiplier 41. Further, the time division controller 1
The output of the adder 50 is latched by latches 55 and 56 as latch means in accordance with the output of the adder 50. Outputs 60 and 61 from the latches 55 and 56 are shown in FIG.
Is sent to the unit 80 shown in FIG. With such a configuration, the switches 101 and 102 are generally smaller in circuit scale than the respective circuits, which is advantageous in terms of product cost.

Further, in the above embodiment, the case of digital signal processing has been described, but analog signal processing is also possible. For example, the A / D converter 3 and the latches 5 and 6 are used as sample-and-hold circuits.
By replacing the adders 50 and 51 and the adders 50 and 51 with an operational amplifier or the like as they are, it is easy to perform the same operation as in the above embodiment.

[0054]

As described above, according to the present invention, the continuous signal wave phase-locked to the burst signal by the clock signal generator and the continuous wave signal of 2 times and 4 times thereof are generated, and the carrier color signal is generated. Code conversion is performed on the basis of the continuous wave signal phase-locked to the burst signal, and the output of the first latch means is latched by the two first latch means at different timings with the output of the continuous wave signal doubled. The portion corresponding to the burst is latched by the two second-stage latch units, and the operation of Expression 1 is performed by the arithmetic unit from the outputs A and B of the first latch unit and the outputs a and b of the second latch unit. Is obtained so as to obtain the (RY) and (BY) color difference signals of the calculation results X and Y, so that the lock phase angle of the clock generator and the level of the carrier color signal can be obtained from the burst signal regardless of the level. A correct color difference demodulated signal is obtained. It is.

Further, not only is the adjustment unnecessary, but also with respect to disturbances, the accuracy is high, and the addition of correction means is generally realized by using an IC as a whole. No amplitude adjustment volume and PLL
Since the lock angle adjustment volume can be removed, there is an effect that the number of adjustment steps can be reduced and an adjustment jig is not required.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a color signal demodulation device according to one embodiment of the present invention.

FIG. 2 is a block diagram showing an entire configuration in detail showing an internal configuration of a unit in the embodiment.

FIG. 3 is a color difference signal correction vector diagram for explaining the embodiment.

FIG. 4 is a block diagram showing a configuration of a unit portion in another embodiment of the color signal demodulation device of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a conventional color signal demodulation device.

FIG. 6 is a conceptual diagram of color signal demodulation for explaining the operation of a conventional color signal demodulation device.

[Explanation of symbols]

 2 PLL clock generator 3 A / D converter 4 Encoder 5 Latch 6 Latch 12 Unit 15 Inverter 31 Latch 32 Latch 35 Complement 36 Complement 40 Multiplier 41 Multiplier 42 Multiplier 43 Multiplier 50 Adder 51 Adder 60 unit 70 unit 80 unit 90 unit 100 time division controller 101 switch 102 switch

Claims (1)

(57) [Claims] A clock signal generator for receiving a carrier color signal of an NTSC television signal and generating a continuous wave signal whose phase is locked to a burst signal, a double continuous wave signal, and a quadruple continuous wave signal thereof; An encoding device for performing code conversion based on a continuous wave signal obtained by phase-locking the carrier chrominance signal to the burst signal, and an output of the encoding device
Two first latch means for latching at different timings based on the multiplied continuous wave signal, second latch means for latching a burst-equivalent portion of the output of the first latch means; The outputs A and B of the latch means and the outputs a and b of the second latch means are inputted, and A color signal demodulation device comprising: a calculation device that outputs the calculation results X and Y.