JP2001346221A - Video encoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video encoder capable of suppressing the capacity of a memory required for generation of a chrominance subcarrier from being increased, dealing with color television systems and eliminating the shift of an SCH phase. SOLUTION: In the case that shifting an address given to a ROM 2 synchronously with a clock signal of primary color signals R, G, B uses a signal read from the ROM 2 for a chrominance subcarrier, number of shifts from an address having been given just before an address going to be given to the ROM 2 at an interval of one horizontal scanning period is corrected depending on an error between actual number of shifts and number of shifts when the frequency of the signal read from the ROM 2 is equal to the frequency of the chrominance subcarrier with respect to number of shifts for one horizontal scanning period of an address given to the ROM 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a video encoder for generating a video signal from a digital primary color signal.

[0002]

2. Description of the Related Art In a video encoder, three signals of a luminance signal, a carrier chrominance signal (chroma signal), and a composite color video signal (composite signal) are generally generated from red, green, and blue primary color signals. I do. In the case of the NTSC system, the following relationship exists between the primary color signals R, G, and B, and the luminance signal Y and the carrier color signal C.

[0003] Y = 0.299 R + 0.587 G + 0.144 BC C = {(RY) /1.14} .cos (ωt) +
{(B−Y) /2.08} · sin (ωt) where ω = 2πf, where f _SC is the frequency of the color subcarrier.
_SC . In the case of the NTSC system, f _SC = 3.5
79545 [MHz].

Therefore, in order to generate the carrier chrominance signal C, two color sub-carriers sin (ω
t) and cos (ωt) are required, but the primary color signals R,
When G and B are digital signals, sin (ωt)
And the value of cos (ωt) are stored in the memory in association with the address for each predetermined phase, and the address to be read out is read out from the memory while being shifted in synchronization with the clock signal of the primary color signal, so that the two color Carrier sin
(Ωt) and cos (ωt).

Here, sin (ω) to be stored in the memory
How to determine the values of t) and cos (ωt) will be described. Assuming that the number of bits of the address in the memory is ⁿ , the number of addresses of the memory is 2 ⁿ , so s
Regarding in (ωt) and cos (ωt), values at 0 [deg], values at (1/2 ⁿ ) · 360 [deg], (2/2 ⁿ )
・ Value at 360 [deg], ..., {(2 ⁿ -1) / 2 ⁿ } 3
The values at 60 [deg] are stored at addresses 0, 1, and
2,..., 2 ⁿ -1.

If the address is shifted by a number corresponding to one cycle of the clock signal in synchronization with the clock signal, two color subcarriers sin (ωt) and cos whose phases are shifted by 90 ° from the memory. (Ωt) is output. The address shift number IS corresponding to one cycle of the clock signal is IS = (f _SC / f _CLK ) · 2 ⁿ with respect to the frequency f _{CLK of the} clock signal.

For example, when a memory address is 10 bits, as shown in FIG. 4A, the phase of each of a sine wave A and a cos wave B having an amplitude of 1 is changed from 0 to ( As shown in (b) of FIG. 4, values every 1/2 ¹⁰ ) · 360 [deg] are stored in the memory in order from address 0.

The frequency f _{CLK of the} clock signal is f = 1
3.5 [MHz], NTSC system (color subcarrier frequency f _SC =
3.579545 [MHz]), and if the operation of shifting the address is performed with the same 10 bits as the address of the memory, the number of address shifts S is calculated by the theoretical value I
Since S is given by IS = (3.579545 / 13.5) · 2 ¹⁰ = 271.515117..., The theoretical value IS may be set to a value obtained by rounding off the decimal point, that is, S = 272. You should keep it.

In this method, the frequency of a signal read from the memory can be adjusted by changing the number of address shifts, so that the capacity of the memory can be suppressed and the NTSC, PAL, PAL can be adjusted. −M,
There is an advantage that it is possible to cope with a plurality of television systems having different frequencies of color subcarriers such as PAL-N.

[0010]

However, since the number of address shifts is an approximate value obtained by truncating the decimal part of the theoretical value, the frequency of the signal generated as the chrominance subcarrier has an error with respect to the theoretical value. Have. For this reason, there has been a problem that the SCH phase (which means the positional relationship between the horizontal synchronization signal and the zero cross point of the color subcarrier in the NTSC system) is shifted.

Therefore, the present invention can cope with a plurality of color television systems while suppressing an increase in the memory capacity required for generating color subcarriers, and
An object of the present invention is to provide a video encoder capable of eliminating a CH phase shift.

[0012]

In order to achieve the above object, according to the present invention, a color difference signal generating means for generating a color difference signal from a primary color signal, and an address which is shifted by a predetermined number in synchronization with a clock signal are generated. Address generating means, storing means for storing values at a plurality of phases of the sine wave, outputting the value stored at the address generated by the address generating means, and generating the color difference signal generated by the color difference signal generating means. And a multiplication unit for multiplying the color difference signal and the signal output from the storage unit, wherein the number of shifts of the address generated by the address generation unit in one horizontal scanning period; Of the address given to the storage means when the frequency of the signal output from
Means is provided for correcting the number of address shifts in the address generation means so that an error from the number of shifts in the horizontal scanning period is reduced.

With this configuration, depending on the relationship between the frequency of the clock signal and the frequency in one horizontal scanning period, and the relationship between the frequency of the color subcarrier, the frequency in one horizontal scanning period, and the number of bits of the operation for shifting the address. When viewed every other horizontal scanning period, the error between the frequency of the signal output from the storage means and the frequency of the color subcarrier can be made zero.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a video encoder according to an embodiment of the present invention. The luminance / color difference signal generation circuit 1 converts a luminance signal Y and a color difference signal RY, from primary color signals R, G, and B, which are 8-bit digital signals.
Generate BY. The color difference signals RY and BY generated by the luminance / color difference signal generation circuit 1 have amplitudes of 1 /
It is limited to 1.14, 1 / 2.08. In the present embodiment, the frequency of the clock signals of the primary color signals R, G, and B is 13.5 [MHz].

The ROM 2 stores si signals each having an amplitude of 1.
The values of the predetermined phases of the n-wave and the cos-wave are stored as a sin value and a cos value, respectively, after associating the phase with the address, and stored at the address given from the address operation circuit 3. The value and the cos value are output from terminals O1 and O2, respectively.

The address arithmetic circuit 3 calculates a value obtained when a sine wave and a cosine wave having the frequency of the color subcarrier in the selected color television system are sampled at the frequency of the clock signal. O
2 is given an address to the ROM 2 so as to be output from the ROM 2 respectively. The address calculation circuit 3 receives the select signal Se and recognizes the selected color television system by the select signal Se.

As a result, the signal output from the terminal O1 of the ROM 2 and the signal output from the terminal O2 become two color subcarriers whose phases are shifted by 90 °. Then, the signal output from the terminal O1 of the ROM 2 is multiplied by the multiplication circuit 4 with the color difference signal BY output from the luminance / color difference signal generation circuit 1. On the other hand, the terminal O of the ROM 2
The signal output from 2 is multiplied by the multiplication circuit 5 with the color difference signal RY output from the luminance / color difference signal generation circuit 1.

However, as for the signal output from the terminal O2 of the ROM 2, when generating an NTSC video signal, the switch 6 is fixed to the terminal a side. When a PAL video signal is generated, the switch 6 is alternately switched between the terminal a and the terminal b every horizontal scanning period. The signal is input to the multiplication circuit 5 via the circuit 7, that is, the polarity is inverted every horizontal scanning period before being input to the multiplication circuit 5.

The addition circuit 8 adds the signal obtained by the multiplication circuit 4 and the signal obtained by the multiplication circuit 5. As a result, a carrier color signal C corresponding to the selected color television system is generated. The burst sampling circuit 9
The signal output from the terminal O1 of the ROM 2 is inverted
, And the input signal is extracted at a predetermined position. The signal extracted by the burst extraction circuit 9 is inserted by the addition circuit 11 into the back porch of the carrier chrominance signal C as a color burst.

The luminance signal Y generated by the luminance / color difference signal generating circuit 1 is added to a composite synchronizing signal SYC composed of various synchronizing signals such as a horizontal synchronizing signal and a vertical synchronizing signal by an adding circuit 12. The carrier chrominance signal C obtained by the addition circuit 11 and the luminance signal Y obtained by the addition circuit 12 are added by the addition circuit 13. As a result, a composite color video signal V is generated.

Hereinafter, the ROM 2 and the address arithmetic circuit 3 will be described in more detail. In the present embodiment, RO
The address of M2 is 10 bits, and as described above (see FIG. 4), the address 0 is used as the sin value and the cos value.
, 0, 1, ..., address 256, 1, 0, ...,
The address 512 stores 0, -1,..., And the address 768 stores -1, 0,.

The address operation circuit 3 performs an operation with a larger number of bits than the address of the ROM 2, and converts the operation result into the number of bits of the address of the ROM 2.
An address to be given to the ROM 2 is obtained. In this embodiment, the operation is performed with 20 bits, and the operation result is converted into 10 bits.

FIG. 2 shows the internal configuration of the address arithmetic circuit 3. The addition value setting circuit 31 recognizes the selected color television system by the select signal Se, and usually,
The shift value corresponding to the selected color television system is output.

The address operation circuit 3 applies a value obtained by adding the first correction value to the shift value in synchronization with a pulse appearing every other horizontal scanning period in a clock signal having a frequency of 13.5 [MHz]. Output instead of the value. Specifically, for example, after the trigger edge of the pulse included at the end of one horizontal scanning period among the pulses of the clock signal CLK of the flip-flop circuit 33 described later, for the second in the next one horizontal scanning period Only before the trigger edge of the included pulse, a value obtained by adding the first correction value to the shift value is output instead of the shift value.

Further, when the PAL system or the PAL-N system is selected, the address arithmetic circuit 3
A value obtained by adding the first correction value and the second correction value to the shift value,
It is output in place of a shift value in synchronization with a pulse appearing every other frame in a clock signal having a frequency of 13.5 [MHz]. Specifically, for example, of the pulses of the clock signal CLK of the flip-flop circuit 33 described later, after the trigger edge of the pulse included at the end of one frame, the pulse included in the second pulse of the next one frame Only before the trigger edge, a value obtained by adding the first correction value and the second correction value to the shift value is output instead of the shift value.

The adder 32 outputs the output (20 bits) of the addition value setting circuit 31 and the output (2
0 bit) and outputs the addition result in 20 bits. The addition circuit 32 ignores overflow, and performs addition. When the addition result is 1048576 (= 2 ²⁰ ) or more, the addition circuit 32 subtracts 1048576 from the addition result. Is output.

The output (20 bits) of the adding circuit 32 is input to the flip-flop 33. The flip-flop 33 operates in synchronization with a clock signal CLK having a frequency of 13.5 [MHz]. Therefore, the value output from flip-flop circuit 33 increases by the value output from addition value setting circuit 31 in synchronization with clock signal CLK. The conversion circuit 34 converts the output (20 bits) of the flip-flop circuit 33 into 1024 by dividing the output (1024 bits) into 10 bits and outputs the result. The output of the conversion circuit 34 is stored in the ROM 2
Is given as an address.

As described above, the operation of shifting the address given to the ROM 2 storing the sin value and the cos value is performed by R
By using a larger number of bits than the address of the OM2, the error included in the number of address shifts is reduced, so that a more accurate color subcarrier can be generated.

The shift value, the first correction value, and the second correction value in the addition value setting circuit 31 will be described. First,
The shift value is a theoretical shift number (that is, a number by which an address given to the ROM 2 should be shifted each time in synchronization with a clock signal in order to make the frequency of the signal output from the ROM 2 the frequency of the color subcarrier). ) Is rounded down to the decimal point. Note that the theoretical shift number IS is IS = (f _SC , with respect to the frequency f _SC of the color subcarrier, the frequency f _{CLK of the} clock signal, and the number of operation bits n.
/ _FCLK ) ²ⁿ .

That is, in the present embodiment, since the frequency f _{CLK of the} clock signal is 13.5 [MHz] and the number of operation bits is n = 20, the NTSC system (frequency f _{SC of the} color subcarrier =
When 3.579545 [MHz] is selected, IS = (3.579545 / 13.5) · 2 ²⁰ = 278031.4798..., And the shift value S is S = 278031.

The PAL system (f _SC = 4.44331)
875 [MHz]), IS = (4.43361875 / 13.5) · 2 ²⁰ = 344369.3492..., And the shift value S is S = 344369.

The PAL-M system (f _SC = 3.575)
When 61149 [MHz] is selected, since IS = (3.57561149 / 13.5) · 2 ²⁰ = 277725.955..., The shift value S is S = 277726.

The PAL-N system (f _SC = 3.582)
If 05625 [MHz]) is selected, then IS = (3.5820625 / 13.5) · 2 ²⁰ = 2782266.5344..., And the shift value S is S = 278227.

Here, the error E _WN between the wave number of the signal output from the ROM 2 during one horizontal scanning period and the wave number of the color subcarrier included in one horizontal scanning period is the frequency f of the horizontal synchronizing signal.
_H, the color subcarrier frequency f _SC, the signal output from the ROM 2 'with respect to, E _WN = f _SC' frequency f _SC is a _{/ f H -f SC / f H} .

The signal f _SC ′ output from the ROM 2 is f _SC ′ = (S / 2 ²⁰ ) with respect to the shift value S output from the addition value setting circuit 31 and the frequency f _{CLK of the} clock signal. -F _CLK .

Therefore, the number of addresses E _ADRS corresponding to the error E _WN (hereinafter, referred to as “address error in one horizontal scanning period”) is E _ADRS = E _WN · 2 ²⁰ , so that E _ADRS = _{(f SC '/ f H -f} SC / f H) · 2 20 = S · (f CLK / f H) - a _{(f SC / f H) ·} 2 20.

In the NTSC system, since S = 278031 f _CLK / f _H = 858 f _SC / f _H = 227.5, E _ADRS = −442.

In the PAL system, S = 344369 f _CLK / f _H = 864 f _SC / f _H = 283.7516, so that E _ADRS = −301.7216.

In the PAL-M system, since S = 277726 f _CLK / f _H = 858 f _SC / f _H = 227.25, E _ADRS = 13.

In the PAL-N system, since S = 278227 f _CLK / f _H = 864 f _SC / f _H = 229.2516, E _ADRS = 402.2784.

The first correction value is set to a value obtained by inverting the sign of the address error E _ADRS in one horizontal scanning period and then rounding the absolute value. That is, N
When the TSC method is selected, the first correction value H
Becomes H = 442.

When the PAL system is selected, the first correction value H is H = 302.

When the PAL-M system is selected, the first correction value H is H = -13.

When the PAL-N system is selected, the first correction value H is H = -402.

As described above, when the NTSC system and the PAL-M system are selected, the RO when the frequency of the signal output from the ROM 2 becomes the frequency of the chrominance subcarrier is determined.
The address given to the ROM 2 shifts in one horizontal scanning period by the number of shifts of the address given to M2 in one horizontal scanning period, that is, the frequency of the signal output from the ROM 2 when viewed every other horizontal scanning period. And the frequency of the chrominance subcarrier is zero, which results in SC
H phase shift can be eliminated.

Here, assuming that the first correction value has an error (E _ADRS ) _H with respect to -E _ADRS (the result of inverting the sign of the address error E _ADRS during one horizontal scanning period), the value is given to the ROM 2. The address to be given is shifted by an error (E _ADRS ) _{H from the} address to be provided for each horizontal scanning period, so that the address stored in one frame is shifted (hereinafter referred to as “address error in one frame”). ) (E _ADRS ) _V is the frequency f _H during one horizontal scanning period,
For a frequency f _{V of} one frame, (E _ADRS ) _V = (E _ADRS ) _H · (f _H / f _V ).

In the NTSC system and the PAL-M system, since (E _ADRS ) _H = 0, (E _ADRS ) _V = 0.

In the PAL system, (E _ADRS ) _H = 302−301.7216 = 0.2784 f _H / f _V = 625, so that (E _ADRS ) _V = 0.2784 · 625 = 174.

In the PAL-N system, (E _ADRS ) _H = −402 − (− 402.2784) = 0.
Since 2784 f _H / f _V = 625, (E _ADRS ) _V = 0.2784 · 625 = 174.

The second correction value is set to a value obtained by inverting the sign of the address error (E _ADRS ) _V in one frame. That is, NTSC or PAL
When the −M method is selected, the second correction value V becomes V = 0.

When the PAL system or the PAL-N system is selected, the second correction value V becomes V = -174. FIG. 3 shows a table summarizing the relationship between the selected color television system, shift value, first correction value, and second correction value.

As described above, even when the PAL system or the PAL-N system is selected, the RO when the frequency of the signal output from the ROM 2 becomes the frequency of the chrominance subcarrier is obtained.
The address given to the ROM 2 shifts to one frame by the number of shifts of the address given to M2 in one frame.
The error between the frequency of the signal output from the OM2 and the frequency of the chrominance subcarrier becomes zero, thereby making it possible to eliminate the SCH phase shift.

[0053]

As described above, according to the present invention,
In a video encoder capable of coping with a plurality of color television systems while suppressing an increase in the memory capacity required for generating a color subcarrier, the frequency of a clock signal and the frequency of one horizontal scanning period And the relationship between the frequency of the color subcarrier, the frequency of one horizontal scanning period, and the number of bits of the operation for shifting the address, the data is read out from the memory when viewed every other horizontal scanning period. Since the error between the frequency of the signal generated as the color subcarrier and the frequency of the original color subcarrier can be made zero, it is possible to eliminate the SCH phase shift.

[Brief description of the drawings]

FIG. 1 is a block diagram of a video encoder according to an embodiment of the present invention.

FIG. 2 is a diagram showing an internal configuration of an address operation circuit.

FIG. 3 is a diagram showing a table summarizing a relationship among selected color television systems, shift values, first correction values, and second correction values.

FIG. 4 is a diagram for explaining contents stored in a memory (ROM).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Luminance / color difference signal generation circuit 2 ROM 3 Address calculation circuit 4 Multiplication circuit 5 Multiplication circuit 6 Switch 7 Inversion circuit 8 Addition circuit 9 Burst sampling circuit 10 Inversion circuit 11 Addition circuit 12 Addition circuit 13 Addition circuit 31 Addition value setting circuit 32 Addition Circuit 33 Flip-flop circuit 34 Conversion circuit

Claims (1)

[Claims] 1. A color difference signal generating means for generating a color difference signal from a primary color signal, an address generating means for generating an address shifted by a predetermined number in synchronization with a clock signal, and storing values at a plurality of phases of a sine wave. Storage means for outputting a value stored at an address generated by the address generation means, and a color difference signal generated by the color difference signal generation means multiplied by a signal output from the storage means. Wherein the number of shifts of the address generated by the address generating means in one horizontal scanning period and the frequency of the signal output from the storage means become the frequency of the color subcarrier. Of the address given to the storage means in one horizontal scanning period, so that the error is small. Video encoder, characterized in that a means for correcting the number of shifts of the address in the generating means.