JP2569109B2 - Pressure contact type semiconductor device - Google Patents

Pressure contact type semiconductor device

Info

Publication number
JP2569109B2
JP2569109B2 JP63039395A JP3939588A JP2569109B2 JP 2569109 B2 JP2569109 B2 JP 2569109B2 JP 63039395 A JP63039395 A JP 63039395A JP 3939588 A JP3939588 A JP 3939588A JP 2569109 B2 JP2569109 B2 JP 2569109B2
Authority
JP
Japan
Prior art keywords
electrode
semiconductor substrate
electrode plate
plate
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63039395A
Other languages
Japanese (ja)
Other versions
JPH01215028A (en
Inventor
重靖 高槌
修六 桜田
恒吾 小田井
政文 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP63039395A priority Critical patent/JP2569109B2/en
Publication of JPH01215028A publication Critical patent/JPH01215028A/en
Application granted granted Critical
Publication of JP2569109B2 publication Critical patent/JP2569109B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、自己消弧機能を有する圧接型半導体装置に
係り、特に電流遮断性能の向上に好適な電極板の接続に
関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pressure contact type semiconductor device having a self-extinguishing function, and more particularly to connection of an electrode plate suitable for improving current interruption performance.

〔従来の技術〕[Conventional technology]

従来の圧接型半導体装置、特に半導体基板をタングス
テン又はモリブデンの支持板に合金ろう接しない構造で
は、例えば特開昭47-4715号公報に記載のように、半導
体基板の両主面に展延性の金属板を配置し、それに隣接
する応力緩衝板を介してポスト電極で加圧接触する構造
にとしていた。そし半導体基板を中心にして、展延性金
属板と応力緩衝板を対称的に配置する事を特徴としてい
た。
In a conventional pressure-contact type semiconductor device, particularly in a structure in which a semiconductor substrate is not brazed to a tungsten or molybdenum support plate by alloying, for example, as described in JP-A-47-4715, extensibility is applied to both main surfaces of the semiconductor substrate. In this structure, a metal plate is disposed, and a pressure contact is made with a post electrode via a stress buffer plate adjacent to the metal plate. The spreadable metal plate and the stress buffer plate are symmetrically arranged around the semiconductor substrate.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上記従来技術は半導体基板、展延性の金属及び応力緩
衝板が全て加圧により接触する構造であるので、特にGT
Oサイリスタのように、半導体基板の電極が多数個に分
割されている場合、分割された電極全面にわたつて電気
的,機械的に均一に加工接触させる点について考慮が払
われていなかつた。半導体基板に不均一な加圧力が加え
られると、半導体基板の多数個の電極とこれに接する金
属板の間の接触抵抗が不均一になり、GTOサイリスタの
場合には多数個の電極に流れる電流分担が不均一になつ
て接触抵抗の小さい電極に電流が集中する。そして電流
遮断(ターンオフ)時にはこの電流集中が更に拡大さ
れ、半導体基板全体としての電流遮断性能が低下し、著
しい場合には遮断不能又は電流が集中する部分で素子が
破壊するという問題があつた。本発明の目的は半導体基
板の両主面に形成された電極とそれに接する金属板とを
電気的,機械的に均一に接続して多数個の電極に電流を
均一に分散させ、電流遮断性能を向上することにある。
The above prior art has a structure in which the semiconductor substrate, the extensible metal and the stress buffering plate are all in contact with each other under pressure, so that especially the GT
When an electrode of a semiconductor substrate is divided into a large number of pieces, such as an O-thyristor, no consideration has been given to the point of uniformly and mechanically contacting the entire surface of the divided electrodes. When a non-uniform pressing force is applied to the semiconductor substrate, the contact resistance between many electrodes of the semiconductor substrate and the metal plate in contact therewith becomes non-uniform, and in the case of a GTO thyristor, the current sharing of the many electrodes is divided. The current becomes non-uniform and the current concentrates on the electrode having a small contact resistance. At the time of current interruption (turn-off), the current concentration is further increased, and the current interruption performance of the entire semiconductor substrate is reduced. If the current interruption is severe, the element cannot be interrupted or the element is destroyed at a portion where the current is concentrated. SUMMARY OF THE INVENTION An object of the present invention is to uniformly and electrically and mechanically connect electrodes formed on both main surfaces of a semiconductor substrate and a metal plate in contact with the electrodes, thereby dispersing current uniformly to a large number of electrodes, and improving current interrupting performance. To improve.

〔課題を解決するための手段〕[Means for solving the problem]

かかる目的は、半導体基板の一方主面に形成された電
極を、薄い金属板により金属学的に合金接着し、特に多
数個に分割された電極を薄い金属板で並列に結合するこ
とにより達成される。
This object is achieved by metallurgically bonding the electrodes formed on one main surface of the semiconductor substrate with a thin metal plate, and in particular, by connecting a plurality of divided electrodes in parallel with the thin metal plate. You.

また、半導体基板の他方の主面に形成された電極に薄
い金属板を接着すると目的を達成する上で好ましい結果
が得られる。ここでいう薄い金属板とは、モリブデン,
タングステン,金,銀,銅から選ばれた材料で作られ、
0.5mm以下好ましくは0.1mm付近の厚さを有する金属板で
ある。
Further, if a thin metal plate is bonded to an electrode formed on the other main surface of the semiconductor substrate, a favorable result for achieving the object can be obtained. Here, the thin metal plate is molybdenum,
Made of materials selected from tungsten, gold, silver and copper,
It is a metal plate having a thickness of 0.5 mm or less, preferably around 0.1 mm.

〔作用〕[Action]

半導体基板の一方主面に形成された電極に薄い金属板
を接着することは、電極が多数個に分割された一方の主
面では薄い金属板により多数個の電極を一体化すること
になり、多数個の各々の電極と金属板の間に介在する接
触抵抗を無くすことができる。そのため多数個の電極に
流れる電流の分担が均一化されるので電流遮断時の電流
集中を低減でき、安全に電流を遮断できる。また、他方
の主面において電極と薄い金属板を接着すれば、半導体
基板と異なる材料の接着による半導体基板自体の変形を
防止することになり、さらに薄い金属板とそれに対向す
る応力緩衝板間の接触抵抗も低減できる。このことは、
一方主面に形成される電極が多数個に分割されていない
場合においても本発明の効果が期待できることを意味し
ている。
Adhesion of a thin metal plate to an electrode formed on one main surface of a semiconductor substrate means that a large number of electrodes are integrated by a thin metal plate on one main surface where the electrodes are divided into a number of pieces. It is possible to eliminate the contact resistance between the plurality of electrodes and the metal plate. Therefore, the distribution of the current flowing through the multiple electrodes is made uniform, so that the current concentration at the time of current interruption can be reduced, and the current can be safely interrupted. In addition, if the electrode and the thin metal plate are bonded on the other main surface, deformation of the semiconductor substrate itself due to bonding of a material different from that of the semiconductor substrate is prevented, and furthermore, between the thin metal plate and the stress buffer plate opposed thereto. Contact resistance can also be reduced. This means
On the other hand, it means that the effects of the present invention can be expected even when the electrodes formed on the main surface are not divided into a large number.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図により説明する。 Hereinafter, an embodiment of the present invention will be described with reference to FIG.

第1図は圧接型GTOサイリスタの断面構造図で、円板
状を有する半導体基板1のカソード面においては多数個
オーミツク接触したカソード電極2に薄い円板状のカソ
ード電極板4が接着され、他方アノード面においては、
分割されていないアノード電極3に薄い円板状のアノー
ド電極板5が接着されている。そして、カソード電極板
4は円板状のカソード応力緩衝板6を介してカソードポ
スト電極8に、アノード電極板5は円板状のアノード応
力緩衝板7を介してアノードポスト電極9によりそれぞ
れ加圧接触している。一方、ゲート電極12はゲートリー
ド13がゲート絶縁体14と座金11を介して皿バネ10により
一定圧力で加圧接触されている。そして半導体基板1は
ポスト電極8,9、絶縁体15及びフランジ16,17により構成
される容器内に気密封止されている。第2図は第1図の
要部を拡大して示したものである。半導体基板1のカソ
ード電極2とアノード電極3に接着するカソード電極板
4とアノード電極板5はこれの接着時に、又は半導体装
置動作時に半導体基板1に過大な応力を与えない様にそ
の厚さは0.5mm以下で0.1mm程度であることが望ましい。
そしてその材料はモリブデンやタングステンであれば、
熱膨張係数が半導体基板1の材料であるシリコン等に近
似しているので半導体基板に与える応力は小さくなり信
頼性の高いものとなる。また、銅,銀,金等の材料であ
る場合には電気,熱伝導が良好であるため半導体装置全
体としての特性が向上する。熱膨張係数は半導体基板1
と大きく異なつてくる縦弾性係数が小さく、また薄板で
あるため半導体基板1に与える応力は小さいものとなり
不都合は生じない。さらに、カソード電極板4とアノー
ド電極板5と同じ厚みにする事で異なる材料の接着によ
る半導体基板1の彎曲を防止できる。
FIG. 1 is a sectional view of a press-contact type GTO thyristor. On a cathode surface of a semiconductor substrate 1 having a disk shape, a thin disk-shaped cathode electrode plate 4 is adhered to a plurality of cathode electrodes 2 in ohmic contact. On the anode side,
A thin disk-shaped anode electrode plate 5 is bonded to the undivided anode electrode 3. The cathode electrode plate 4 is pressed by the cathode post electrode 8 via the disk-shaped cathode stress buffer plate 6, and the anode electrode plate 5 is pressed by the anode post electrode 9 via the disk-shaped anode stress buffer plate 7. In contact. On the other hand, the gate electrode 12 is brought into pressure contact with the gate lead 13 at a constant pressure by the disc spring 10 via the gate insulator 14 and the washer 11. The semiconductor substrate 1 is hermetically sealed in a container formed by the post electrodes 8 and 9, the insulator 15 and the flanges 16 and 17. FIG. 2 is an enlarged view of a main part of FIG. The thickness of the cathode electrode plate 4 and the anode electrode plate 5 that are bonded to the cathode electrode 2 and the anode electrode 3 of the semiconductor substrate 1 are set so that excessive stress is not applied to the semiconductor substrate 1 at the time of bonding or when the semiconductor device is operated. It is desirable that the thickness be about 0.5 mm or less and about 0.1 mm.
And if the material is molybdenum or tungsten,
Since the coefficient of thermal expansion is close to that of silicon or the like, which is the material of the semiconductor substrate 1, the stress applied to the semiconductor substrate is small and the reliability is high. In addition, when the material is made of copper, silver, gold, or the like, the electrical and thermal conductivity is good, so that the characteristics of the semiconductor device as a whole are improved. Coefficient of thermal expansion is semiconductor substrate 1
The longitudinal elastic coefficient, which is largely different from that described above, is small, and since it is a thin plate, the stress applied to the semiconductor substrate 1 is small and no inconvenience occurs. Further, by making the thicknesses of the cathode electrode plate 4 and the anode electrode plate 5 the same, it is possible to prevent the semiconductor substrate 1 from being bent due to adhesion of different materials.

一方、カソード応力緩衝板6とアノード応力緩衝板7
は、半導体基板1と大きく熱膨張係数の異なる通常は銅
からなるカソードポスト電極8とアノードポスト電極9
から受ける熱応力を緩和するため、1mm以上の板厚でか
つ材料は熱膨張係数が半導体基板に近く、縦弾性係数が
銅より十分大きいモリブデンやタングステンが用いられ
る。
On the other hand, the cathode stress buffer plate 6 and the anode stress buffer plate 7
Are a cathode post electrode 8 and an anode post electrode 9 which are usually made of copper and have a large thermal expansion coefficient different from that of the semiconductor substrate 1.
Molybdenum or tungsten having a plate thickness of 1 mm or more and a thermal expansion coefficient close to that of the semiconductor substrate and a sufficiently large longitudinal elastic coefficient than copper is used to alleviate the thermal stress received from the substrate.

本実施例によれば、多数個に分割されたカソード電極
2をカソード電極板4で接着一体化したので、加圧の不
均一による接触抵抗を無くなつて最良の並列動作が可能
となり、またアノード電極3をアノード電極板で接着し
てカソード電極板3を接着した影響を緩和しているので
GTOサイリスタの性能を十分引出すことができる。さら
に本実施例の構成からなる半導体装置はGTOサイリスタ
ばかりでなく、圧接型のサイリスタトランジスタ,ダイ
オードやSIサイリスタの様な比較的大電流を制御する圧
接型半導体装置に適用する事により各々の装置の特性を
最大に引出すことが可能となる。
According to this embodiment, since the cathode electrode 2 divided into a large number is bonded and integrated with the cathode electrode plate 4, the best parallel operation is possible without contact resistance due to uneven pressurization. Since the electrode 3 is bonded with the anode electrode plate to reduce the effect of bonding the cathode electrode plate 3,
GTO thyristor performance can be fully exploited. Further, the semiconductor device having the structure of the present embodiment is applied to not only a GTO thyristor but also a pressure-contact type semiconductor device which controls a relatively large current, such as a pressure-contact thyristor transistor, a diode, and an SI thyristor. Characteristics can be maximized.

〔発明の効果〕〔The invention's effect〕

本発明によれば、半導体基板に多数個配列された電極
を薄い電極板で均一に接着するため電極と電極板間の接
触抵抗を無くすことができ、これにより加圧の不均一に
よる接触抵抗の不均一、さらに接触抵抗の不均一による
電流遮断時の電流集中の増大を低減できるので電流遮断
性能が向上する効果がある。
According to the present invention, a large number of electrodes arranged on a semiconductor substrate are uniformly adhered to each other with a thin electrode plate, so that contact resistance between the electrodes and the electrode plate can be eliminated. Since an increase in current concentration at the time of current interruption due to non-uniformity and non-uniform contact resistance can be reduced, there is an effect that current interruption performance is improved.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の一実施例の圧接型GTOサイリスタの縦
断面図、第2図は第1図の要部拡大図である。 1……半導体基板、2……カソード電極、3……アノー
ド電極、4……カソード電極板、5……アノード電極
板、6……カソード応力緩衝板、7……アノード応力
板。
FIG. 1 is a longitudinal sectional view of a press contact type GTO thyristor of one embodiment of the present invention, and FIG. 2 is an enlarged view of a main part of FIG. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Cathode electrode, 3 ... Anode electrode, 4 ... Cathode electrode plate, 5 ... Anode electrode plate, 6 ... Cathode stress buffer plate, 7 ... Anode stress plate.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小田井 恒吾 茨城県日立市幸町3丁目1番1号 株式 会社日立製作所日立工場内 (72)発明者 小野 政文 茨城県日立市弁天町3丁目10番2号 日 立原町電子工業株式会社内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kogo Otai 3-1-1, Sachimachi, Hitachi-shi, Ibaraki Hitachi, Ltd. Hitachi Plant (72) Inventor Masafumi Ono 3-chome, Bentencho, Hitachi-shi, Ibaraki No. 2 Sun Tachihara Town Electronics Co., Ltd.

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】一対の主面間に少なくとも1つのPN接合を
有する半導体基板と、半導体基板の一方の主面にオーミ
ック接触し多数個に分割された一方の電極と、一方の電
極上に載置され一方の電極のそれぞれに接着された第1
の電極板と、第1の電極板上に載置され第1の電極板よ
り厚さが大きく半導体基板に近似した熱膨張係数を有す
る第2の電極板と、第2の電極板上に載置され第2の電
極板を第1の電極板に押圧する第1の金属ポスト電極と
を具備することを特徴とする圧接型半導体装置。
1. A semiconductor substrate having at least one PN junction between a pair of main surfaces, one electrode divided into a number of pieces by ohmic contact with one main surface of the semiconductor substrate, and mounted on one electrode. And a first electrode attached to each of the one electrodes
An electrode plate, a second electrode plate mounted on the first electrode plate, having a larger thermal expansion coefficient than the first electrode plate and having a thermal expansion coefficient close to that of the semiconductor substrate, and a second electrode plate mounted on the second electrode plate. And a first metal post electrode for pressing the second electrode plate against the first electrode plate.
【請求項2】一対の主面間に少なくとも1つのPN接合を
有する円板状の半導体基板と、半導体基板の一方主面に
オーミック接触した複数個の一方の電極と、半導体基板
の他方主面にオーミック接触した他方の電極と、複数個
の一方の電極に接着した円板状の第1の電極板とを具備
するサブアセンブリを、半導体基板に近似した熱膨張係
数を有し第1の電極板より厚い円板状を有する一対の第
2の電極板を介して一対の金属ポスト電極により押圧す
ることを特徴とする圧接型半導体装置。
2. A disk-shaped semiconductor substrate having at least one PN junction between a pair of main surfaces, a plurality of one electrodes in ohmic contact with one main surface of the semiconductor substrate, and the other main surface of the semiconductor substrate. A sub-assembly including the other electrode in ohmic contact with the first electrode and a disc-shaped first electrode plate adhered to the plurality of one electrodes, the first electrode having a thermal expansion coefficient similar to that of the semiconductor substrate; A press-contact type semiconductor device characterized in that a pair of metal post electrodes presses through a pair of second electrode plates having a disc shape thicker than a plate.
【請求項3】請求項2記載の第1の電極板がタングステ
ン,モリブデン,金,銀,銅から選ばれた材料からなっ
ていることを特徴とする圧接型半導体装置。
3. The pressure-contact type semiconductor device according to claim 2, wherein the first electrode plate is made of a material selected from tungsten, molybdenum, gold, silver, and copper.
JP63039395A 1988-02-24 1988-02-24 Pressure contact type semiconductor device Expired - Fee Related JP2569109B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63039395A JP2569109B2 (en) 1988-02-24 1988-02-24 Pressure contact type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63039395A JP2569109B2 (en) 1988-02-24 1988-02-24 Pressure contact type semiconductor device

Publications (2)

Publication Number Publication Date
JPH01215028A JPH01215028A (en) 1989-08-29
JP2569109B2 true JP2569109B2 (en) 1997-01-08

Family

ID=12551809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63039395A Expired - Fee Related JP2569109B2 (en) 1988-02-24 1988-02-24 Pressure contact type semiconductor device

Country Status (1)

Country Link
JP (1) JP2569109B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3259599B2 (en) * 1995-06-20 2002-02-25 三菱電機株式会社 Pressure contact type semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921033A (en) * 1982-07-27 1984-02-02 Mitsubishi Electric Corp All compression bonding type semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921033A (en) * 1982-07-27 1984-02-02 Mitsubishi Electric Corp All compression bonding type semiconductor device

Also Published As

Publication number Publication date
JPH01215028A (en) 1989-08-29

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