JPH09213723A - Power semiconductor device - Google Patents

Power semiconductor device

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Publication number
JPH09213723A
JPH09213723A JP2090096A JP2090096A JPH09213723A JP H09213723 A JPH09213723 A JP H09213723A JP 2090096 A JP2090096 A JP 2090096A JP 2090096 A JP2090096 A JP 2090096A JP H09213723 A JPH09213723 A JP H09213723A
Authority
JP
Japan
Prior art keywords
post
cathode
anode
semiconductor device
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2090096A
Other languages
Japanese (ja)
Inventor
Toshiaki Morita
俊章 守田
Hitoshi Onuki
仁 大貫
Mitsuo Kato
光雄 加藤
Mitsuo Sato
満雄 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2090096A priority Critical patent/JPH09213723A/en
Publication of JPH09213723A publication Critical patent/JPH09213723A/en
Pending legal-status Critical Current

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  • Die Bonding (AREA)
  • Thyristors (AREA)

Abstract

PROBLEM TO BE SOLVED: To eliminate deformation in external electrodes due to pressure during machining, heat treatment or compression bonding by selecting as external electrode material a material having a breakdown strength of specific value or above, excellent in strength, electrical conductivity, thermal conductivity and heat resistance. SOLUTION: A large number of cathode electrodes 2 placed on the cathode plane on a semiconductor device substrate 1 are pressurized and brought into contact by a cathode post 4 with a cathode stress relieving board 3. An anode electrode plate 5 is pressurized and brought into contact by an anode post 7 with an anode stress relieving board 6. A copper-chromium alloy or copper- silver alloy, excellent in heat radiation and electrical conductivity, and having such a high strength that the 0.2% breakdown strength of the post electrode material is 1kg/mm<2> or above, is used for the cathode post 4 and the anode post 7. The posts are provided with a structure that contributes to uniform pressurization. This eliminates contact resistance due to uneven pressurization to numerously divided cathode electrodes, and enables best parallel operation, which gets the best performance from a GTO thyristor.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は電力用半導体装置に
係り、特に、加圧時の局部的な面圧分布を抑制できる電
力用半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device capable of suppressing local surface pressure distribution during pressurization.

【0002】[0002]

【従来の技術】ダイオード,光サイリスタ,GTO(ゲ
ートターンオフ)サイリスタ等の電力用半導体素子と電
極とを加圧接触させる圧接型半導体装置、すなわち、電
力用半導体装置は、放熱,電流容量,半導体素子基板径
などの特殊な条件を満足させるために、スタット型ある
いはフラット型などの加圧接触(圧接)型パッケージが
用いられる。
2. Description of the Related Art A pressure contact type semiconductor device in which a power semiconductor element such as a diode, an optical thyristor, a GTO (gate turn-off) thyristor and the like is brought into pressure contact with an electrode, that is, a power semiconductor device includes heat dissipation, a current capacity, a semiconductor element. A pressure contact (pressure contact) type package such as a stat type or a flat type is used to satisfy special conditions such as a substrate diameter.

【0003】図2(a),(b)はそれぞれ従来の圧接型
GTOサイリスタについて、合金型、および圧接型構造
の一例を概略的に示したものである。ここで16はpn
接合を有する半導体素子基板であり、両主面に電極が形
成されている。また、この半導体素子基板の周端面部
は、シリコーンゴム17で覆われている。
2 (a) and 2 (b) schematically show an example of an alloy type and a pressure contact type structure of a conventional pressure contact type GTO thyristor, respectively. Where 16 is pn
It is a semiconductor element substrate having a junction, and electrodes are formed on both main surfaces. The peripheral end surface of the semiconductor element substrate is covered with silicone rubber 17.

【0004】(a)に示す合金型構造では、半導体素子
基板の陽極側が内部電極材(モリブデン,タングステン
など)18に金属ろう材を介して固着され、半導体素子
基板の陰極側に内部電極部材18が配置され、これらの
両面から外部電極材(銅)19により加圧されている。
In the alloy type structure shown in (a), the anode side of the semiconductor element substrate is fixed to the internal electrode material (molybdenum, tungsten, etc.) 18 via a brazing metal, and the internal electrode member 18 is attached to the cathode side of the semiconductor element substrate. Are arranged and pressed from both sides by the external electrode material (copper) 19.

【0005】(b)に示す圧接型構造では、半導体素子
基板16の両主面の電極に対してそれぞれ内部電極部材
18を介して加圧した状態で外部電極材19が配置され
ている。この場合、半導体素子基板16と内部電極部材
18と外部電極材19との各対向面は互いに固着される
ことなく、互いに接触した状態で加圧されている。
In the pressure contact type structure shown in (b), the external electrode material 19 is arranged in a state of being pressed against the electrodes on both main surfaces of the semiconductor element substrate 16 via the internal electrode members 18, respectively. In this case, the facing surfaces of the semiconductor element substrate 16, the internal electrode member 18, and the external electrode material 19 are not fixed to each other but are pressed in a state of being in contact with each other.

【0006】GTOのような半導体素子で、均一な圧接
が実現できないと十分な電気的特性が得られない。この
構造の圧半導体装置の半導体素子に生じる応力分布は、
外部電極の形状に強く依存する。圧接時に外部電極が塑
性変形すると、面圧分布(圧縮応力)は高い箇所と低い
箇所とが生ずるようになり、内部電極電極材と半導体基
板上に形成した電極とが均一に接触できなくなる。特に
GTO,大電力用トランジスタ等のように陰極側の電極
が多数あるような半導体素子は接触部の圧接形態が均一
にならなく、個々の電極接触部の電気的特性が低下する
ものがある。
In a semiconductor device such as GTO, sufficient electrical characteristics cannot be obtained unless uniform pressure contact is realized. The stress distribution generated in the semiconductor element of the pressure semiconductor device having this structure is
It strongly depends on the shape of the external electrode. When the external electrode is plastically deformed during the pressure contact, a portion where the surface pressure distribution (compressive stress) is high and a portion where the surface pressure is low are generated, and the internal electrode electrode material and the electrode formed on the semiconductor substrate cannot be contacted uniformly. In particular, in a semiconductor device having a large number of electrodes on the cathode side such as a GTO and a transistor for high power, the pressure contact form of the contact portion may not be uniform, and the electrical characteristics of the individual electrode contact portions may deteriorate.

【0007】[0007]

【発明が解決しようとする課題】上記従来技術は、半導
体素子基板と電極部材とが全て加圧により接触する構造
であるので、特に半導体素子基板の電極が多数個に分割
されている場合、外部電極が塑性変形していると、分割
された電極全面にわたって電気的,機械的に均一に加圧
接触させることは困難である。
The above-mentioned prior art has a structure in which the semiconductor element substrate and the electrode member are all brought into contact with each other by pressurization. Therefore, especially when the electrodes of the semiconductor element substrate are divided into a large number, When the electrodes are plastically deformed, it is difficult to make electrical and mechanical uniform pressure contact over the entire surface of the divided electrodes.

【0008】半導体素子基板に不均一な加圧力が加えら
れると、半導体素子基板の多数個の電極とこれに接する
金属板の間の接触抵抗が不均一になり、GTOサイリス
タの場合には多数個の電極に流れる電流分担が不均一に
なって接触抵抗の小さい電極に集中する。そして電流遮
断時にはこの電流集中が拡大され、著しい場合には、電
流が集中する部分で半導体素子が破壊し、すなわち破壊
耐量が低くなってしまうという問題があった。
When a non-uniform pressure is applied to the semiconductor element substrate, the contact resistance between the many electrodes of the semiconductor element substrate and the metal plate in contact therewith becomes non-uniform, and in the case of the GTO thyristor, many electrodes are applied. The distribution of the current flowing through the electrodes becomes uneven, and the current concentrates on the electrodes with low contact resistance. Then, when the current is cut off, the current concentration is increased, and when it is significant, the semiconductor element is broken at the portion where the current is concentrated, that is, the breakdown resistance is low.

【0009】本発明の目的は、外部電極の加工,熱処
理、及び圧接時の塑性変形を無くして、半導体素子と電
極板の接触を均一にすることで、多数個の電極に電流を
均一に分散させ、半導体素子の破壊耐量が増加する圧接
型半導体装置を提供することにある。
An object of the present invention is to eliminate the plastic deformation during processing, heat treatment, and pressure contact of the external electrodes to make the contact between the semiconductor element and the electrode plate uniform, so that the current is evenly distributed to a large number of electrodes. Another object of the present invention is to provide a pressure contact type semiconductor device in which the breakdown resistance of the semiconductor element is increased.

【0010】[0010]

【課題を解決するための手段】上記目的を達成するた
め、本発明は外部電極材として、高強度,高電気伝導
性,高熱伝導性,高耐熱性を有する材料を選択する。
In order to achieve the above object, the present invention selects a material having high strength, high electrical conductivity, high thermal conductivity and high heat resistance as an external electrode material.

【0011】外部電極材として、高強度,高電気伝導
性,高熱伝導性を有する材料を選択することにより、加
工,熱処理、及び圧接時の圧力による外部電極の変形を
無くす。その結果、半導体素子に偏荷重が生じないの
で、広範囲にわたり均一に加圧することができる。さら
に、多数個の電極に流れる電流の分担が均一化されるの
で、電流遮断時の電流集中を低減でき、安全に電流を遮
断できる。
By selecting a material having high strength, high electrical conductivity and high thermal conductivity as the external electrode material, deformation of the external electrode due to pressure during processing, heat treatment and pressure welding can be eliminated. As a result, an unbalanced load does not occur in the semiconductor element, so that the semiconductor element can be uniformly pressed over a wide range. Further, since the sharing of the current flowing through a large number of electrodes is made uniform, the current concentration at the time of current interruption can be reduced and the current can be safely interrupted.

【0012】[0012]

【発明の実施の形態】以下、本発明の一実施例を図1に
より説明する。図1は圧接型GTOサイリスタの断面図
で、半導体素子基板1のカソード面に多数個配列された
カソード電極2は、カソード応力緩衝板3を介してカソ
ードポスト4に、アノード電極板5はアノード応力緩衝
板6を介してアノードポスト7によりそれぞれ加圧接触
する。半導体素子基板1周端部はエンキャップ材(シリ
コーンゴム)15で覆われている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a cross-sectional view of a pressure contact type GTO thyristor. A large number of cathode electrodes 2 arranged on the cathode surface of a semiconductor element substrate 1 are connected to a cathode post 4 via a cathode stress buffer plate 3, and an anode electrode plate 5 is connected to an anode stress. The anode posts 7 are brought into pressure contact with each other via the buffer plate 6. A peripheral end portion of the semiconductor element substrate 1 is covered with an encap material (silicone rubber) 15.

【0013】一方、ゲート電極8にはゲートリード9が
ゲート絶縁体10と座金11を介して皿ばね12により
一定加圧で加圧接触される。そして半導体素子基板は、
絶縁体13とフランジ14により気密封止されている。
On the other hand, a gate lead 9 is brought into pressure contact with the gate electrode 8 by a disc spring 12 via a gate insulator 10 and a washer 11 at a constant pressure. And the semiconductor element substrate is
It is hermetically sealed by the insulator 13 and the flange 14.

【0014】カソード応力緩衝板3とアノード応力緩衝
板6は、カソードポスト4とアノードポスト7から受け
る熱応力を緩和し、半導体素子基板1を保護するため、
1mm以上の板厚でかつ材料は熱膨張係数が半導体素子基
板1のシリコンの熱膨張係数に近いモリブデンやタング
ステンが用いられる。
The cathode stress buffer plate 3 and the anode stress buffer plate 6 alleviate the thermal stress received from the cathode posts 4 and the anode posts 7 and protect the semiconductor element substrate 1.
Molybdenum or tungsten having a plate thickness of 1 mm or more and having a thermal expansion coefficient close to that of silicon of the semiconductor element substrate 1 is used as the material.

【0015】カソードポスト4およびアノードポスト7
には、放熱性,電気伝導性に優れ、かつ高強度を有する
銅−クロム(Cu−Cr)合金、または銅−銀(Cu−
Ag)合金を用い、均一加圧に寄与する構造をとってい
る。
Cathode post 4 and anode post 7
Include a copper-chromium (Cu-Cr) alloy having excellent heat dissipation and electric conductivity and high strength, or copper-silver (Cu-
It uses an Ag) alloy and has a structure that contributes to uniform pressurization.

【0016】純銅,Cu−Cr合金、およびCu−Ag
合金の種々の熱処理温度に対する0.2% 耐力を図3に
示す。熱処理時間は20分である。
Pure copper, Cu-Cr alloy, and Cu-Ag
The 0.2% yield strength of the alloy for various heat treatment temperatures is shown in FIG. The heat treatment time is 20 minutes.

【0017】ここでフランジ14とカソードポスト4お
よびフランジ14とアノードポスト7とをろう材を用い
て接合する温度範囲は、600ないし800℃である。
Here, the temperature range in which the flange 14 and the cathode post 4 and the flange 14 and the anode post 7 are joined by using a brazing material is 600 to 800 ° C.

【0018】純銅は、熱処理温度が250℃を超えると
0.2% 耐力が急激に減少し、600℃以上になると0.2
% 耐力が数MPa程度にまで低下する。カソードポス
ト4およびアノードポスト7を押して使用する本実施例
のような電力用半導体装置では、加圧したときの各ポス
トに及ぼされる圧力は、数MPaないし10MPaであ
ることが多い。従ってポスト材料に純銅を用いると、加
圧時の応力が0.2 %耐力を超えるために塑性変形して
しまう。その結果、偏荷重が生じ、半導体基板を均一に
加圧できなくなる。
Pure copper has a 0.2% proof stress when the heat treatment temperature exceeds 250 ° C., and 0.2% when the heat treatment temperature exceeds 600 ° C.
% Proof strength decreases to about several MPa. In the power semiconductor device of the present embodiment in which the cathode post 4 and the anode post 7 are pressed to be used, the pressure exerted on each post when pressurized is often several MPa to 10 MPa. Therefore, when pure copper is used as the post material, the stress at the time of pressurization exceeds 0.2% proof stress, resulting in plastic deformation. As a result, an unbalanced load is generated and the semiconductor substrate cannot be pressed uniformly.

【0019】Cu−Cr合金、およびCu−Ag合金
は、800℃で20分熱処理の0.2%耐力は50MP
a以上ある。ポスト材料にCu−Cr合金、あるいはC
u−Ag合金を用いれば、前述した加圧力に対して変形
することが無く、均一加圧が実現できる。
The Cu-Cr alloy and the Cu-Ag alloy have a 0.2% proof stress of 50 MP after heat treatment at 800 ° C for 20 minutes.
There is more than a. Cu-Cr alloy or C for post material
If the u-Ag alloy is used, uniform pressing can be realized without being deformed by the above-mentioned pressing force.

【0020】フランジ14とカソードポスト4およびフ
ランジ14とアノードポスト7とを接合する際に用いる
ろう材を低融点のものにすれば、さらに信頼性の高い半
導体装置が実現できる。
If the brazing filler metal used when joining the flange 14 and the cathode post 4 and the flange 14 and the anode post 7 to each other has a low melting point, a more reliable semiconductor device can be realized.

【0021】本実施例によれば、ポスト電極材に、放熱
性,電気伝導性に優れ、かつ高強度を有し、高加圧力下
でも塑性変形しない材料を用いることで、多数個に分割
されたカソード電極に対し、加圧の不均一による接触抵
抗を無くして最良の並列動作が可能となり、GTOサイ
リスタの性能を十分引き出すことができる。
According to the present embodiment, the post electrode material is divided into a large number by using a material having excellent heat dissipation and electrical conductivity, high strength, and not plastically deformed even under a high applied pressure. With respect to the cathode electrode, it is possible to eliminate the contact resistance due to the non-uniformity of pressurization and perform the best parallel operation, so that the performance of the GTO thyristor can be fully brought out.

【0022】さらに、本実施例の構成からなる半導体装
置は、GTOサイリスタのみならず、圧接型のサイリス
タ,トランジスタ,ダイオードやSIサイリスタのよう
な比較的大電流を制御する圧接型半導体装置に適用する
ことにより、各々の装置の特性を最大に引き出すことが
できる。
Further, the semiconductor device having the structure of this embodiment is applied not only to GTO thyristors but also to pressure contact type semiconductor devices such as pressure contact type thyristors, transistors, diodes and SI thyristors which control a relatively large current. As a result, the characteristics of each device can be maximized.

【0023】なお、本発明で、ポスト電極材料には、C
u−Cr合金およびCu−Ag合金のみならず、放熱
性,電気伝導性に優れ、かつ高強度を有し、高加圧力下
でも塑性変形せず、また、熱膨張係数が半導体素子基板
を形成するシリコン(Si)に近いため、熱応力が低減
できる銅−タングステン(Cu−W)材も有用である。
In the present invention, the post electrode material is C
Not only u-Cr alloys and Cu-Ag alloys, but also excellent in heat dissipation and electrical conductivity, having high strength, not plastically deformed even under high pressure, and forming a semiconductor element substrate with a thermal expansion coefficient. A copper-tungsten (Cu-W) material that can reduce thermal stress because it is close to silicon (Si) is also useful.

【0024】[0024]

【発明の効果】本発明によれば、ポスト電極材料に、放
熱性,電気伝導性に優れ、かつ高強度を有し、高加圧力
下でも塑性変形しない材料を採用するため、半導体素子
基板に対する偏荷重の発生を回避できるので、半導体素
子基板に多数個配列された電極と内部電極板とを均一に
加圧接触させること、すなわち、加圧の不均一による接
触抵抗の不均一、さらに接触抵抗の不均一による電流遮
断時の電流集中の増大を低減できるので、電流遮断性能
が向上する。
According to the present invention, a material for a post electrode that is excellent in heat dissipation and electric conductivity, has high strength, and is not plastically deformed even under high pressure is applied. Since it is possible to avoid the occurrence of an unbalanced load, it is necessary to uniformly press-contact the electrodes arranged in large numbers on the semiconductor element substrate and the internal electrode plate, that is, non-uniform contact resistance due to non-uniform pressure, and further contact resistance. Since the increase in current concentration at the time of current interruption due to the non-uniformity of can be reduced, the current interruption performance is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による圧接型半導体装置の実施例の断面
図。
FIG. 1 is a sectional view of an embodiment of a pressure contact type semiconductor device according to the present invention.

【図2】従来から用いられている圧接型半導体装置の断
面図。
FIG. 2 is a cross-sectional view of a conventional pressure contact type semiconductor device.

【図3】純銅,Cu−Cr合金、およびCu−Ag合金
の種々の熱処理温度に対する0.2% 耐力を示した特性
図。
FIG. 3 is a characteristic diagram showing 0.2% proof stress of pure copper, Cu—Cr alloy, and Cu—Ag alloy at various heat treatment temperatures.

【符号の説明】[Explanation of symbols]

1…半導体素子基板、2…カソード電極、3…カソード
応力緩衝板、4…カソードポスト、5…アノード電極、
6…アノード応力緩衝板、7…アノードポスト、8…ゲ
ート電極、9…ゲートリード、10…ゲート絶縁体、1
1…座金、12…皿ばね、13…絶縁体、14…フラン
ジ、15…エンキャップ材。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element substrate, 2 ... Cathode electrode, 3 ... Cathode stress buffer plate, 4 ... Cathode post, 5 ... Anode electrode,
6 ... Anode stress buffer plate, 7 ... Anode post, 8 ... Gate electrode, 9 ... Gate lead, 10 ... Gate insulator, 1
1 ... Washer, 12 ... Disc spring, 13 ... Insulator, 14 ... Flange, 15 ... Encap material.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐藤 満雄 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuo Sato 7-1-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】少なくとも一つのpn接合を有する半導体
素子基板と、前記半導体素子基板の両主面に設けられた
第一電極板と、前記半導体素子基板を保護するために熱
膨張係数が前記半導体素子基板に近い第二の電極板と、
前記第一電極板と前記第二電極板を介して前記半導体素
子基板の両主面を圧接するポスト電極を備えた電力用半
導体装置において、前記ポスト電極材料の0.2%耐力
が1kg/mm2以上であることを特徴とする電力用半導体
装置。
1. A semiconductor device substrate having at least one pn junction, first electrode plates provided on both main surfaces of the semiconductor device substrate, and a semiconductor having a thermal expansion coefficient for protecting the semiconductor device substrate. A second electrode plate close to the element substrate,
In a power semiconductor device including a post electrode that press-contacts both main surfaces of the semiconductor element substrate through the first electrode plate and the second electrode plate, a 0.2% proof stress of the post electrode material is 1 kg / mm. A semiconductor device for electric power, characterized in that it is 2 or more.
【請求項2】請求項1において、前記ポスト電極が銅−
クロム(Cu−Cr)合金、または銅−銀(Cu−A
g)合金である電力用半導体装置。
2. The post electrode according to claim 1, wherein the post electrode is made of copper.
Chromium (Cu-Cr) alloy, or copper-silver (Cu-A)
g) A power semiconductor device which is an alloy.
JP2090096A 1996-02-07 1996-02-07 Power semiconductor device Pending JPH09213723A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2090096A JPH09213723A (en) 1996-02-07 1996-02-07 Power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2090096A JPH09213723A (en) 1996-02-07 1996-02-07 Power semiconductor device

Publications (1)

Publication Number Publication Date
JPH09213723A true JPH09213723A (en) 1997-08-15

Family

ID=12040114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2090096A Pending JPH09213723A (en) 1996-02-07 1996-02-07 Power semiconductor device

Country Status (1)

Country Link
JP (1) JPH09213723A (en)

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