JP2569044B2 - Digital signal processing system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing system and, for example, to a technology effective when used in a digital servo mechanism included in an optical disk reproducing apparatus. is there.

[Conventional technology]

2. Description of the Related Art In an optical disk reproducing apparatus, there is a digital servo mechanism for controlling a position and a focus of a laser beam. The digital servo mechanism includes a digital signal processing system including an A / D conversion circuit, a digital signal processor (digital signal processor), and the like.

On the other hand, there is a level shift circuit that shifts the DC level of an analog signal according to, for example, a power supply voltage of a circuit in a subsequent stage.

For such a level shift circuit, for example, 19
"Analog Integrated Circuit" published by Modern Science Co., Ltd. on September 15, 1975
It is described on pages 124-138.

[Problems to be solved by the invention]

In the above digital servo mechanism, for example, as shown in FIG. 3, the analog signal Vs output from the reflected light sensor OS is converted into a digital signal by the A / D conversion circuit A / D. These digital signals are subjected to necessary processing by a digital signal processor DSP to form predetermined control signals. These control signals are supplied to the servo motor SMO to correct the position and focus of the laser beam.

Here, the analog signal output from the reflected light sensor OS
Vs is an AC signal centered on the ground potential of the circuit, that is, zero V, and the A / D converter circuit and the digital signal processor use the power supply voltage Vcc such as +5 V and the ground potential of the circuit as operating power supplies. Therefore, a level shift circuit LVC that raises the analog signal Vs as a whole according to a bias voltage Vb of, for example, 2.5 V and shifts the DC level to an operation power supply region such as an A / D conversion circuit is required. At this time, the A / D conversion circuit forms a digital signal including the bias voltage Vb. In addition, the digital signal processor DSP converts the bias voltage V
After fixedly canceling b, a signal component for the analog signal Vs is extracted, and predetermined signal processing is performed on the signal component.

However, since the bias voltage Vb applied to the level shift circuit LVC actually changes slightly according to the fluctuation of the power supply voltage or the like, the bias voltage Vb between the level shift by the level shift circuit LVC and the offset by the digital signal processor DSP is changed. There is a slight difference in For this reason, the digital signal processor DSP cannot accurately extract the analog signal Vs, and the accuracy of the digital servo mechanism is reduced, so that accurate position and focus control of the laser beam cannot be performed.

An object of the present invention is to provide a digital signal processing system capable of accurately canceling out the level shift.
Another object of the present invention is to improve the accuracy of a digital servo mechanism including a digital signal processing system.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
At each sampling cycle of the A / D conversion circuit, both the output signal of the level shift circuit and the bias voltage applied to the level shift circuit are sampled, converted into a digital signal and transmitted to a digital signal processor, and the digital signal is processed. In the processor, an input analog signal is extracted by subtracting a digital signal corresponding to a bias voltage from a digital signal corresponding to an output signal of a level shift circuit which is sequentially applied, and performs predetermined signal processing.

[Action]

According to the above-described means, the level shift amount due to the bias signal is transmitted to the digital signal processor at each sampling period, and only the analog signal is accurately extracted, so that the performance as a digital servo mechanism is improved. It is possible to precisely control the position and focus of the light beam.

〔Example〕

FIG. 3 is a block diagram showing an embodiment of a digital servo mechanism to which the present invention is applied. Third
The circuit elements constituting each block in the figure are not particularly limited, except for the optical and mechanical parts of the servo mechanism, but are formed on a single semiconductor substrate such as single crystal silicon by a known MOS integrated circuit manufacturing technique. Formed.

Although not particularly limited, the digital servo mechanism of this embodiment is included in an optical disk reproducing apparatus, and performs position control and focus control of a reproducing laser beam on a groove of an optical disk. The playback device includes an optical disk driver ODD and a servomotor SMO for controlling the position and focus of a laser beam.
The position and focus state of the laser beam are identified by the signal level of the analog signal Vs output from the laser beam reflected light sensor OS. The analog signal Vs is level-shifted by a predetermined bias voltage Vb by a level shift circuit LVC, converted into a digital signal by an A / D conversion circuit A / D, and supplied to a digital signal processor DSP. The digital signal processor DSP forms a control signal for the servo motor SMO based on these digital signals. A digital servo mechanism of the reproducing apparatus is constituted by these series of feedback systems.

In FIG. 3, the analog signal Vs output from the reflected light sensor OS is first supplied to the level shift circuit LVC. The analog signal Vs is an AC signal centered on the ground potential of the circuit, that is, zero V, and has a maximum amplitude smaller than a power supply voltage Vcc of, for example, + 5V.

The level shift circuit LVC is supplied with a predetermined bias voltage Vb from the voltage generation circuit VC. This bias voltage Vb
Is set to 1/2 of the power supply voltage Vcc, that is, for example, about 2.5 V, although not particularly limited.

As described later, the level shift circuit LVC has an operational amplifier as a basic configuration, raises the level of the analog signal Vs supplied from the reflected light sensor OS as a whole according to the bias voltage Vb, and sets the center level to about 2.5 V. I do. The output signal Vo of the level shift circuit LVC is supplied to one input terminal of the switch circuit SW. The other input terminal of the switch circuit SW is supplied with the bias voltage Vb from the voltage generation circuit VG.

The switch circuit SW is formed by two sets of complementary transmission gates, as described later. The gates of the switch MOSFETs constituting these complementary transmission gates are supplied with a predetermined combination of a non-inverted signal and an inverted signal at the timing φc supplied from the digital signal processor DSP. The switch circuit SW follows the timing φc.
Select the analog signal Vs or bias voltage Vb by A / D
The signal is transmitted to the conversion circuit A / D.

Specific configurations and operations of the level shift circuit LVC, the voltage generation circuit VG, and the switch circuit SW will be described later in detail.

Although not particularly limited, the A / D conversion circuit A / D is configured by an instantaneous comparison type A / D conversion circuit. The sampling clock signal φs is supplied from the digital signal processor DSP to the A / D conversion circuit A / D. Although not particularly limited, the sampling clock signal φs is temporarily set to a high level about every 20 microseconds (μs). Also,
The timing φc supplied to the switch circuit SW is
Although not particularly limited, this sampling clock signal φ
It is at a low level in the first half of the period in which s is at the high level, and at a high level in the latter half. That is, in the A / D conversion circuit A / D, the bias voltage Vb supplied from the voltage generation circuit VG is sampled in the first half of each sampling period, and the output signal Vo of the level shift circuit LVC is sampled in the second half. The level of the bias voltage Vb and the level of the output signal Vo sampled in each sampling period are respectively set to the first by the A / D conversion circuit A / D.
And a second digital signal, which is further supplied to a digital signal processor DSP. These first and second digital signals have a predetermined number of bits according to the performance of the digital servo mechanism.

The digital signal processor (digital signal processor) DSP is a processing device of a stored program type, though not particularly limited, and has an arithmetic logic unit having various arithmetic functions and a data RAM (random access memory).
And so on. The digital signal processor DSP performs predetermined signal processing on the analog signal Vs sampled and digitized by the A / D conversion circuit A / D to form a control signal for driving the servo motor SMO. As described above, the analog signal Vs is digitized after being level-shifted by the level shift circuit LVC. For this reason, the digital signal processor DSP first starts A / D
By subtracting the first digital signal from the second digital signal supplied from the conversion circuit A / D, only the signal component for the analog signal Vs is extracted.

The control signal generated by the digital signal processor DSP is sent to the servo motor SMO. The servo motor SMO is driven by these control signals, and automatic control of the position and focus of the laser beam of the optical disk driver ODD with respect to the optical disk is performed.

FIG. 1 is a circuit diagram showing one embodiment of the level shift circuit LVC, voltage generation circuit VG, and switch circuit SW of the digital servo mechanism shown in FIG. In the figure, the MOSFET with an arrow added to the channel (back gate) portion is P
N-channel type with no arrows
It is distinguished from MOSFET.

In FIG. 1, a voltage generation circuit VG has an NPN-type bipolar transistor T1 constituting an emitter follower circuit as its basic configuration. The collector of transistor T1 is coupled to the power supply voltage Vcc of the circuit. Also, the transistor T1
A resistor R3 is provided between the base and the power supply voltage Vcc of the circuit, and series-connected diodes D1 to D4 and a resistor R4 are provided between the base and the ground potential of the circuit. further,
Series resistors R5 and R6 are provided between the emitter of the transistor T1 and the ground potential of the circuit. The voltage at the node where these resistors R5 and R6 are commonly connected is the bias voltage Vb.

The base potential of the transistor T1 of the voltage generating circuit VG is determined by the combined value of the forward voltage of the series-connected diodes D1 to D4 and the resistance.
Are predetermined base voltage V _B which is determined by the ratio of the resistance R value of R3 and R4. Also, the transistor T1 has almost the resistance R3
And a predetermined base current determined by R4. As a result, the transistor T1 is connected to the resistor provided at its emitter.
An emitter follower circuit is formed together with R5 and R6, and the amplification factor is substantially "1". At this time, the emitter voltage V _E of the transistor T1, when the base-emitter voltage V _BE, the V _E = V _B -V _BE. At this time, the emitter voltage _VE is further increased by the resistance R5 and
The pressure is divided by R6 and is not particularly limited, for example, about 2.
Each constant of the voltage generation circuit VG is set to be 5V.
The bias voltage Vb is supplied to one input terminal of a switch circuit SW described later, while being supplied to the level shift circuit LVC.

The level shift circuit LVC includes, but is not limited to, an operational amplifier OA and resistors R1 and R2. The inverting input terminal-of the operational amplifier OA is connected to the resistor R1 from the reflected light sensor OS.
The analog signal Vs is supplied via the. The bias voltage Vb is supplied from the voltage generating circuit VG to the non-inverting input terminal + of the operational amplifier OA. A resistor R2 is provided between the inverting input terminal-of the operational amplifier OA and the output terminal of the operational amplifier OA.

As a result, the amplification factor of the operational amplifier OA is substantially "1", and the analog signal Vs is transmitted to the output terminal of the operational amplifier OA with the same amplitude. At this time, the operational amplifier OA
Is added to the bias voltage Vb supplied to the non-inverting input terminal + of the operational amplifier OA, and the center level is set to about 2.5V. The output signal Vo of the operational amplifier OA is supplied to the other input terminal of the switch circuit SW.

Although the switch circuit SW is not particularly limited, the P-channel MOSFET Q1, the N-channel MOSFET Q3, and the P-channel MO
Includes two sets of complementary transmission gates consisting of SFET Q2 and N-channel MOSFET Q4. The gates of the MOSFETs Q2 and Q3 are supplied with a timing signal φc from the digital signal processor DSP. Further, an inverted signal of the timing signal φc by the inverter circuit N1 is supplied to the gates of the MOSFETs Q1 and Q4. As described above, the timing signal φc is set to a low level in the first half of each sampling period in which the sampling clock signal φs is set to the high level, and is set to an input level in the second half.

When the timing signal φc is at a low level, the MOSF
ETQ2 and Q4 are both turned on, and MOSFETs Q1 and Q3 are turned off. As a result, the bias voltage Vb supplied from the voltage generation circuit VG becomes A / A via the MOSFETs Q2 and Q4.
It is transmitted to the D conversion circuit A / D. On the other hand, the timing signal φc
Is high, MOSFETs Q1 and Q3 are both on, and MOSFETs Q2 and Q4 are off. As a result, the output signal Vo of the level shift circuit LVC is
The signal is transmitted to the A / D conversion circuit A / D via 1 and Q3.

FIG. 2 shows a signal waveform diagram of one embodiment of the digital servo mechanism of this embodiment. The figure shows an analog signal Vs formed by the reflected light sensor OS, an output signal Vo formed by the level shift circuit LVC, a sampling clock signal φs, a timing signal φc, and an input signal Va of the A / D conversion circuit A / D. Is illustratively shown for one cycle.

In FIG. 2, the analog signal Vs supplied from the reflected light sensor OS has its center level set to the ground potential of the circuit, ie, zero V, and its maximum amplitude is adjusted to be within the power supply voltage Vcc of the circuit. .

This analog signal Vs is level-shifted by the bias voltage Vb by the operational amplifier OA of the level shift circuit LVC, and an output signal Vo of the level shift circuit LVC is formed.
That is, the output signal Vo has a center level of about 2.5 V, for example.
And the maximum and minimum levels thereof are lower than the power supply voltage Vcc of the circuit and higher than the ground potential.

Although not particularly limited, the sampling clock signal φs is temporarily set to a high level at a predetermined sampling cycle of, for example, every 20 μs. In the sampling period in which the sampling clock signal φs is at a high level,
In the first half, the timing signal φc is set to the low level, and in the second half, the timing signal φc is set to the high level. Thus, the bias voltage Vb is sampled in the first half of each sampling period, and is supplied to the A / D conversion circuit A / D as the input signal Va. In the latter half of each sampling period, the output signal Vo of the level shift circuit LVC is sampled, and is similarly supplied to the A / D conversion circuit A / D as an input signal Va.

The sampling signal of the bias voltage Vb input to the A / D conversion circuit A / D and the sampling signal of the output signal Vo of the level shift circuit LVC are A
The signals are digitized by the / D conversion circuit A / D as first and second digital signals having a predetermined number of bits, and further transmitted to the digital signal processor DSP. In the digital signal processor DSP, first, as described above, the second
After extracting only the signal component for the analog signal Vs by canceling the first digital signal component from the digital signal component of the above, predetermined signal processing is performed to form a drive signal for the servo motor SMO.

As described above, the digital servo mechanism of this embodiment includes the analog signal Vs formed by the reflected light sensor OS.
Level shift circuit LVC for level-shifting the level of the A / D conversion circuit A / D according to the operating power supply, etc., and a voltage generating circuit VG for supplying the level shift bias voltage Vb to the level shift circuit LVC. Provided. Also, for each sampling period by the A / D conversion circuit A / D, the bias voltage Vb is selected in the first half and the output signal Vo of the level shift circuit LVC is selected in the second half, and the A / D conversion is performed.
A switch circuit SW for transmitting to the conversion circuit A / D is provided.
These sampling levels are digitized as first and second digital signals by an A / D conversion circuit A / D and supplied to a digital signal processor DSP.
In the digital signal processor DSP, first, the first digital signal is subtracted from the second digital signal to cancel the bias voltage Vb to extract a signal component with respect to the analog signal Vs. To form a control signal for driving the servo motor SMO. For this reason, although the voltage generation circuit VG has a relatively simple circuit configuration and the bias voltage Vb is at a relatively unstable level due to fluctuations in the power supply voltage, etc.
The digital signal processor DSP accurately cancels the level shift with respect to the analog signal Vs, and the analog signal Vs
Only the signal processing can be performed. For this reason,
The digital servo mechanism has improved accuracy and can perform stable position control and focus control of a laser beam.

As shown in the present embodiment, when the present invention is applied to the digital servo mechanism of the optical disk reproducing apparatus, the following effects can be obtained. (1) At each sampling cycle of the A / D conversion circuit, both the output signal of the level shift circuit and the bias voltage applied to the level shift circuit are sampled, converted into a digital signal, and transmitted to the digital signal processor. By doing so, in the digital signal processor, by subtracting these digital signals, it is possible to obtain the effect that the level shift can be accurately canceled and the analog signal component can be accurately extracted.

(2) According to the above item (1), there is obtained an effect that the accuracy of a digital signal processing system including an A / D conversion circuit and a digital signal processor can be improved, and the performance of a digital servo mechanism and the like can be improved.

(3) According to the above item (1), it is possible to simplify the circuit configuration of the voltage generating circuit for generating the bias voltage and to reduce the cost of the digital signal processing system.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in this embodiment, the bias voltage Vb is sampled in the first half of each sampling cycle in the A / D conversion circuit, and the output signal Vo of the level shift circuit LVC is sampled in the second half, but the order is reversed. There may be. In this embodiment, one A / D conversion circuit is provided, and the A / D conversion circuit is time-divisionally used by the timing signal φc to sample the bias voltage Vb and the output signal Vo of the level shift circuit LVC. A / D conversion circuits are provided corresponding to the bias voltage Vb and the output signal Vo of the level shift circuit LVC, respectively, and the digital output signals of these A / D conversion circuits are selectively taken into the digital signal processor DSP. It may be. Reflected light sensor O
The central level of the analog signal Vs formed by S is
It does not need to be the ground potential of the circuit, and the level of the bias voltage Vb need not be Vcc / 2. Further, various embodiments such as a specific circuit configuration of the level shift circuit LVC, the voltage generation circuit VG, and the switch circuit SW shown in FIG. 1 and a block configuration of the digital servo mechanism shown in FIG. 3 can be adopted. Things.

In the above description, the case where the invention made by the present inventor is mainly applied to the digital servo mechanism of the optical disc reproducing apparatus, which is the background of application, has been described. However, the present invention is not limited to this. And various digital servo mechanisms and digital control devices. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a digital signal processing system requiring at least a level shift of an input analog signal and a digital device including such a digital signal processing system.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. That is, at each sampling cycle of the A / D conversion circuit, both the output signal of the level shift circuit and the bias voltage applied to the level shift circuit are sampled and converted into digital signals, which are then transmitted to the digital signal processor, By subtracting these digital signals in the signal processor, it is possible to accurately extract analog signal components by canceling out level shifts with respect to analog signals, thereby improving the accuracy of digital signal processing systems and improving digital signal processing. It is possible to improve the performance and reduce the cost of the digital servo mechanism including the system.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing one embodiment of a level shift circuit of a digital servo mechanism to which the present invention is applied and peripheral circuits thereof. FIG. 2 is a level diagram of the level shift circuit of FIG. 1 and peripheral circuits thereof. FIG. 3 is a signal waveform diagram showing an embodiment of a shift operation and a sampling operation. FIG. 3 is a block diagram showing an embodiment of a digital servo mechanism including the level shift circuit and peripheral circuits of FIG. LVC: Level shift circuit, VG: Voltage generation circuit, SW:
... Switch circuit, A / D ... A / D conversion circuit, DSP ... Digital signal processor, SMO ... Servo motor, OS ...
… Reflection light sensor, ODD …… Optical disk driver. Q1, Q2…
… P-channel MOSFET, Q3, Q4 …… N-channel MOSFE
T, T1 ... NPN-type bipolar transistor, D1-D4 ... Diode, R1-R6 ... Resistance, N1 ... Inverter circuit, OA
…… Operational amplifier.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H03M 1/10 H03M 1/10 A

Claims (2)

(57) [Claims] A voltage generating circuit for generating a predetermined bias voltage; and a level shift circuit for outputting a level-shifted analog output signal superimposed on the bias voltage by shifting a DC level of an input analog signal according to the bias voltage. The bias voltage from the voltage generating circuit is applied to the first input terminal, the level shift analog output signal from the level shift circuit is applied to the second input terminal, and the timing input is applied to the control input terminal. When the timing signal is at a first level, the bias voltage applied to the first input terminal is transmitted to its output terminal, and the timing signal is different from the first level. The level shift analog output signal applied to the second input terminal at the time of the level is output to the output terminal. A switch circuit that reaches the output signal of the switch circuit is applied to its input terminal, a sampling clock signal is applied to its control input terminal, and when the sampling clock signal is at a predetermined level, an analog signal of the input terminal is converted to a digital signal A / D conversion circuit for converting the digital signal of the A / D conversion circuit into a digital signal processing device that performs predetermined signal processing on the digital signal of the A / D conversion circuit. The level-shifted analog output signal is an AC signal that is set to a potential substantially intermediate between the power supply voltage supplied to the A / D conversion circuit and the ground potential of the circuit. A digital signal processing system for causing a signal to fall within an operation range of A / D conversion of a circuit, wherein the sampling clock signal is at a predetermined level. The sampling clock signal and the timing signal so that there is a first period in which the timing signal is at the first level and a second period in which the timing signal is at the second level. A timing relationship with a signal is set, and the A / D conversion circuit converts a first digital conversion signal responsive to the bias voltage during the first period during the period when the sampling clock signal is at the predetermined level. And outputting a second digital conversion signal in response to the level-shifted analog output signal during the second period. The digital signal processing device outputs the first digital conversion signal and the second digital conversion signal. By performing a subtraction process with the digital conversion signal, the component of the bias voltage is canceled, and the digital signal corresponding to the input analog signal is cancelled. Digital signal processing system characterized by extracting information. 2. A servo motor is driven by the digital information extracted by the digital signal processing device, and the input analog signal is obtained from a sensor for detecting a rotation state of the servo motor. 2. The digital signal processing system according to claim 1, wherein: