JP3278027B2 - Sample and hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for sampling and holding an input analog voltage as a pre-process of A / D conversion for encoding an input analog voltage into a digital code. The present invention relates to a sample and hold circuit capable of outputting a current signal without an offset error.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram of a conventional sample and hold circuit 4. This is ISSCC90, SESSION 10, An
alog-to-Digital Converter, TPM 10.3, A 10bit 30MHz
two-Step Pallalel BiCMOS ADC with Internal S / H, A
This is the circuit described in Kira Matsuzawa, Minoru Kagawa, el.

The sample and hold circuit 5 shown in FIG. 5 includes diodes D11 to D16, bipolar transistors Q51 to Q57, a PMOS transistor Q58,
Q59, a hold capacitor C11, a phase compensation capacitor C12, and current sources I21 to I27.

[0005] 501 is a sample and hold unit, 502 is a voltage follower circuit, 503 is an emitter follower circuit, and 5
04 is an analog voltage input terminal, 505 is a sample clock input terminal, 506 is a hold clock input terminal,
507 is an output terminal.

In this circuit, during the sample period,
A high level voltage is applied to the sample clock input terminal 505,
A low-level voltage is applied to the hold clock input terminal 506, turning on the transistor Q51 and turning off the transistor Q52. As a result, diode D11~D14 is turned on, D15, D16 are turned off, the analog voltage V _in that is input to the input terminal 504, a common connection point of the diodes D13 and D14, that is the capacitor C11
Appears as it is.

That is, the voltage Vs of the capacitor C11 is as follows. _{Vs = V in -V D1 1 +} V D1 3 = V in , however, V _{D1 1,} V _{D1 3} each diode D11,
D13 is a forward voltage of a V _{D1 1} = V _{D1 3.}

The voltage Vs is input to the voltage follower circuit 502 and appears as it is at the point C which is the emitter of the transistor Q56.
03 is output to the output terminal 17 from the transistor Q57.

Next, in the hold period, contrary to the above, a low level voltage is applied to the sample clock input terminal 505 and a high level voltage is applied to the hold clock input terminal 506, so that the transistor Q51 is turned off and the transistor Q52 is turned off. Is turned on. As a result, the diodes D11 to D14
Is in the off state, D15 and D16 are in the on state, and the electric charge charged in the capacitor C11 is held there,
The voltage Vo of the output terminal 507 is also in a hold state.

At this time, a voltage at the same level as the emitter voltage V _C (= Vs) of transistor Q56 is applied to diode D
15 and D16, which are clamped by applying a voltage to the common connection point. The off state of the diodes D11 to D14, the on state of the diodes D15 and D16 are guaranteed, and the saturation state of the transistors Q51 and Q52 and the current sources I21 to I23. Is preventing.

[0010] From the above, the analog signal voltage V _in applied to the input terminal 504, it has been output sample-and-hold the output terminal 507.

The circuit shown in FIG. 5 includes a diode D1
Sample-and-hold is performed by the current switch function of 1 to D16, and high-speed operation is enabled by using a simple voltage follower circuit 502.

[0012]

The above-mentioned FIG.
In the sample and hold circuit 5, the output signal corresponding to the input voltage is a voltage signal, not a current signal. Therefore, when trying to obtain a current signal as an output signal, it is necessary to connect a V / I (voltage → current) conversion circuit to the output terminal 507.

However, this V / I conversion circuit has a problem that an offset occurs because the DC bias voltage is V / I converted when there is no signal. In addition, if a V / I conversion circuit in which the output current becomes zero when only the DC bias is used is used, this problem is eliminated. However, when a small signal is input, the output current signal becomes small, and the high speed operation of the output transistor is impaired. is there.

The present invention has been made in view of the above points, and has as its object to sample and hold an input voltage signal and obtain a current signal as an output signal,
An object of the present invention is to provide a sample-and-hold circuit which does not generate an offset error and realizes high accuracy.

[0015]

SUMMARY OF THE INVENTION According to the present invention, there is provided a sample and hold section for repeating a sampling operation of an input analog voltage by a clock signal and a holding operation for holding a voltage obtained by the sampling operation in a capacitor, and a sample and hold section for holding the sample and hold section. From a high impedance input circuit for inputting the output voltage, a first resistor for converting an output voltage of the high impedance input circuit into a current signal, and a first current output circuit for outputting a current signal generated by the first resistor. A V / I conversion unit, an offset voltage generation circuit for generating the same offset voltage as the offset voltage generated by the sample and hold unit and the V / I conversion unit, and a current signal that outputs the offset voltage generated by the offset voltage generation circuit. The second resistor, which is converted by the second resistor An offset current generation section comprising a second current output circuit for outputting a current signal corresponding to an offset current generated in the I conversion section; and a current signal output from the V / I conversion section and an output from the offset current generation section. The current signal obtained by subtracting the current signal is output as the output signal.

In the present invention, the high input impedance circuit of the V / I converter can be constituted by a source follower circuit composed of a MOS transistor and a voltage follower circuit composed of a MOS transistor for transmitting the voltage output of the source follower circuit.

Further, in the present invention, the offset voltage generating circuit of the offset current generating section may include a circuit equivalent to a sample state of the sample and hold circuit, and a V / I
It can be constituted by a circuit equivalent to the high impedance input circuit of the converter.

[0018]

According to the present invention, a voltage signal obtained by sampling and holding an input voltage is converted into a current signal and output. The offset current generated at this time is separately generated by an offset current generator and subtracted from the output signal. The offset component is canceled from the output current signal.

[0019]

Embodiments of the present invention will be described below. FIG. 1 is a block diagram showing the entirety of the embodiment. 1 is a sample and hold unit for sampling and holding an input analog voltage, and 2 is a V / I converter for converting a voltage signal obtained by the sample and hold unit 1 into a current signal and outputting four identical current signals. 3 is the sample and hold unit 1
And 4 which is equivalent to the offset current generated in the V / I converter 2
An offset current generator 4 for generating current signals and subtracting the current signal from the output current of the V / I converter 2 is an output unit including four output terminals 401 to 404.

FIG. 2 is a circuit diagram showing a specific example of the sample and hold section 1 described above. This circuit comprises a bipolar transistor Q1, Q2 differentially connected, and a diode D1 connected between the collectors of the transistors Q1, Q2.
To D4, a bipolar transistor Q3 having an emitter connected to the collector of the transistor Q1, a bipolar transistor Q4 having an emitter connected to the collector of the transistor Q2, and current sources I1 to I3 (where I1 + I2 = I
3) A voltage source V1 and a hold capacitor C1. 101 is a signal voltage input terminal, 102 is a sampling clock input terminal, 103 is a hold clock input terminal, and 104 is an output terminal.

In this circuit, during the sample period,
When a high-level voltage is applied to the sample clock input terminal 102 and a low-level voltage is applied to the hold clock input terminal 103, the transistor Q1 is turned on and the transistor Q2 is turned off. Therefore, the diode D
1, D2 is turned on, and diodes D3, D4 are turned off.

[0022] Thus, the voltage Vs obtained as voltage V _in that is input to the input terminal 101 to the output terminal 104, V _BEQ3 the base-emitter voltage of the transistors Q3, the forward voltage of the diode D1 when the V _{D1 , Vs = V in -V BEQ3 +} V D1 ···· (1) , and the is charged in the capacitor C1 (sampling).

[0023] In this case, correspond exactly to the rate of change of the input voltage V _in to charge the capacitor C1 is charged and discharged, values of the current source I2 of the capacitor C1 is set.

On the other hand, in the hold period, a low level voltage is applied to the sample clock input terminal 102, a high level voltage is applied to the hold clock input terminal 103, and the transistor Q1 is turned off. The transistor Q2 is turned on.

For this reason, the diodes D3 and D4 are turned on, reverse bias is applied to the diodes D1 and D2, and the diodes D1 and D2 are locked in the off state. The input terminal 101 at the time when the diodes D1 and D2 are turned off (at the time of lock switching) is connected to the capacitor C1.
Voltage V _in of is held.

The transistor Q4 has a diode D
3, D4 is for determining the bias voltage in the ON state. This is because the cathode point of diode D1 (the anode point of diode D3) must be locked to a sufficiently high bias voltage in order to reliably lock diodes D1 and D2 in the off state.

At this time, the reference voltage V1 is determined as follows. When the voltage of the cathode point of the diodes D1 and V _D1C, in order to reliably turn off the diode D1, V than the state at the maximum of the input signal V _in (= V _full)
Since _D must be locked in the high bias or (forward voltage of the diode), a _{V D1C ≧ V full -V BEQ3 +} V D ···· (2). Further, from the level of the diodes D3, D4 and transistors Q4, the reference voltage V1 becomes _{V1 = V D1C -2V D + V} BEQ4 ···· (3). The above V _BEQ3 = V _BEQ4 . Therefore, it is determined as follows from Expressions (2) and (3). V1 ≧ V _full −V _D (4)

FIG. 3 is a circuit diagram showing a specific example of the V / I conversion circuit 2. In FIG. 3, the NMOS transistor Q5
And the current source I4 constitute a source follower circuit 201 having a high input impedance, and the PMOS transistors Q6, Q7,
The diode Q5, the current sources I5 and I6, and the PMOS transistors Q8 to Q11 constitute a high input impedance voltage follower circuit 202. That is, the source follower circuit 201 and the voltage follower circuit 202 constitute a high impedance input circuit. Further, transistors Q12 to Q15, Q16 to Q19, Q20 to Q23,
Q24 to Q27 constitute low input impedance current mirror circuits 203 to 206 (first current output circuits) having an input / output ratio of 1: 1. The resistor R1 is a resistor for voltage / current conversion, and has high input impedance of the source follower transistors Q8 to Q1 of the voltage follower circuit 202.
1 and the power supply terminal _Vcc, and is set to a value that generates the total amount of output current. Reference numeral 207 denotes an input terminal of the hold voltage Vs obtained by the sample hold unit 1, and 208 to 211 denote current output terminals.

In the V / I conversion circuit 2, the input terminal 20
7 receives the sampled and held voltage Vs, the voltage Vs is impedance-converted and output to the source of the transistor Q5 of the source follower circuit 201, and is output from the transistor Q5 of the voltage follower circuit 202.
Input to gate 6. Thereby, the transistor Q7
The same signal voltage _VA having a different DC bias value with respect to the input signal Vs appears at the point A, which is the gate of the input signal Vs. This voltage _VA is converted into a current signal by the resistor R1, branched to the transistors Q8 to Q11, and taken out as current signals by the current mirror circuits 203 to 206 to the output terminals 208 to 211.

[0030] Here, the current i _{2 0 8} output terminals 208,
Same characteristics transistors Q8～Q11, when the same characteristics a current mirror circuit 203 to 206, a current i _{2 0 9} of the other output terminals _{209~211, i 2 1 0, i} 2 1 becomes ₁ the same as, the value is _{, i 2 0 8 = [(} V CC -V A) / R1] / 4 = [V CC - (Vs-V GSQ5 + V GSQ6 + V D5 -V GSQ7)] / 4R1 = [(V CC + V GSQ5 -V GSQ6 _{-V D5 + V GSQ7) -Vs]} / 4R1 = a _{(V OF 0 -Vs) / 4R1} ···· (5). However, V _{OF 0} = V _CC + V _GSQ5 −V _GSQ6 −V _D5
+ V _GSQ7 V _CC is the supply _{voltage, V GSQ5, V GSQ6, V} GSQ7 transistors Q5, Q6, Q7 gate-source voltage of, V _D5 is forward voltage of the diode D5.

Furthermore, the output signal current i _{2 0 8} for the input signal voltage V _in, including sample and hold circuits 1,
From equation (1) and _{(5), i 2 0 8} = [V OF 0 - (V in -V BEQ1 + V D1)] / 4R1 = (V CC + V GSQ5 -V GSQ6 -V D5 + V GSQ7 -V in + V _{BEQ1 -V D1) / 4R1 = [} (V CC + V GSQ5 -V GSQ6 -V D5 + V GSQ7 + V BEQ1 -V D1) -V in] / 4R1 = (V OF 1 -V in) / 4R1 ···· ( 6) _{However, V OF 1 = V CC +} V GSQ5 -V GSQ6 -V D5 + V GSQ7 +
V _BEQ1 −V _D1 .

[0032] Thus, the power supply voltage V _CC and the sample and hold the voltage is converted into a current signal a voltage signal corresponding to the difference between Vs, the output of the larger value the input voltage V _in is smaller current i _{2 0 8} Is obtained. It contains the offset current component "V _{OF 1} / 4R1" This output signal i _{2 0 8.} The diode D5 is a voltage for increasing the DC bias at the point A so that the bias of the transistors of the current mirror circuits 203 to 206 is sufficiently ensured even when the power supply voltage V _CC is low (for example, 5 V). It is for shift.

FIG. 4 shows the offset current component "V _OF "
Is a circuit diagram showing a specific example of the offset current generating unit 3 for canceling ₁ / 4R1. " In FIG. 4, 3
01 is an input terminal to which a DC voltage is applied. Bipolar transistors Q28, Q29, diodes D6, D
7, the voltage source V2 and the current sources I7 to I9 constitute an emitter follower circuit 302, and the NMOS transistor Q30 and the current source I10 constitute a source follower circuit 303. P
MOS transistors Q31 to Q33, diode D8,
The current sources I11 and I12 form a voltage follower circuit 304, and the source voltage of the transistor Q30 is
Output to

The emitter-follower circuit 302 is equivalent to the sample-and-hold operation circuit of the sample and hold section 1 shown in FIG. 2 (a circuit in which the diodes D3 and D4, the transistors Q2 and Q4, the voltage source V1, and the capacitor C1 are deleted).
The source follower circuit 303 is connected to the V / I converter 2
, The voltage follower circuit 304 is equivalent to the voltage follower circuit 202 of the V / I conversion circuit 2, and these constitute a high input impedance circuit.

The resistor R2 is a resistor for voltage / current conversion (R2
= 4 · R1), bipolar transistors Q34 to Q37
Constitutes a current mirror circuit 305 having an input / output ratio of 1: 1. Further, the bipolar transistors Q38 to Q43,
A current mirror circuit 306 composed of resistors R3 to R9 and a PMOS transistor Q44 and having an input / output ratio of 1: 1 outputs the same current as the output current of the current mirror circuit 305 to output terminals 307 to 310 (V / I converter). (Discharge current opposite to 2). The circuit including the resistors R4 and R9 and the transistors Q43 and Q44 is a transistor Q38 to a transistor Q38.
42, for compensating the base current of the PNP transistor 2
It can be replaced with a Darlington circuit composed of individual components.

In the offset current generating section 3,
The application of any of the DC voltage to the input terminal 301, appears at point B voltage V _B corresponding to the DC voltage. The voltage V _B is converted into a current signal by the resistor R2, via respective current mirror circuits 305 and 306, offset current signal for correcting the four output terminals _{307~310 i 3 0 7, i 3} 0 _8, i ₃ is output as _{0 9,} i _{3 1 0.}

[0037] In this embodiment, the output current i _{2 0 8} of V / I converter 2 when the input voltage V _in is the maximum value, i _{2 0 9,} i
Since _{2 1 0,} i _{2 1 1} is a minimum value becomes configuration, in the offset current generating unit 3 applies a DC voltage equivalent to the maximum value of the input voltage V _in to the input terminal 301. That is,
If the input signal voltage V _in that the input DC voltage of the input terminal 301 and the DC voltage V _full maximum value equivalent, current i _{3 0 7} flowing to the output terminal 307, other output terminal 308～
Be identical to the current _{i 3 0 8, i 3 0} 9, i 3 1 0 flowing through the _{310, i 3 0 7 = (} V CC -V B) / R2 = [V CC - (V full -V BEQ2 8 _{+ V D6 -V SGQ3 0 + V} SGQ3 1 + V D8 -V SGQ3 2)] / R2 = a becomes _{(V OF 2 -V full) /} R2 ···· (7).

[0038] _{However, V OF 2 = V CC +} V BEQ2 8 -V D6 + V SGQ3 0 -V SGQ3 1 -
A V _D8 + V _{SGQ3 2.} V _{BEQ2 8} transistor base-emitter voltage of _{Q28, V SGQ3 0, V SGQ3} 1, V SGQ3 2 the transistors Q30, Q31, the gate-source voltage of Q32,
V _D6 and V _D8 are forward voltages of the diodes D6 and D8.

Here, as described above, the emitter follower circuit 302 is equivalent to the circuit of the sample and hold section 1 shown in FIG. 2 at the time of sampling, and the source follower circuit 303 is connected to the source follower circuit 201 of the V / I conversion circuit 2. Since the voltage follower circuit 304 is equivalent to the voltage follower circuit 202 of the V / I conversion circuit 2,
_{V BEQ2 8 = V BEQ3, V} D6 = V D1, V SGQ3 0 = V SGQ5, V
_{SGQ3 1 = V SGQ6, V D8} = V D5, V SGQ3 a ₂ = V _SGQ7, also a 4 · R1 = R2. Therefore, the equation (7) becomes i _{3 0 7} = offset current component equivalent of the _{(V OF 1 -V full) /} 4R1 ···· (8) , and the above formula (3) .

As shown in FIG. 1, the output terminal 208 of the V / I conversion circuit 2 and the output terminal 307 of the offset current generation circuit 3 are commonly connected to the output terminal 401.
The output terminal 401, V / I converting circuit 2 output current obtained from the output terminal 208 (sink current) i _{2 0 8} offset current component obtained from the offset current generating circuit 3 from among (discharge current) i _{3 0 7} current i _{4 0 1} shown in canceled following equation (9) by the subtraction is to be output (suction). This is the same for the current _{i 4 0 2, i 4 0} 3, i 4 0 4 flowing through the other output terminals 402 to 404. _{i 4 0 1 = i 2 0} 8 -i 3 0 7 = (V full -V in) / 4R1 ···· (9)

In this embodiment, since the current mirror circuits 203 to 206 of the V / I converter 2 and the current mirror circuit 306 of the offset current generator 3 are constituted by NPN transistors, they are constituted by PNP transistors. High-speed operation becomes possible as compared with the case where the operation is performed.

In the A / D conversion of the output current obtained from the current terminals 401 to 404, the larger the current value is, the smaller the value is converted to a digital signal. The digital value obtained by this conversion is obtained by converting the current value to A / D
Since only the logic is inverted compared to the converted one,
It is sufficient to take out the inverted logic before the output of the A / D converter that performs the normal A / D conversion.
Since the CL circuit can take out both the normal and inverted signals at the same time, it is not necessary to add a special element if it is configured to take out the inverted signal.

Since the sample and hold circuit of this embodiment has four current signals, it is suitable when a multi-input is required by the A / D conversion method. For example, in a flash (parallel) A / D conversion, n
When obtaining a bit resolution, (2 ⁿ -1) input signals are compared with (2 ⁿ -1) reference values obtained by dividing the full scale value by (2 ⁿ -1), and are converted into digital signals. Is suitable for such a system.

[0044]

As described above, according to the present invention, a voltage signal obtained by sampling and holding an input voltage is converted into a current signal and output. The offset current generated at this time is separately generated by an offset current generating unit to output the output signal. , The offset component is canceled, and a highly accurate sample and hold circuit can be realized.

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of a sample and hold circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram of a sample hold unit.

FIG. 3 is a circuit diagram of a V / I conversion unit.

FIG. 4 is a circuit diagram of an offset current generator.

FIG. 5 is a circuit diagram of a conventional sample and hold circuit.

[Description of Signs] 1: Sample hold unit, 101: input terminal, 102:
Sample clock input terminal, 103: hold clock input terminal, 104: output terminal, 2: V / I converter,
201: source follower circuit, 202: voltage follower circuit, 203 to 206: current mirror circuit, 207:
Input terminals, 208 to 211: output terminals, 3: offset current generator, 301: input terminal, 302: emitter follower circuit, 303: source follower circuit, 304: voltage follower circuit, 304, 305: current mirror circuit,
307 to 310: output terminal, 4: output unit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88 G11C 27/02

Claims (3)

(57) [Claims] A sample-and-hold unit that repeats a sampling operation of an input analog voltage by a clock signal and a holding operation of holding a voltage obtained by the sampling operation in a capacitor; and a high impedance that inputs the voltage held by the sample-and-hold unit. A V / I converter comprising an input circuit, a first resistor for converting an output voltage of the high impedance input circuit into a current signal, and a first current output circuit for outputting a current signal generated by the first resistor; An offset voltage generating circuit for generating the same offset voltage as the offset voltage generated by the sample and hold unit and the V / I converter; and the second resistor for converting the offset voltage generated by the offset voltage generating circuit into a current signal , An offset generated by the second resistor and generated in the V / I converter. And an offset current generating section comprising a second current output circuit for outputting a current signal corresponding to a current signal, and subtracting a current signal output from the V / I conversion section and a current signal output from the offset current generating section. A sample-and-hold circuit characterized in that the current signal obtained is used as an output signal. 2. The high-input impedance circuit of the V / I conversion section includes a source follower circuit composed of a MOS transistor and an M for transmitting a voltage output of the source follower circuit.
2. The sample and hold circuit according to claim 1, comprising a voltage follower circuit comprising an OS transistor. 3. The offset voltage generation circuit of the offset current generation section comprises a circuit equivalent to a sample state of the sample hold circuit and a circuit equivalent to the high impedance input circuit of the V / I conversion section. The sample and hold circuit according to claim 1, wherein: