JPH0851362A - Sample-and-hold circuit - Google Patents

Abstract

PURPOSE:To eliminate off-set difference at the time of executing an output by sampling and holding a voltage signal and outputting it as a current signal. CONSTITUTION:A V/I converting part 2 converting the output voltage of a sample-and-hold part 1 sampling and holding the voltage signal into the current signal is provided. An off-set current generating part 3 generating an off-set signal which is generated in the sample-and-hold part 1 and the V/I converting part 2 as the current signal is provided. The difference between the output current of the V/I converting part 2 and the output current of the off-set current generating part 3 is adopted as an output current signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for sampling and holding an input analog voltage as a pre-processing of A / D conversion for encoding an input analog voltage into a digital code, and particularly to the held voltage. The present invention relates to a sample and hold circuit capable of outputting a current signal without an offset error.

[0002]

2. Description of the Related Art FIG. 5 shows a circuit diagram of a conventional sample-and-hold circuit 4. This is ISSCC90, SESSION 10, An
alog-to-Digital Converter, TPM 10.3, A 10bit 30MHz
two-Step Pallalel BiCMOS ADC with Internal S / H, A
This is the circuit described in Kira Matsuzawa, Minoru Kagawa, el.

The sample and hold circuit 5 shown in FIG. 5 includes diodes D11 to D16, bipolar transistors Q51 to Q57, a PMOS transistor Q58,
Q59, a holding capacitor C11, a phase compensating capacitor C12, and current sources I21 to I27.

Reference numeral 501 is a sample hold unit, 502 is a voltage follower circuit, 503 is an emitter follower circuit, 5
04 is an analog voltage input terminal, 505 is a sample clock input terminal, 506 is a hold clock input terminal,
Reference numeral 507 is an output terminal.

In this circuit, during the sampling period,
A high level voltage is applied to the sample clock input terminal 505,
A low level voltage is applied to the hold clock input terminal 506 to turn on the transistor Q51 and turn off the transistor Q52. As a result, the diodes D11 to D14 are turned on, D15 and D16 are turned off, and the analog voltage V _in input to the input terminal 504 is the common connection point of the diodes D13 and D14, that is, the capacitor C11.
Appears as it is.

That is, the voltage Vs of the capacitor C11 is as follows. Vs = V _in −V _{D1 1} + V _{D1 3} = V _in However, V _{D1 1} and V _{D1 3} are diodes D11 and
It is the forward voltage of D13 and V _{D1 1} = V _{D1 3} .

Further, this voltage Vs is input to the voltage follower circuit 502, appears at the point C which is the emitter of the transistor Q56 as it is, and the emitter follower circuit 5
No. 03 transistor Q57 outputs to the output terminal 17.

In the hold period, conversely to the above, a low level voltage is applied to the sample clock input terminal 505 and a high level voltage is applied to the hold clock input terminal 506 to turn off the transistor Q51 and Q52. Turns on. As a result, the diodes D11 to D14
Is turned off and D15 and D16 are turned on, and the electric charge charged in the capacitor C11 is held there,
The voltage Vo of the output terminal 507 is also in the hold state.

At this time, the voltage at the same level as the emitter voltage V _C (= Vs) of the transistor Q56 is the diode D.
It is applied to the common connection point of 15 and D16 and clamped, so that the off state of the diodes D11 to D14 and the on state of the diodes D15 and D16 are guaranteed, and the saturation state of the transistors Q51 and Q52 and the current sources I21 to I23 is ensured. Is preventing.

From the above, the analog signal voltage V _in input to the input terminal 504 is sampled and held and output to the output terminal 507.

The circuit shown in FIG. 5 has a diode D1.
Sample-and-hold is performed by the current switch actions 1 to D16, and high-speed operation is enabled by using the simple voltage follower circuit 502.

[0012]

By the way, the above-mentioned FIG.
In the sample-and-hold circuit 5 shown in, the output signal with respect to the input voltage is a voltage signal, not a current signal. Therefore, in order to obtain a current signal as an output signal, it is necessary to connect a V / I (voltage → current) conversion circuit to the output terminal 507.

However, this V / I conversion circuit has a problem that an offset occurs because the DC bias voltage is V / I converted when there is no signal. Also, if a V / I conversion circuit in which the output current becomes zero when only a DC bias is used, this problem will be solved, but there is a problem that the output current signal becomes minute when a small signal is input and the high speed of the output transistor is impaired. is there.

The present invention has been made in view of the above points, and an object thereof is to sample and hold an input voltage signal and obtain a current signal as an output signal,
At this time, an offset error does not occur, and it is an object of the present invention to provide a sample-and-hold circuit that realizes high accuracy.

[0015]

According to the present invention, there is provided a sample hold section for repeating a sampling operation of an input analog voltage by a clock signal and a hold operation for holding a voltage obtained by the sampling operation in a capacitor, and a sample hold section. A high impedance input circuit for inputting the generated voltage, a first resistor for converting an output voltage of the high impedance input circuit into a current signal, and a first current output circuit for outputting a current signal generated by the first resistor A V / I conversion section, an offset voltage generation circuit that generates the same offset voltage as the offset voltage generated in the sample hold section and the V / I conversion section, and an offset voltage generated in the offset voltage generation circuit as a current signal. The second resistance, which is generated by the second resistance and And an offset current generator including a second current output circuit that outputs a current signal corresponding to the offset current generated in the I converter, and outputs the current signal output from the V / I converter and the offset current generator. The current signal obtained by subtracting the current signal is used as the output signal.

In the present invention, the high input impedance circuit of the V / I conversion section can be composed of a source follower circuit composed of a MOS transistor and a voltage follower circuit composed of a MOS transistor transmitting a voltage output of the source follower circuit.

Further, in the present invention, the offset voltage generating circuit of the offset current generating unit is equivalent to a circuit equivalent to the sample state of the sample hold circuit, and the V / I.
A circuit equivalent to the high impedance input circuit of the converter can be used.

[0018]

In the present invention, the voltage signal obtained by sampling and holding the input voltage is converted into the current signal and output. The offset current generated at this time is separately generated by the offset current generator and subtracted from the output signal. The offset component is canceled from the output current signal.

[0019]

Embodiments of the present invention will be described below. FIG. 1 is a block diagram showing the whole of the embodiment. Reference numeral 1 is a sample / hold unit for sampling and holding an input analog voltage, and 2 is a V / I conversion unit for converting a voltage signal obtained by the sample / hold unit 1 into a current signal and outputting four identical current signals. 3 is a sample hold unit 1
And 4 which is equivalent to the offset current generated in the V / I converter 2.
An offset current generator 4 for generating a current signal and subtracting it from the output current of the V / I converter 2 is an output unit composed of four output terminals 401 to 404.

FIG. 2 is a circuit diagram showing a concrete example of the sample hold unit 1 described above. This circuit comprises a differentially connected bipolar transistor Q1, Q2 and a diode D1 connected between the collectors of the respective transistors Q1, Q2.
˜D4, a bipolar transistor Q3 whose emitter is connected to the collector of the transistor Q1, a bipolar transistor Q4 whose emitter is connected to the collector of the transistor Q2, and current sources I1 to I3 (where I1 + I2 = I
3) A voltage source V1 and a holding capacitor C1. 101 is a signal voltage input terminal, 102 is a sample clock input terminal, 103 is a hold clock input terminal, and 104 is an output terminal.

In this circuit, during the sampling period,
A high level voltage is applied to the sample clock input terminal 102 and a low level voltage is applied to the hold clock input terminal 103 to turn on the transistor Q1 and turn off the transistor Q2. Therefore, the diode D
1, D2 are turned on, and the diodes D3, D4 are turned off.

[0022] Thus, the voltage Vs obtained as voltage V _in that is input to the input terminal 101 to the output terminal 104, V _BEQ3 the base-emitter voltage of the transistors Q3, the forward voltage of the diode D1 when the V _D1 , Vs = V _in −V _BEQ3 + V _D1 (1) and the capacitor C1 is charged (sampled).

At this time, the value of the capacitor C1 and the value of the current source I2 are set so that the capacitor C1 is charged and discharged _{in accordance with} the changing speed of the input voltage V _in exactly.

On the other hand, in the hold period, conversely to the above, a low level voltage is applied to the sample clock input terminal 102, a high level voltage is applied to the hold clock input terminal 103, and the transistor Q1 is turned off. The transistor Q2 is turned on.

Therefore, the diodes D3 and D4 are turned on, the diodes D1 and D2 are reverse-biased, and the diodes D1 and D2 are locked in the off state. The capacitor C1 has an input terminal 101 at the time when the diodes D1 and D2 are turned off (lock switching time).
Voltage V _in is held.

The transistor Q4 is a diode D
3 and D4 are for determining the bias voltage in the ON state. This is because the cathode point of the diode D1 (the anode point of the diode D3) must be locked to a sufficiently high bias voltage in order to reliably lock the diodes D1 and D2 in the off state.

At this time, the reference voltage V1 is determined as follows. _Assuming that the voltage at the cathode point of the diode D1 is V _D1C , in order to reliably turn off the diode D1, V _D is more than the maximum (= V _full ) state of the input signal V _in.
Since it must be locked to a bias higher than _D (forward voltage of the diode), V _D1C ≧ V _full −V _BEQ3 + V _D (2) Further, based on the levels of the diodes D3, D4 and the transistor Q4, the reference voltage V1 becomes V1 = V _D1C −2V _D + V _BEQ4 (3) The above V _BEQ3 = V _BEQ4 . Therefore, it is determined from the equations (2) and (3) as follows. V1 ≧ V _full −V _D ··· (4)

FIG. 3 is a circuit diagram showing a concrete example of the V / I conversion circuit 2. In FIG. 3, the NMOS transistor Q5
And the current source I4 constitute a source follower circuit 201 having high input impedance, and PMOS transistors Q6, Q7,
The diode Q5, the current sources I5 and I6, and the PMOS transistors Q8 to Q11 form a voltage follower circuit 202 with high input impedance. That is, the source follower circuit 201 and the voltage follower circuit 202 form a high impedance input circuit. Further, transistors Q12 to Q15, Q16 to Q19, Q20 to Q23,
Q24 to Q27 form low input impedance current mirror circuits 203 to 206 (first current output circuits) having an input / output ratio of 1: 1. The resistor R1 is a resistor for voltage / current conversion, and is a source follower transistor Q8-Q1 of high input impedance of the voltage follower circuit 202.
It is connected between the source of No. 1 and the power supply terminal V _CC, and is set to a value that generates the total amount of output current. Reference numeral 207 is an input terminal for the hold voltage Vs obtained by the sample hold unit 1, and 208 to 211 are current output terminals.

In the V / I conversion circuit 2, the input terminal 20
When the sample-and-hold voltage Vs described above is input to 7, the voltage Vs is impedance-converted and output to the source of the transistor Q5 of the source follower circuit 201, and the transistor Q5 of the voltage follower circuit 202 is output.
Input to the gate of 6. As a result, the transistor Q7
The same signal voltage V _A having different DC bias values with respect to the input signal Vs appears at the point A which is the gate of. The voltage V _A is converted into a current signal by the resistor R1, branched into the transistors Q8 to Q11, and taken out as current signals by the current mirror circuits 203 to 206 to the output terminals 208 to 211.

[0030] Here, the current i _{2 0 8} output terminals 208,
Same characteristics transistors Q8～Q11, when the same characteristics a current mirror circuit 203 to 206, a current i _{2 0 9} of the other output terminals _{209~211, i 2 1 0, i} 2 1 becomes ₁ the same as, the value is _{, i 2 0 8 = [(} V CC -V A) / R1] / 4 = [V CC - (Vs-V GSQ5 + V GSQ6 + V D5 -V GSQ7)] / 4R1 = [(V CC + V GSQ5 -V GSQ6 −V _D5 + V _GSQ7 ) −Vs] / _4R1 = (V _{OF 0} −Vs) / 4R1 ... (5) However, V _{OF 0} = V _CC + V _GSQ5 −V _GSQ6 −V _D5
+ V _GSQ7 V _CC is the power supply voltage, V _GSQ5 , V _GSQ6 and V _GSQ7 are the gate-source voltage of the transistors Q5, Q6 and Q7, and V _D5 is the forward voltage of the diode D5.

Furthermore, the output signal current i _{2 0 8} for the input signal voltage V _in, including sample and hold circuits 1,
From equation (1) and _{(5), i 2 0 8} = [V OF 0 - (V in -V BEQ1 + V D1)] / 4R1 = (V CC + V GSQ5 -V GSQ6 -V D5 + V GSQ7 -V in + V _{BEQ1 -V D1) / 4R1 = [} (V CC + V GSQ5 -V GSQ6 -V D5 + V GSQ7 + V BEQ1 -V D1) -V in] / 4R1 = (V OF 1 -V in) / 4R1 ···· ( 6) However, V _{OF 1} = V _CC + V _GSQ5 −V _GSQ6 −V _D5 + V _GSQ7 +
It becomes V _BEQ1- V _D1 .

[0032] Thus, the power supply voltage V _CC and the sample and hold the voltage is converted into a current signal a voltage signal corresponding to the difference between Vs, the output of the larger value the input voltage V _in is smaller current i _{2 0 8} Is obtained. It contains the offset current component "V _{OF 1} / 4R1" This output signal i _{2 0 8.} The diode D5 is a voltage for increasing the DC bias at the point A so that the bias of the transistors of the current mirror circuits 203 to 206 is sufficiently secured even when the power supply voltage V _CC is a low voltage (for example, 5 V). It is for shifting.

FIG. 4 shows the offset current component "V _OF
It is a circuit diagram which shows the specific example of the offset current generation part 3 for canceling " ₁ / 4R1." In FIG. 4, 3
01 is an input terminal to which a DC voltage is applied. Bipolar transistors Q28, Q29, diodes D6, D
7, the voltage source V2, and the current sources I7 to I9 form an emitter follower circuit 302, and the NMOS transistor Q30 and the current source I10 form a source follower circuit 303. P
MOS transistors Q31 to Q33, diode D8,
The current sources I11 and I12 form a voltage follower circuit 304, and the source voltage of the transistor Q30 is set to point B.
Output to.

The emitter follower circuit 302 is equivalent to the operation circuit (the circuit in which the diodes D3 and D4, the transistors Q2 and Q4, the voltage source V1 and the capacitor C1 are removed) at the time of sampling of the sample and hold unit 1 shown in FIG.
Further, the source follower circuit 303 is connected to the V / I conversion unit path 2 described above.
Of the source follower circuit 201, the voltage follower circuit 304 is equivalent to the voltage follower circuit 202 of the V / I conversion circuit 2, and these constitute a high input impedance circuit.

The resistor R2 is a resistor for converting voltage / current (R2
= 4 · R1), bipolar transistors Q34 to Q37
Constitutes a current mirror circuit 305 having an input / output ratio of 1: 1. Further, the bipolar transistors Q38 to Q43,
The current mirror circuit 306 having the input / output ratio of 1: 1 composed of the resistors R3 to R9 and the PMOS transistor Q44 branches the same current as the output current of the current mirror circuit 305 to the output terminals 307 to 310 (V / I converter). The discharge current is the opposite of 2. The circuit formed by the resistors R4 and R9 and the transistors Q43 and Q44 is the transistor Q38 to
42 for compensating the base current of PNP transistor 2
It can be replaced with a Darlington circuit composed of individual pieces.

In this offset current generator 3,
When an arbitrary DC voltage is applied to the input terminal 301, the voltage V _B corresponding to this DC voltage appears at the point B. The voltage V _B is converted into a current signal by the resistor R2, and the offset current signals i _{3 0 7} and i _{3 0} for correction are supplied to the four output terminals 307 to 310 via the current mirror circuits 305 and 306, respectively. _8, i ₃ is output as _{0 9,} i _{3 1 0.}

[0037] In this embodiment, the output current i _{2 0 8} of V / I converter 2 when the input voltage V _in is the maximum value, i _{2 0 9,} i
_{Since 2 1 0} and i _{2 1 1} have the minimum values, the offset current generator 3 applies a DC voltage corresponding to the maximum value of the input voltage V _in to the input terminal 301. That is,
If the input signal voltage V _in that the input DC voltage of the input terminal 301 and the DC voltage V _full maximum value equivalent, current i _{3 0 7} flowing to the output terminal 307, other output terminal 308～
Be identical to the current _{i 3 0 8, i 3 0} 9, i 3 1 0 flowing through the _{310, i 3 0 7 = (} V CC -V B) / R2 = [V CC - (V full -V BEQ2 8 + V _D6 −V _{SGQ3 0} + V _{SGQ3 1} + V _D8 −V _{SGQ3 2} )] / R2 = (V _{OF 2} −V _full ) / R2 ... (7).

However, V _{OF 2} = V _CC + V _{BEQ2 8} −V _D6 + V _{SGQ3 0} −V _{SGQ3 1} −
V _D8 + V _{SGQ3 2} . V _{BEQ2 8} is the base-emitter voltage of the transistor Q28, V _{SGQ3 0} , V _{SGQ3 1} , and V _{SGQ3 2} are the gate-source voltages of the transistors Q30, Q31, and Q32.
V _D6 and V _D8 are forward voltages of the diodes D6 and D8.

Here, as described above, the emitter follower circuit 302 is equivalent to the sampling circuit of the sample and hold unit 1 shown in FIG. 2, and the source follower circuit 303 is the same as the source follower circuit 201 of the V / I conversion circuit 2. Since the voltage follower circuit 304 is equivalent to the voltage follower circuit 202 of the V / I conversion circuit 2, the voltage follower circuit 304 is equivalent.
V _{BEQ2 8} = V _BEQ3 , V _D6 = V _D1 , V _{SGQ3 0} = V _SGQ5 , V
_{SGQ3 1} = V _SGQ6 , V _D8 = V _D5 , V _{SGQ3 2} = V _SGQ7 , and 4 · R1 = R2. Therefore, the above equation (7) becomes i _{3 0 7} = (V _{OF 1} −V _full ) / 4R ₁ (8), which is equivalent to the offset current component in the above equation (3). .

As shown in FIG. 1, the output terminal 208 of the V / I conversion circuit 2 and the output terminal 307 of the offset current generating circuit 3 are commonly connected to the output terminal 401.
The output terminal 401, V / I converting circuit 2 output current obtained from the output terminal 208 (sink current) i _{2 0 8} offset current component obtained from the offset current generating circuit 3 from among (discharge current) i _{3 The} current i _{4 0 1} shown in the following equation (9) in which _{0 7} is canceled by subtraction is output (sucked). This is the same for the current _{i 4 0 2, i 4 0} 3, i 4 0 4 flowing through the other output terminals 402 to 404. i _{4 0 1} = i _{2 0 8} −i _{3 0 7} = (V _full −V _in ) / 4R1 ... (9)

In this embodiment, since the current mirror circuits 203 to 206 of the V / I converter 2 and the current mirror circuit 306 of the offset current generator 3 are composed of NPN transistors, they are composed of PNP transistors. High-speed operation becomes possible compared to the case.

The A / D conversion of the output current obtained at the current terminals 401 to 404 is converted into a digital signal showing a smaller value as the current value increases. The digital value obtained by this conversion is the same as the current value in the A / D
Since the logic is only inverted compared to the converted one,
It is only necessary to take out the inversion logic before the output of the A / D converter that performs the normal A / D conversion, and especially E used for high-speed processing.
Since the CL circuit can take out both the forward rotation signal and the inverted signal at the same time, it is not necessary to add a special element if the inverted signal is taken out.

Since the sample-and-hold circuit of this embodiment has four current signals, it is suitable when a large number of inputs are required by the A / D conversion method. For example, in flash (parallel) A / D conversion, n
When obtaining bit resolution, (2 ⁿ -1) input signals are compared with (2 ⁿ -1) reference values obtained by dividing the full-scale value into (2 ⁿ -1) and converted into digital signals. However, it is suitable for such a system.

[0044]

As described above, according to the present invention, a voltage signal obtained by sampling and holding an input voltage is converted into a current signal and is output. The offset current generated at this time is separately generated by the offset current generator, and the output signal is generated. , The offset component is canceled and a highly accurate sample and halt circuit can be realized.

[Brief description of drawings]

FIG. 1 is an overall circuit diagram of a sample-and-hold circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a sample hold unit.

FIG. 3 is a circuit diagram of a V / I conversion unit.

FIG. 4 is a circuit diagram of an offset current generator.

FIG. 5 is a circuit diagram of a conventional sample-and-hold circuit.

[Explanation of symbols]

1: Sample and hold unit, 101: input terminal, 102:
Sample clock input terminal, 103: Hold clock input terminal, 104: Output terminal, 2: V / I converter,
201: Source follower circuit, 202: Voltage follower circuit, 203 to 206: Current mirror circuit, 207:
Input terminals, 208 to 211: output terminals, 3: offset current generating unit, 301: input terminal, 302: emitter follower circuit, 303: source follower circuit, 304: voltage follower circuit, 304, 305: current mirror circuit,
307 to 310: output terminals, 4: output unit.

Claims (3)

[Claims] 1. A sample hold unit for repeating a sampling operation of an input analog voltage by a clock signal and a hold operation for holding a voltage obtained by the sampling operation in a capacitor, and a high impedance for inputting the voltage held by the sample hold unit. An input circuit, a first resistor for converting an output voltage of the high impedance input circuit into a current signal, and a V / I conversion unit including a first current output circuit for outputting a current signal generated by the first resistor; An offset voltage generation circuit that generates the same offset voltage as the offset voltage generated in the sample hold unit and the V / I conversion unit, and the second resistor that converts the offset voltage generated in the offset voltage generation circuit into a current signal. , The offset generated by the second resistor and generated in the V / I converter. And an offset current generation unit including a second current output circuit that outputs a current signal corresponding to the current, and subtracts the current signal output from the V / I conversion unit and the current signal output from the offset current generation unit. A sample-and-hold circuit characterized in that the output current signal is used as the output signal. 2. The high input impedance circuit of the V / I conversion section transmits a source follower circuit composed of a MOS transistor and a voltage output of the source follower circuit.
The sample-and-hold circuit according to claim 1, comprising a voltage follower circuit including an OS transistor. 3. The offset voltage generating circuit of the offset current generating section comprises a circuit equivalent to the sampled state of the sample and hold circuit and a circuit equivalent to the high impedance input circuit of the V / I conversion section. The sample-and-hold circuit according to claim 1.