JP2561095B2 - Field effect semiconductor device - Google Patents
Field effect semiconductor deviceInfo
- Publication number
- JP2561095B2 JP2561095B2 JP62212699A JP21269987A JP2561095B2 JP 2561095 B2 JP2561095 B2 JP 2561095B2 JP 62212699 A JP62212699 A JP 62212699A JP 21269987 A JP21269987 A JP 21269987A JP 2561095 B2 JP2561095 B2 JP 2561095B2
- Authority
- JP
- Japan
- Prior art keywords
- buffer layer
- channel layer
- semiconductor device
- field effect
- effect semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 230000005669 field effect Effects 0.000 title claims description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 9
- 239000000969 carrier Substances 0.000 claims description 8
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 240000002329 Inga feuillei Species 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
Description
【発明の詳細な説明】 〔概要〕 高周波用或いは高電力用或いは高速スイッチング用と
して用いられている電界効果半導体装置の改良に関し、 バッファ層を有するMESFETに極めて簡単な改変を施す
ことに依って、前掲の高周波特性など諸特性を向上する
ことを目的とし、 半絶縁性GaAs基板上に形成されキャリヤに対するバリ
ヤとして作用するノン・ドープのバッファ層と、該バッ
ファ層上に形成され該バッファ層との界面近傍から表面
に向かってグレーデッドにInが導入され且つ表面では前
記Inの組成が略零であるInXGa1-XAsチャネル層とを備え
るように構成する。DETAILED DESCRIPTION OF THE INVENTION [Outline] Regarding improvement of a field-effect semiconductor device used for high frequency, high power, or high speed switching, by applying an extremely simple modification to a MESFET having a buffer layer, For the purpose of improving various characteristics such as the above-mentioned high frequency characteristics, a non-doped buffer layer formed on a semi-insulating GaAs substrate and acting as a barrier for carriers, and a non-doped buffer layer formed on the buffer layer In is introduced from the vicinity of the interface toward the surface in a graded manner, and the surface is provided with an In X Ga 1-X As channel layer in which the composition of In is approximately zero.
本発明は、高周波用或いは高電力用或いは高速スイッ
チング用として賞用されている電界効果半導体装置の改
良に関する。The present invention relates to an improvement of a field effect semiconductor device which is prized for high frequency, high power or high speed switching.
従来、MESFET（metal semiconductor field effect t
ransistor）と呼ばれる電界効果半導体装置が多用され
ている。Conventionally, MESFET (metal semiconductor field effect t)
ransistor) field-effect semiconductor device is often used.
そのような電界効果半導体装置に於いて、半絶縁性基
板とチャネル層との間に、キャリヤに対しバリヤとして
機能するバッファ層を介在させることに依って、チャネ
ル層から基板に漏洩する電流を低減し、高周波用或いは
高電力用或いは高速スイッチング用としての性能を向上
させたものが知られている（要すれば、「IEEE ELECTRO
N DEVICE LETTERS,VOL.EDL−5,No1,JANUARY 1984 pp.3
−５」、を参照）。In such a field effect semiconductor device, by interposing a buffer layer that functions as a barrier for carriers between the semi-insulating substrate and the channel layer, the current leaking from the channel layer to the substrate is reduced. However, those having improved performance for high frequency, high power, or high speed switching are known (if necessary, "IEEE ELECTRO
N DEVICE LETTERS, VOL.EDL−5, No1, JANUARY 1984 pp.3
-5 ").
第８図はそのような電界効果半導体装置の要部切断側
面図を表している。FIG. 8 shows a cutaway side view of a main part of such a field effect semiconductor device.
図に於いて、１は半絶縁性GaAs基板、２はｉ型AlGaAa
バッファ層、３はｎ型GaAsチャネル層、４はゲート電
極、５はソース電極、６はドレイン電極をそれぞれ示し
ている。In the figure, 1 is a semi-insulating GaAs substrate, 2 is i-type AlGaAa
A buffer layer, 3 is an n-type GaAs channel layer, 4 is a gate electrode, 5 is a source electrode, and 6 is a drain electrode.
この電界効果半導体装置に於いては、ｉ型AlGaAsバッ
ファ層２が電子に対するバリヤの働きをする為、電子は
ｎ型GaAsチャネル層３のみを走行することになり、従っ
て、チャネル層３から基板１に漏洩する電流は殆ど無
く、高周波用、高電力用、高速スイッチング用として優
れた特性をもっている。In this field effect semiconductor device, since the i-type AlGaAs buffer layer 2 acts as a barrier against electrons, the electrons travel only through the n-type GaAs channel layer 3, and therefore the channel layer 3 to the substrate 1 There is almost no leakage current, and it has excellent characteristics for high frequency, high power, and high speed switching.
前記説明したように、バッファ層を有するMESFETは、
高周波特性、高電力性、高速スイッチング特性の全ての
面で通常のMESFETに比較して優れているが、これ等の諸
特性を更に向上できれば大変好ましいことである。As described above, the MESFET having the buffer layer is
It is superior to ordinary MESFETs in all aspects of high-frequency characteristics, high power characteristics, and high-speed switching characteristics, but it is highly desirable if these characteristics can be further improved.
本発明は、前記説明したバッファ層を有するMESFETに
極めて簡単な改変を施すことに依って、前掲の高周波特
性など諸特性を向上しようとする。The present invention seeks to improve various characteristics such as the above-mentioned high frequency characteristics by making a very simple modification to the MESFET having the buffer layer described above.
本発明に依る電界効果半導体装置に於いては、半絶縁
性GaAs基板（例えば半絶縁性GaAs基板１）上に形成され
キャリヤに対するバリヤとして作用するノン・ドープの
バッファ層（例えばｉ型AlGaAsバッファ層２）と、該バ
ッファ層上に形成され該バッファ層との界面近傍から表
面に向かってグレーデッドにInが導入され且つ表面では
前記Inの組成が略零であるInXGa1-XAsチャネル層（例え
ばｎ型gInXGa1-XAsチャネル層７）とを備えている。In the field effect semiconductor device according to the present invention, a non-doped buffer layer (for example, i-type AlGaAs buffer layer) formed on a semi-insulating GaAs substrate (for example, semi-insulating GaAs substrate 1) and acting as a barrier for carriers is provided. 2) and an In X Ga 1-X As channel in which In is introduced into the buffer layer in a graded manner from the vicinity of the interface with the buffer layer toward the surface and the composition of In is substantially zero on the surface. Layer (for example, n-type gIn X Ga 1-X As channel layer 7).
前記手段を採ることに依り、チャネル層に於けるキャ
リヤの移動度は高くなり、また、チャネル層からバッフ
ァ層へのキャリヤの漏洩は殆ど無くなり、従って、高周
波特性、高電力特性、高速スイッチング特性は更に向上
し、高い電圧を印加した状態でも安定に動作することが
できる。By adopting the above means, the mobility of carriers in the channel layer becomes high, and the leakage of carriers from the channel layer to the buffer layer is almost eliminated. Therefore, high frequency characteristics, high power characteristics, and high speed switching characteristics are It is further improved, and stable operation is possible even when a high voltage is applied.
第１図は本発明一実施例の要部切断側面図を表し、第
８図に於いて用いた記号と同記号は同部分を示すか或い
は同じ意味を持つものとする。FIG. 1 is a sectional side view of an essential part of one embodiment of the present invention, and the same symbols as those used in FIG. 8 indicate the same parts or have the same meanings.
図に於いて、７はｎ型gInXGa1-XAsチャネル層を示し
ている。尚、ｇは傾斜組成（graded composition）を有
していることを指示するものとする。In the figure, 7 indicates an n-type gIn X Ga 1-X As channel layer. Note that g indicates that it has a graded composition.
図示例の各部分に関する主要なデータを例示すると次
の通りである。The main data regarding each part of the illustrated example is as follows.
（１） バッファ層について 厚さ:1000〔Å〕 （２） チャネル層７について 厚さ:500〔Å〕 不純物:Si 不純物濃度:4×1017〔cm-3〕 （３） ゲート電極４について 材料:Al 厚さ:4000〔Å〕 ゲート長:0.25〔μｍ〕 （４） ソース電極５及びドレイン電極６について 材料:AuGe/Au 厚さ:200〔Å〕/3800〔Å〕 本実施例が第８図に見られる従来例と相違する点は、
チャネル層にInを導入し、しかも、そのInの分布をバッ
ファ層２とチャネル層７との界面から表面に向かうにつ
れて低減させるグレーデッドとし、特に、チャネル層７
の表面ではInが殆ど存在しない状態にしたことである。(1) About buffer layer Thickness: 1000 [Å] (2) About channel layer 7 Thickness: 500 [Å] Impurity: Si Impurity concentration: 4 × 10 17 [cm -3 ] (3) About gate electrode 4 Material : Al thickness: 4000 [Å] Gate length: 0.25 [μm] (4) Source electrode 5 and drain electrode 6 Material: AuGe / Au Thickness: 200 [Å] / 3800 [Å] This embodiment is the eighth The difference from the conventional example seen in the figure is
The In is introduced into the channel layer, and the distribution of In is reduced from the interface between the buffer layer 2 and the channel layer 7 toward the surface.
It means that In is almost absent on the surface of.
第２図は第１図に見られる本発明一実施例に対応する
Inの組成変化、即ち、ｘ値の変化を表す線図である。FIG. 2 corresponds to an embodiment of the present invention shown in FIG.
It is a diagram showing composition change of In, that is, change of x value.
図から判るように、バッファ層２とチャネル層７との
界面近傍ではチャネル層７はInを約10〔％〕程度含有
し、そこから表面に向かうにつれてInの含有量は低減さ
れ、表面近傍では殆ど零になっていることが認識されよ
う。As can be seen from the figure, the channel layer 7 contains about 10% [In] in the vicinity of the interface between the buffer layer 2 and the channel layer 7, and the In content decreases from the surface toward the surface. It will be recognized that it is almost zero.
このように表面近傍でIn組成を零にする理由は、InGa
Asに対して良好なショットキ・バリヤを生成し得る金属
が存在せず、従って、ショットキのゲート電極４に対応
する半導体結晶としてはGaAsの方が好ましいことに依
る。The reason for making the In composition zero near the surface is that InGa
This is because there is no metal capable of forming a good Schottky barrier against As, and therefore GaAs is preferable as the semiconductor crystal corresponding to the Schottky gate electrode 4.
また、In組成をグレーデッドにする理由は、バッファ
層２をなすAlGaAsと、チャネル層の一部をなすInGaAs
と、同じくチャネル層の一部をなすGaAsとの間に存在す
る格子定数の相違に起因する格子歪を有限な距離で緩和
する為である。The reason for making the In composition graded is that AlGaAs forming the buffer layer 2 and InGaAs forming a part of the channel layer.
And similarly, the lattice strain caused by the difference in lattice constant existing between GaAs forming a part of the channel layer is relaxed at a finite distance.
このようなことまでしてチャネル層３にInを導入する
のは、InGaAsがGaAsに比較してキャリヤ移動度が大きい
こと、バッファ層２のバリヤ高はInGaAs/AlGaAs系のほ
うがGaAs/AlGaAs系に比較して高いことに依る。The reason why In is introduced into the channel layer 3 is that InGaAs has a higher carrier mobility than GaAs, and the barrier height of the buffer layer 2 is GaAs / AlGaAs in InGaAs / AlGaAs. It depends on what is high in comparison.
第３図は第１図に見られる実施例のエネルギ・バンド
・ダイヤグラムを表し、第１図に於いて用いた記号と同
記号は同部分を示すか或いは同じ意味を持つものとす
る。尚、図では簡明にする為、伝導帯の底のみを示して
いる。FIG. 3 shows an energy band diagram of the embodiment shown in FIG. 1, wherein the same symbols as those used in FIG. 1 indicate the same parts or have the same meanings. In the figure, only the bottom of the conduction band is shown for the sake of simplicity.
図に於いて、ECは伝導帯の底、EFフェルミ・レベル、
ΔECはバッファ層２のバリヤ高をそれぞれ示し、そし
て、破線はGaAs/AlGaAs系の伝導帯の底を示している。In the figure, E C is the bottom of the conduction band, E F Fermi level,
ΔE C indicates the barrier height of the buffer layer 2, and the broken line indicates the bottom of the conduction band of the GaAs / AlGaAs system.
図から明らかなように、バッファ層２のバリヤ高はIn
GaAs/AlGaAs系が遥かに高く、従って、チャネル層７
（或いは３）から基板１への電子の漏洩は、InGaAs/AlG
aAs系の方が少ないことになる。As is clear from the figure, the barrier height of the buffer layer 2 is In
The GaAs / AlGaAs system is much higher, so the channel layer 7
(Or 3) electron leakage from substrate 1 to InGaAs / AlG
There are less aAs systems.
第４図は第１図に見られる実施例に於ける内部の電子
の分布状態を表す要部切断側面図であり、そして、第５
図は従来例に於ける同様な要部切断側面図である。尚、
各図はモンテカルロ粒子シミュレーションに依って得ら
れたものであり、そして、第１図及び第８図に於いて用
いた記号と同記号は同部分を示すか或いは同じ意味を持
つものとする。FIG. 4 is a cutaway side view of an essential part showing an internal electron distribution state in the embodiment shown in FIG. 1, and FIG.
The figure is a similar cutaway side view of a main part in the conventional example. still,
Each figure was obtained by Monte Carlo particle simulation, and the same symbols as those used in FIGS. 1 and 8 indicate the same parts or have the same meanings.
図では電子の分布を砂地模様で表してあり、これから
看取できるように、本発明一実施令に於いては、チャネ
ル層７からバッファ層２に対する電子の漏洩は充分に抑
制され著しく少ないが、従来例においては、かなり多く
の漏洩が見られる。In the figure, the distribution of electrons is represented by a sandy pattern. As can be seen from this, in the first embodiment of the present invention, the leakage of electrons from the channel layer 7 to the buffer layer 2 is sufficiently suppressed, but In the conventional example, quite a lot of leaks are seen.
第６図は第１図に見られる実施例に於けるドレイン電
圧VDS対ドレイン電流IDSの関係を表す線図であり、そし
て、第７図は従来例に於ける同様な線図である。FIG. 6 is a diagram showing the relationship between the drain voltage V DS and the drain current I DS in the embodiment shown in FIG. 1, and FIG. 7 is a similar diagram in the conventional example. .
各図では、横軸にドレイン電圧VDSを、また、縦軸に
ドレイン電流IDSをそれぞれ採ってある。In each figure, the horizontal axis represents the drain voltage V DS , and the vertical axis represents the drain current I DS .
図から判るように、本発明一実施例は、相互コンダク
タンスgmが従来例に比較して高く、そして、電流飽和の
傾向も良好な状態を示し、ピンチ・オフ特性（電流遮断
特性）も改善されていることが理解されよう。斯かる利
点は、ゲート長が短くなる程顕著になる。As can be seen from the figure, in one embodiment of the present invention, the transconductance g m is higher than that in the conventional example, the tendency of current saturation is also good, and the pinch-off characteristic (current cutoff characteristic) is improved. It is understood that it is done. Such an advantage becomes more remarkable as the gate length becomes shorter.
ところで、本発明では、チャネル層７に導入するInを
最高で10〔％〕程度、また、最低で５〔％〕程度とした
が、これは、約10〔％〕程度を越えると格子欠陥が発生
する率が多くなるところから選定された値であり、そし
て、約５〔％〕程度を下回るとInを導入した効果が希薄
になることに由来している。このようなことから、本発
明を実施するには、チャネル層７にInを導入するには、
格子欠陥が問題にならない程度で、しかも、導入したこ
とに依る効果が現れる程度の範囲で組成を選択すること
が重要である。By the way, in the present invention, In introduced into the channel layer 7 is set to about 10% at the maximum and about 5% at the minimum. It is a value selected from the fact that the rate of occurrence is large, and it is derived from the fact that the effect of introducing In becomes weaker when it falls below about 5%. From the above, in order to carry out the present invention, in order to introduce In into the channel layer 7,
It is important to select the composition within a range in which the lattice defect does not cause a problem and the effect due to the introduction is exhibited.
前記実施例に於いては、基板１として半絶縁性GaAs
を、また、バッファ層２としてｉ型AlGaAsを採用してい
るが、これは、基板１の材料をInPに、そして、バッフ
ァ層２のそれをｉ型AlInAsにそれぞれ代替しても同効で
あることが確認されている。In the above embodiment, the substrate 1 is semi-insulating GaAs.
In addition, i-type AlGaAs is adopted as the buffer layer 2. This has the same effect even if the material of the substrate 1 is replaced with InP and that of the buffer layer 2 is replaced with i-type AlInAs. It has been confirmed.
本発明に依る電界効果半導体装置に於いては、バッフ
ァ層の上に形成されるチャネル層の材料にInXGa1-XAsを
用い、しかも、Inの組成がバッファ層との界面近傍から
表面に向かうにつれて小さくなるようにしている。In the field effect semiconductor device according to the present invention, In X Ga 1-X As is used as the material of the channel layer formed on the buffer layer, and the composition of In changes from the vicinity of the interface with the buffer layer to the surface. It becomes smaller as it goes to.
前記構成を採ることに依り、チャネル層に於けるキャ
リヤの移動度は高くなり、また、チャネル層からバッフ
ァ層へのキャリヤの漏洩は殆ど無くなり、従って、高周
波特性、高電力特性、高速スイッチング特性は更に高上
し、高い電圧を印加した状態でも安定に動作することが
できる。By adopting the above configuration, the mobility of carriers in the channel layer becomes high, and the leakage of carriers from the channel layer to the buffer layer is almost eliminated. Therefore, high frequency characteristics, high power characteristics, and high speed switching characteristics are Further, it is possible to operate stably even when the voltage is further increased and a high voltage is applied.
第１図は本発明一実施例の要部切断側面図、第２図は第
１図に見られる実施例に於けるInの組成に関する線図、
第３図は第１図に見られる実施例のエネルギ・バンド・
ダイヤグラム、第４図は第１図に見られる実施例の内部
に於ける電子の分布状態を説明する為の要部切断側面
図、第５図は従来例の内部に於ける電子の分布状態を説
明する為の要部切断側面図、第６図は第１図に見られる
実施例をドレイン電圧対ドレイン電流の関係を説明する
為の線図、第７図は従来例のドレイン電圧対ドレイン電
流の関係を説明する為の線図、第８図は従来例の要部切
断側面図をそれぞれ表している。 図に於いて、１は半絶縁性GaAs基板、２はｉ型AlGaAsバ
ッファ層、３はｎ型GaAsチャネル層、４はゲート電極、
５はソース電極、６はドレイン電極、７はｎ型gInXGa
1-XAsチャネル層をそれぞれ示している。FIG. 1 is a side view of an essential part of an embodiment of the present invention, and FIG. 2 is a diagram relating to the composition of In in the embodiment shown in FIG.
FIG. 3 shows the energy band of the embodiment shown in FIG.
A diagram, FIG. 4 is a sectional side view of an essential part for explaining an electron distribution state inside the embodiment shown in FIG. 1, and FIG. 5 shows an electron distribution state inside the conventional example. FIG. 6 is a cutaway side view of an essential part for explaining, FIG. 6 is a diagram for explaining the relation between the drain voltage and the drain current of the embodiment shown in FIG. 1, and FIG. 7 is the drain voltage vs. drain current of the conventional example. FIG. 8 is a diagram for explaining the relationship between FIG. 8 and FIG. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an i-type AlGaAs buffer layer, 3 is an n-type GaAs channel layer, 4 is a gate electrode,
5 is a source electrode, 6 is a drain electrode, 7 is n-type gIn X Ga
1-X As channel layers are shown respectively.
Claims (1)
対するバリヤとして作用するノン・ドープのバッファ層
と、 該バッファ層上に形成され該バッファ層との界面近傍か
ら表面に向かってグレーデッドにInが導入され且つ表面
では該Inの組成が略零になっているInXGa1-XAsチャネル
層と、 を備えてなることを特徴とする電界効果半導体装置。1. A non-doped buffer layer formed on a semi-insulating GaAs substrate and acting as a barrier against carriers, and a graded layer formed on the buffer layer from near the interface with the buffer layer toward the surface. A field effect semiconductor device comprising: an In X Ga 1-X As channel layer in which In is introduced and the composition of In is substantially zero on the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62212699A JP2561095B2 (en) | 1987-08-28 | 1987-08-28 | Field effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62212699A JP2561095B2 (en) | 1987-08-28 | 1987-08-28 | Field effect semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6457677A JPS6457677A (en) | 1989-03-03 |
| JP2561095B2 true JP2561095B2 (en) | 1996-12-04 |
Family
ID=16626962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62212699A Expired - Fee Related JP2561095B2 (en) | 1987-08-28 | 1987-08-28 | Field effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2561095B2 (en) |
-
1987
- 1987-08-28 JP JP62212699A patent/JP2561095B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6457677A (en) | 1989-03-03 |
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