JP2547486B2 - Method for automatically generating wiring connection information of semiconductor integrated circuit - Google Patents

Method for automatically generating wiring connection information of semiconductor integrated circuit

Info

Publication number
JP2547486B2
JP2547486B2 JP3187339A JP18733991A JP2547486B2 JP 2547486 B2 JP2547486 B2 JP 2547486B2 JP 3187339 A JP3187339 A JP 3187339A JP 18733991 A JP18733991 A JP 18733991A JP 2547486 B2 JP2547486 B2 JP 2547486B2
Authority
JP
Japan
Prior art keywords
file
lead frame
connection information
pad
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3187339A
Other languages
Japanese (ja)
Other versions
JPH0536750A (en
Inventor
典夫 大西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
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Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3187339A priority Critical patent/JP2547486B2/en
Publication of JPH0536750A publication Critical patent/JPH0536750A/en
Application granted granted Critical
Publication of JP2547486B2 publication Critical patent/JP2547486B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49177—Combinations of different arrangements
    • H01L2224/49179—Corner adaptations, i.e. disposition of the wire connectors at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はＬＳＩ設計の支援装置と
してパッケージとチップ間の接続情報の自動生成方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically generating connection information between a package and a chip as an LSI design support device.

【０００２】近来、ＬＳＩが高集積化することに伴い、
チップ内部の高密度化と共に、パッケージピン（リード
フレーム）数も数百本に増大し、チップとリードフレー
ム間を接続した配線図面を作成すること、及びその配線
図面の内容の表記を正確に素早く行うこと、即ちＬＳＩ
設計支援装置上で実行できるようにされていることが要
求される。Recently, with the high integration of LSIs,
The number of package pins (lead frame) has increased to several hundreds with the high density inside the chip, and it is possible to create a wiring drawing that connects the chip and the lead frame, and to display the contents of the wiring drawing accurately and quickly. What to do, that is, LSI
It is required to be able to be executed on the design support device.

【０００３】[0003]

【従来の技術】図３は半導体集積回路とリードフレーム
との接続状態を説明するための図である。図３におい
て、１は半導体集積回路のチップ、２はチップを外包す
るパッケージ、3-1,3-2 〜はパッドで半導体集積回路の
周辺部に並ぶもの、4-1,4-2 〜はリードフレーム( パッ
ケージに埋め込まれ一方の先端が外部接続端子となるも
の) 、5-1,5-2〜は接続線でボンディングワイヤと呼ば
れているものを示す。図４は図３を更に詳細に示す図で
ある。図４では接続線とリードフレームの数が120本で
あって、パッドについてはリードフレームと接続しない
ものが若干個数図示されている。2. Description of the Related Art FIG. 3 is a diagram for explaining a connection state between a semiconductor integrated circuit and a lead frame. In FIG. 3, 1 is a chip of a semiconductor integrated circuit, 2 is a package for enclosing the chip, 3-1, 3-2 ... are pads arranged in the peripheral part of the semiconductor integrated circuit, 4-1, 4-2 ... are Lead frames (embedded in the package, one end of which serves as an external connection terminal), 5-1 and 5-2 ~ are connecting wires called bonding wires. FIG. 4 is a diagram showing FIG. 3 in more detail. In FIG. 4, the number of connecting lines and lead frames is 120, and some of the pads that are not connected to the lead frame are shown.

【０００４】従来は図４に示すようなチップを製造する
ときの設計図を見て、パッド・リードフレーム間の接続
を人間の目で目視し（接続されているかどうか）予め定
められたルールに従って接続情報を記述していた。その
接続情報は例えば図５に示すようになっていた。図５に
おいて、ＰＡＤはパッドを示す番号、leadはリードフレ
ームを示す番号で、−は接続されていることを示す記号
である。そのため目視情報を基として、図５に示すよう
な情報をファイルに順次入力・格納していた。このよう
にして得られた接続情報はワイヤボンディング装置によ
りボンディングするときの基礎データとしてワイヤボン
ディング装置に供給されて使用される。Conventionally, a connection between a pad and a lead frame is visually checked by a human eye (whether or not the connection is made) according to a predetermined rule by looking at a design drawing for manufacturing a chip as shown in FIG. Described the connection information. The connection information is as shown in FIG. 5, for example. In FIG. 5, PAD is a number indicating a pad, lead is a number indicating a lead frame, and-is a symbol indicating connection. Therefore, based on the visual information, the information shown in FIG. 5 is sequentially input and stored in the file. The connection information obtained in this way is supplied to the wire bonding apparatus and used as basic data for bonding by the wire bonding apparatus.

【０００５】[0005]

【発明が解決しようとする課題】ＬＳＩチップは益々高
密度化し、リードフレームが数多くなるから、パッドと
の接続情報が図面上において複雑となり、読取りが困難
となる傾向にある。そのため作成した接続対応情報が誤
っていたり、接続ルールに反した接続情報の存在するこ
とが起こった。その結果ワイヤボンディングを実行しＬ
ＳＩ製造後の試験でミスが発見されて、ＬＳＩ製造をや
り直すことが発生した。Since the density of LSI chips becomes higher and the number of lead frames increases, the connection information with the pads tends to be complicated on the drawing, making it difficult to read. Therefore, the created connection correspondence information is incorrect, or there is connection information that violates the connection rules. As a result, wire bonding is performed and L
A mistake was found in the test after the SI was manufactured, and the LSI manufacturing was restarted.

【０００６】本発明の目的は前述の欠点を改善し、配線
図面を予めデータベース化し、なお別ファイルに入って
いる規則を参照しながら、パッドとリードフレームとの
接続情報を正確に自動的に生成する方法を提供すること
を目的とする。The object of the present invention is to improve the above-mentioned drawbacks, to make a wiring diagram in advance into a database, and to automatically and accurately generate the connection information between the pad and the lead frame while referring to the rules contained in another file. The purpose is to provide a method of doing.

【０００７】[0007]

【課題を解決するための手段】図１は本発明の原理構成
を示す図である。図１において、１１は第１ファイルで
パッドとリードフレーム間の接続情報を図形パターンに
展開して記録したもの、１２は第２ファイルでパッドと
リードフレームとを接続線により接続することの一般的
規則を格納したもの、１３はデータ処理装置、１４は生
成データファイル、１５は誤りデータの表示形態を示
す。FIG. 1 is a diagram showing the principle configuration of the present invention. In FIG. 1, reference numeral 11 is a first file in which the connection information between the pad and the lead frame is expanded and recorded in a graphic pattern, and 12 is a second file, which is a general example of connecting the pad and the lead frame by a connecting line. Rules are stored, 13 is a data processing device, 14 is a generated data file, and 15 is a display form of error data.

【０００８】半導体集積回路チップの周囲に設けられた
パッケージのリードフレームと、チップ上のパッドとを
接続線で接続して記述した配線図面から、配線接続情報
を生成する方法において、本発明は下記の構成としてい
る。即ち、前記配線図面を、リードフレームを示す線図
と、パッドを示す線図と、接続線を示す線図とで記述
し、該線図に基づいてリードフレーム・パッド・接続線
をそれぞれ図形パターンに展開して第１ファイル１１に
格納し、一方、リードフレームとパッドとを接続線によ
り接続することの一般的規則を第２ファイル１２に格納
し、次いで第１ファイル１１の格納データについて第２
ファイル(12)のデータを参照しながら、処理装置(13)に
より処理してリードフレームとチップ間の配線接続情報
を第３ファイル１４に生成することで構成する。In a method of generating wiring connection information from a wiring drawing in which a lead frame of a package provided around a semiconductor integrated circuit chip and a pad on the chip are connected by a connecting line, the present invention provides the following: It has a configuration of. That is, the wiring diagram is described by a diagram showing a lead frame, a diagram showing pads, and a diagram showing connection lines, and based on the diagram, the lead frame, the pads, and the connection lines are each formed into a graphic pattern. Stored in the first file 11 and stored in the first file 11, while the general rule of connecting the lead frame and the pad by the connecting wire is stored in the second file 12, and then the stored data of the first file 11 is stored in the second file 12.
It is configured by referring to the data of the file (12) and generating the wiring connection information between the lead frame and the chip in the third file 14 by processing by the processing device (13).

【０００９】[0009]

【作用】半導体集積回路においてリードフレームとパッ
ドとを接続することの一般的な規則、即ちパッドの位置
と対応するリードフレームとの順序関係、パッドと対向
するリードフレームの位置が判ったとき必要な接続線の
長さなどについて、第２フレーム１２に予め格納して置
く。半導体集積回路の設計が出来てその配線図面が得ら
れたとき、同時に配線図面データを直線の集合としてそ
のデータを第１ファイル１１に格納する。そのデータは
パッド・リードフレーム・接続線の各グループ別にまと
めて置くと良い。This is necessary when the general rule for connecting the lead frame and the pad in the semiconductor integrated circuit, that is, the order relation between the position of the pad and the corresponding lead frame and the position of the lead frame facing the pad are known. The length of the connecting line and the like are stored in advance in the second frame 12. When the semiconductor integrated circuit can be designed and its wiring drawing is obtained, at the same time, the wiring drawing data is stored in the first file 11 as a set of straight lines. The data should be put together for each group of pads, lead frames and connecting wires.

【００１０】次に第１ファイル１１の格納データについ
て、第２ファイル１２に格納の接続ルールを参照しなが
ら、データ処理装置１３により処理する。即ち、パッド
とリードフレームについて所定の接続線により接続する
ことを配線接続情報として生成する。例えば接続するこ
との順序関係に基づいて順次に接続することをデータ化
する。この過程においてリードフレームとパットとの対
応関係において距離の長短・隣接接続線との間隔の広狭
・或いはボンディングの位置によって接続線の角度が規
格値より過大・過少になるときはエラーとなることを表
示或いはデータファイルに格納する。このようにして配
線接続情報が人間の目視によらず正確に自動生成され
る。Next, the data stored in the first file 11 is processed by the data processor 13 with reference to the connection rule stored in the second file 12. That is, the connection between the pad and the lead frame by a predetermined connection line is generated as the wiring connection information. For example, the sequential connection is converted into data based on the order relation of the connection. In this process, an error will occur if the angle of the connecting wire becomes too large or too small from the standard value depending on the length of the lead frame and the pad, the distance between the adjacent connecting wires, and the bonding position. Display or store in data file. In this way, the wiring connection information is accurately and automatically generated without the need for human visual inspection.

【００１１】[0011]

【実施例】配線図面に基づいてパッド・接続線・リード
フレームのそれぞれに順序番号を付し、各々について
「始点座標・終点座標・その間をつなぐ線分」とを少な
くとも４組揃えて１つの四角の枠を形成する情報を得
る。そして配線図面から判断して大きさからパッドとリ
ードフレームとに大別し、更に接続線について始点座標
と終点座標とを定める。それらは第１ファイル１１内に
格納される。なお当初の作業であり誤りを出来るだけ減
らすため配線図面を作成したＬＳＩの設計者が、データ
を得てファイル１１に格納することが最も適している。[Embodiment] A pad, a connecting wire, and a lead frame are each given a sequence number on the basis of a wiring drawing, and at least four sets of "starting point coordinates, ending point coordinates, and a line segment connecting them" are aligned to form a square. Get the information that forms the frame of. Judging from the wiring diagram, the pad and the lead frame are roughly classified according to the size, and the start point coordinates and the end point coordinates of the connection line are determined. They are stored in the first file 11. It is most appropriate for the designer of the LSI who created the wiring drawing to store the data in the file 11 in order to reduce errors as much as possible.

【００１２】第２ファイル１２内のデータとしては一般
的な接続ルールを格納する。配線接続情報として、配線
図を見たときパッドとリードフレームとの間隔が判れ
ば、必要とする接続線の長さの大小限界値が経験的に求
められる。そのため配線接続情報の中で必要とする接続
線の長さとして限界値を超える値が生じたときエラーと
なる。As the data in the second file 12, general connection rules are stored. As the wiring connection information, if the distance between the pad and the lead frame is known when the wiring diagram is viewed, the limit value of the length of the required connection line can be empirically obtained. Therefore, an error occurs when a value exceeding the limit value occurs in the required length of the connection line in the wiring connection information.

【００１３】また配線接続情報の中で接続線の長さが限
界値付近となっているときパッド・リードフレームに対
し接続線との角度が過大・過少となる場合がある。配線
図においてパッド・リードフレームの両者が通常許され
る範囲内で上下になっているとして接続線とのなす角度
が４５度±１０度の範囲内にない場合をエラーとするこ
とを、第２ファイル１２内に格納する。また隣接する接
続線が図面上では問題ないとしてもデータファイル１１
上では規定値以下になる場合があるため、最小限規定値
を第２ファイル１２に格納して置く。In addition, when the length of the connection line is close to the limit value in the wiring connection information, the angle between the connection line and the pad lead frame may be too large or too small. In the wiring diagram, it is assumed that both the pad and lead frame are vertically above and below the normal allowable range, and if the angle between the pad and the lead frame is not within the range of 45 ° ± 10 °, the second file Stored in 12. In addition, even if the adjacent connecting line has no problem in the drawing, the data file 11
In the above case, the minimum specified value may be stored in the second file 12 because it may be less than the specified value.

【００１４】データ処理装置によるデータ処理は第１フ
ァイル１１内のデータについて、例えば「所定のリード
フレームに対しチップ上、対応する辺のパッドの第３番
以降から互いに順序通り接続すること」のような処理命
令により接続情報を得る処理を開始する。その結果、図
５に示すようにパッドとリードフレームとの接続情報が
得られて、第３ファイル１３に格納される。The data processing by the data processing device is performed on the data in the first file 11 by, for example, "connecting to a predetermined lead frame on the chip in order from the third and subsequent pads of the corresponding side pads". A process for obtaining connection information is started by a different processing command. As a result, as shown in FIG. 5, the connection information between the pad and the lead frame is obtained and stored in the third file 13.

【００１５】次に図２はエラー表示１５の具体例を示す
図である。図２の第１行は、接続線１０は１番パッドと
１０番リードフレームとを接続するもので、入射角度に
エラーがあることを示している。同様に次の第２行は、
接続線２３は１０番パッドと１５番リードフレームを接
続し、入射角度にエラーがあることを示している。第３
行も同様である。Next, FIG. 2 is a diagram showing a specific example of the error display 15. The first line in FIG. 2 shows that the connection line 10 connects the No. 1 pad and the No. 10 lead frame, and there is an error in the incident angle. Similarly, the second line below
The connecting line 23 connects the No. 10 pad and the No. 15 lead frame and indicates that there is an error in the incident angle. Third
The lines are similar.

【００１６】次の実施例として、配線図面が得られたと
き、各パッドとリードフレームにはそれぞれ直流電位
“Ｈ”・接地電位“Ｌ”と交流信号印加のように電位情
報が定められている。そのためパッドとリードフレーム
の情報の内所定位置に電位情報を付加してデータファイ
ル１１を得て置く。データ処理装置１３において接続情
報を得るとき、各接続線の両端の電位情報が等しくなる
筈であるから、接続時の情報チェックとして「電位情
報」を使用することができる。この手段により電気的な
接続チェックを行ったことになり、信頼性が大いに向上
できる。As a next example, when a wiring drawing is obtained, potential information is set for each pad and lead frame such as DC potential "H", ground potential "L", and AC signal application. . Therefore, the electric potential information is added to a predetermined position of the information of the pad and the lead frame, and the data file 11 is obtained and placed. When the data processing device 13 obtains the connection information, the potential information at both ends of each connection line should be equal, so that the "potential information" can be used as an information check at the time of connection. By this means, the electrical connection is checked, and the reliability can be greatly improved.

【００１７】[0017]

【発明の効果】このようにして本発明によると、パッド
とリードフレーム間の配線接続情報を生成するとき、従
来技術のように人間が目視して行う作業ではなく、デー
タ処理装置による自動生成が可能となる。そのため配線
図面作成者が作業するように、従来と比較して正確さを
向上させることができる。また処理の高速化ができる。
なお配線図面から当初に得たファイルにおいて「電位情
報」などを付加すると、接続情報を生成したときエラー
チェックがより正確に出来る。As described above, according to the present invention, when the wiring connection information between the pad and the lead frame is generated, it is not automatically performed by human eyes as in the prior art, but is automatically generated by the data processing device. It will be possible. Therefore, the accuracy can be improved as compared with the conventional method so that the wiring drawing creator works. In addition, the processing speed can be increased.
If "potential information" is added to the file originally obtained from the wiring diagram, error checking can be performed more accurately when the connection information is generated.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の原理構成図である。FIG. 1 is a principle configuration diagram of the present invention.

【図２】本発明の実施例によるエラー表示例の図であ
る。FIG. 2 is a diagram of an error display example according to an embodiment of the present invention.

【図３】半導体集積回路とリードフレームとの接続状態
を説明するための図である。FIG. 3 is a diagram for explaining a connection state between a semiconductor integrated circuit and a lead frame.

【図４】図３を更に詳細に示す図である。FIG. 4 is a diagram showing FIG. 3 in more detail.

【図５】図４に基づく配線接続情報の例を示す図であ
る。5 is a diagram showing an example of wiring connection information based on FIG.

【符号の説明】[Explanation of symbols]

１１ 第１ファイル １２ 第２ファイル １２ データ処理装置 １４ 第３ファイル 11 First File 12 Second File 12 Data Processing Device 14 Third File

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体集積回路チップの周囲に設けられ
たパッケージのリードフレームと、チップ上のパッドと
を接続線で接続して記述した配線図面から、配線接続情
報を生成する方法において、 前記配線図面を、リードフレームを示す線図と、パッド
を示す線図と、接続線を示す線図とで記述し、 該線図に基づいてリードフレーム・パッド・接続線をそ
れぞれ図形パターンに展開して第１ファイル(11)に格納
し、 一方、リードフレームとパッドとを接続線により接続す
ることの一般的規則を第２ファイル(12)に格納し、 次いで第１ファイル(11)の格納データについて第２ファ
イル(12)のデータを参照しながら、処理装置(13)により
処理してリードフレームとチップ間の配線接続情報を第
３ファイル(14)に生成すること、 を特徴とする半導体集積回路の配線接続情報を自動生成
する方法。1. A method of generating wiring connection information from a wiring drawing in which a lead frame of a package provided around a semiconductor integrated circuit chip and a pad on the chip are connected by a connecting line is described. The drawing is described by a diagram showing a lead frame, a diagram showing pads, and a diagram showing connection lines, and the lead frame, pads, and connection lines are developed into graphic patterns based on the diagram. Stored in the first file (11), on the other hand, stored in the second file (12) is the general rule of connecting the lead frame and the pad by connecting wires, and then regarding the stored data of the first file (11) A semiconductor integrated circuit characterized in that, while referring to the data of the second file (12), it is processed by the processing device (13) to generate wiring connection information between the lead frame and the chip in the third file (14). Method of automatically generating the wiring connection information. 【請求項２】 請求項１記載の第１ファイルには図形パ
ターン以外に付加情報を格納しておき、接続線の両端に
おいて同一付加情報が得られないとき、その内容をエラ
ー表示することを特徴とする半導体集積回路の配線接続
情報の自動生成方法。2. The first file according to claim 1 stores additional information other than the graphic pattern, and when the same additional information cannot be obtained at both ends of the connecting line, the content is displayed as an error. A method for automatically generating wiring connection information of a semiconductor integrated circuit.
JP3187339A 1991-07-26 1991-07-26 Method for automatically generating wiring connection information of semiconductor integrated circuit Expired - Fee Related JP2547486B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3187339A JP2547486B2 (en) 1991-07-26 1991-07-26 Method for automatically generating wiring connection information of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3187339A JP2547486B2 (en) 1991-07-26 1991-07-26 Method for automatically generating wiring connection information of semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPH0536750A JPH0536750A (en) 1993-02-12
JP2547486B2 true JP2547486B2 (en) 1996-10-23

Family

ID=16204272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3187339A Expired - Fee Related JP2547486B2 (en) 1991-07-26 1991-07-26 Method for automatically generating wiring connection information of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP2547486B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003297870A (en) * 2002-04-04 2003-10-17 Mitsubishi Electric Corp Design support device for semiconductor device

Also Published As

Publication number Publication date
JPH0536750A (en) 1993-02-12

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