JP2545953B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2545953B2 JP2545953B2 JP63253505A JP25350588A JP2545953B2 JP 2545953 B2 JP2545953 B2 JP 2545953B2 JP 63253505 A JP63253505 A JP 63253505A JP 25350588 A JP25350588 A JP 25350588A JP 2545953 B2 JP2545953 B2 JP 2545953B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type region
- oxide film
- semiconductor device
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に耐放射線性の半導体
装置に関する。The present invention relates to a semiconductor device, and more particularly to a radiation resistant semiconductor device.
従来耐放射線性を目的とした半導体装置は第３図に示
すようにＰ型領域層２が設けられた基板上に薄いフィー
ルド酸化膜５を設け、その上に窒化膜６を成長させその
上にCVD酸化膜７とすることで、耐放射線性向上を企っ
ている。すなわち、フィールド酸化膜５とCVD酸化膜７
の間に窒化膜６を存在させ、これがγ線照射により発生
する正電荷のトラップの役目をはたし、下層の素子領域
までγ線の影響がないようにしていた。As shown in FIG. 3, a conventional semiconductor device for radiation resistance is provided with a thin field oxide film 5 on a substrate provided with a P-type region layer 2, and a nitride film 6 is grown on the thin field oxide film 5. The CVD oxide film 7 is used to improve radiation resistance. That is, the field oxide film 5 and the CVD oxide film 7
A nitride film 6 is present between the two, and this serves as a trap for positive charges generated by γ-ray irradiation so that the lower layer element region is not affected by γ-rays.
上述した従来の半導体装置は、薄いフィールド酸化膜
５の上に窒化膜６を有する構造となっていたNPNトラン
ジスタにおいては、酸化膜５シリコン界面での放射線
（ここではγ線とする）による酸化膜，シリコン界面の
再結合電流の増加は防げるが、その上に形成される窒化
膜がγ線が照射されることで全体的に＋にチャージされ
た状態となり、このため下層のベース（Ｐ型領域２）表
面が反転し、NPNトランジスタのコレクターベース間リ
ーク電流及びコレクターエミッタ間リーク電流の増大が
現われるという欠点がある。また薄いフィールド酸化膜
の上にCVD酸化膜を形成したとしてもフィールド酸化膜
がみかけ上厚くなったものと同等と考えられるため再結
合電流の増加を防ぐことはできない。In the conventional semiconductor device described above, in the NPN transistor in which the nitride film 6 is formed on the thin field oxide film 5, the oxide film 5 is an oxide film caused by radiation (here, γ rays) at the silicon interface. , It is possible to prevent the recombination current at the silicon interface from increasing, but the nitride film formed on it is charged to + as a whole by irradiation with γ-rays, so that the base (P-type region) of the lower layer is 2) There is a drawback that the surface is inverted and the collector-base leakage current and the collector-emitter leakage current of the NPN transistor increase. Further, even if the CVD oxide film is formed on the thin field oxide film, it is considered that the field oxide film is thicker than it is apparently thick, so that the recombination current cannot be prevented from increasing.
本発明の目的は、γ線照射によるＰ型領域表面の反転
を防止することができる半導体装置を提供することにあ
る。It is an object of the present invention to provide a semiconductor device capable of preventing the P-type region surface from being inverted due to γ-ray irradiation.
本発明の半導体装置は、Ｐ型拡散層を有し半導体基板
に形成された素子領域、及び上記Ｐ型拡散層及び上記素
子領域にそれぞれ接続された第１及び第２の電極を備
え、上記素子領域が形成されている半導体基板上に設け
られたシリコン酸化膜上にシリコン窒化膜及びCVDシリ
コン酸化膜が順次堆積されている半導体装置であって、
上記第１及び第２の電極の間に位置する上記Ｐ型拡散層
表面に高濃度のP+型層を有することを特徴とする。A semiconductor device of the present invention includes an element region having a P-type diffusion layer and formed on a semiconductor substrate, and first and second electrodes connected to the P-type diffusion layer and the element region, respectively. A semiconductor device in which a silicon nitride film and a CVD silicon oxide film are sequentially deposited on a silicon oxide film provided on a semiconductor substrate in which a region is formed,
A high-concentration P + -type layer is provided on the surface of the P-type diffusion layer located between the first and second electrodes.
次に本発明について図面を引用し説明する。第１図は
本発明の一実施例を説明するためのNPNトランジスタの
縦断面図である。エピタキシャル層１にＰ型不純物を拡
散したベース領域に当るＰ型領域層２を形成した後、エ
ミッタ及びコレクタコンタクト外部となるN+型領域層３
を形成する。次にベースＰ型領域層２表面にP+型領域層
４を設ける。次に、薄いシリコン酸化膜５を形成した
後、窒化膜6,CVD酸化膜７を順次形成してフィールド絶
縁膜を形成し、NPNトランジスタを構成している。な
お、P+型領域層４はコンタクト部有無にかかわらずベー
スＰ型領域層２表面に設けてある。本発明では前述の通
りベースＰ型領域層２表面に設けられているP+層４によ
りγ線が照射され、窒化膜６が正に帯電しても、Ｐ型領
域層２の表面はＰ型不純物濃度が高いため、その表面の
反転が起こらず、リーク電流の増大を防止できる。Next, the present invention will be described with reference to the drawings. FIG. 1 is a vertical sectional view of an NPN transistor for explaining one embodiment of the present invention. After the P-type region layer 2 corresponding to the base region in which the P-type impurities are diffused is formed in the epitaxial layer 1, the N + -type region layer 3 serving as the outside of the emitter and collector contacts is formed.
To form. Next, the P + type region layer 4 is provided on the surface of the base P type region layer 2. Next, after forming a thin silicon oxide film 5, a nitride film 6 and a CVD oxide film 7 are sequentially formed to form a field insulating film, thus forming an NPN transistor. The P + type region layer 4 is provided on the surface of the base P type region layer 2 regardless of the presence or absence of a contact portion. According to the present invention, as described above, even if the P + layer 4 provided on the surface of the base P-type region layer 2 is irradiated with γ-rays and the nitride film 6 is positively charged, the surface of the P-type region layer 2 is P-type. Since the impurity concentration is high, inversion of the surface does not occur, and an increase in leak current can be prevented.
第２図は本発明の他の実施例を説明するためのＰ型拡
散抵抗の縦断面図である。エピタキシャル層１にＰ型領
域層２を拡散し、エピタキシャル層を高電位にするため
のN+型領域層３を形成し、次にＰ型領域層２上のコンタ
クトを設ける部分にP+層４を設ける。次工程のフィール
ド絶縁膜の形成は、第１の実施例で記述した通りであ
る。上記構造にすることでγ線が照射され窒化膜６が正
に帯電しても拡散抵抗コンタクト部に設けてあるP+型領
域層４によりＰ型領域層２の表面の反転がなくなり高電
位N+層３と拡散抵抗コンタクト部間のリーク電流を防ぐ
ことができる利点がある。FIG. 2 is a vertical sectional view of a P-type diffused resistor for explaining another embodiment of the present invention. A P + type region layer 2 is diffused in the epitaxial layer 1 to form an N + type region layer 3 for making the epitaxial layer a high potential, and then a P + layer 4 is formed on the P type region layer 2 at a portion where a contact is to be provided. To provide. The formation of the field insulating film in the next step is as described in the first embodiment. With the above structure, even if the γ-ray is irradiated and the nitride film 6 is positively charged, the P + -type region layer 4 provided in the diffusion resistance contact portion does not invert the surface of the P-type region layer 2 and the high potential N There is an advantage that a leak current between the + layer 3 and the diffusion resistance contact portion can be prevented.
以上説明した実施例は、NPNトランジスタ及び拡散抵
抗のＰ型領域上にP+型領域を設けた例で説明したが本発
明は上記例に限らず、PNPトランジスタのＰ型領域上等
のＰ型領域の上面にP+領域層を設けることで上層の窒化
膜がγ線によって帯電してもＰ型領域表面の反転を防止
する効果は同様である。Although the embodiment described above has been described as an example in which the P + -type region is provided on the P-type region of the NPN transistor and the diffusion resistance, the present invention is not limited to the above example, and the P-type region on the P-type region of the PNP transistor or the like. Providing the P + region layer on the upper surface of the region has the same effect of preventing the inversion of the surface of the P-type region even if the upper nitride film is charged by γ rays.
以上説明したように本発明は、Ｐ型拡散層の表面に高
濃度P+型領域層を設けることにより、γ線等の放射線で
の窒化膜のみかけ上の正帯電によるＰ型拡散層の反転を
防止し、リーク電流の増大を防ぐことができる効果があ
る。As described above, according to the present invention, by providing the high-concentration P + -type region layer on the surface of the P-type diffusion layer, the inversion of the P-type diffusion layer due to the positive charge on the nitride film apparently by the radiation such as γ-rays. There is an effect that it is possible to prevent the increase of the leak current.
第１図は本発明の第１の実施例を説明するためのNPNト
ランジスタの縦断面図、第２図は本発明の他の実施例を
説明するためのＰ型拡散抵抗の縦断面図、第３図は従来
例を説明するためのNPNトランジスタの縦断面図であ
る。 １……Ｎ型エピタキシャル層、２……Ｐ型領域層、３…
…N+型領域層、４……P+型領域層、５……薄い酸化膜、
６……窒化膜、７……CVD酸化膜、８……アルミニウ
ム。FIG. 1 is a vertical sectional view of an NPN transistor for explaining the first embodiment of the present invention, and FIG. 2 is a vertical sectional view of a P-type diffusion resistor for explaining another embodiment of the present invention. FIG. 3 is a vertical sectional view of an NPN transistor for explaining a conventional example. 1 ... N-type epitaxial layer, 2 ... P-type region layer, 3 ...
… N + type region layer, 4 …… P + type region layer, 5 …… thin oxide film,
6 ... Nitride film, 7 ... CVD oxide film, 8 ... Aluminum.
Claims (1)
素子領域、及び前記Ｐ型拡散層及び前記素子領域にそれ
ぞれ接続された第１及び第２の電極を備え、前記素子領
域が形成されている半導体基板上に設けられたシリコン
酸化膜上にシリコン窒化膜及びCVDシリコン酸化膜が順
次堆積されている半導体装置であって、前記第１及び第
２の電極の間に位置する前記Ｐ型拡散層表面に高濃度の
P+型層を有することを特徴とする半導体装置。1. An element region having a P-type diffusion layer formed on a semiconductor substrate, and first and second electrodes respectively connected to the P-type diffusion layer and the element region, wherein the element region is A semiconductor device in which a silicon nitride film and a CVD silicon oxide film are sequentially deposited on a silicon oxide film provided on a formed semiconductor substrate, wherein the semiconductor device is located between the first and second electrodes. High concentration of P type diffusion layer surface
A semiconductor device having a P + type layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63253505A JP2545953B2 (en) | 1988-10-06 | 1988-10-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63253505A JP2545953B2 (en) | 1988-10-06 | 1988-10-06 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02100339A JPH02100339A (en) | 1990-04-12 |
| JP2545953B2 true JP2545953B2 (en) | 1996-10-23 |
Family
ID=17252313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63253505A Expired - Fee Related JP2545953B2 (en) | 1988-10-06 | 1988-10-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2545953B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4003438B2 (en) | 2001-11-07 | 2007-11-07 | 株式会社デンソー | Semiconductor device manufacturing method and semiconductor device |
| JP4784595B2 (en) | 2007-12-21 | 2011-10-05 | 株式会社デンソー | Bipolar semiconductor device manufacturing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56119655U (en) * | 1980-02-15 | 1981-09-11 | ||
| JPS5742148A (en) * | 1980-08-26 | 1982-03-09 | Seiko Epson Corp | Semiconductor device |
-
1988
- 1988-10-06 JP JP63253505A patent/JP2545953B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| 菅野卓雄監修超高速ＭＯＳデバイス培風館ｐ．１２６−１２９ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02100339A (en) | 1990-04-12 |
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