JP2545823B2 - Error detector - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an error detection device for detecting error symbols in read information, and in particular, when there are a large number of error symbols (3 symbols or more), a detection calculation time The present invention relates to an error detection device that can reduce the error.

[Prior art]

Generally, when using a plastic optical disk in an optical disk device, it is necessary to reduce the error rate and improve the reliability of the data, so a method to strengthen the error correction code (ECC) is necessary. Is becoming.

To correct this error, the Reed-Solomon code
As for the procedure of decoding BCH code), first, demodulate the media data, obtain the syndrome, calculate the error location polynomial σ (χ) from the syndrome,
Further, the inverse element (error position) of the root of σ (χ) is obtained and error correction is performed.

In the process of such error correction, the number of calculations required to obtain the error location polynomial σ (χ) has been a problem.

For example, in the apparatus described in Japanese Patent Laid-Open No. 54-32240, Reed-Solomon code decoding is performed by using the concept that a single error is inspected and corrected before detection of multiple errors, and error symbols are detected. If the number is small, the detection calculation is speeded up.

However, this method does not consider the case where the number of error symbols is large.

[Problems to be solved by the invention]

In the above conventional technique, when the number of error symbols is large,
The error position of the error symbol and the error
Since no consideration was given to the pattern detection calculation time, there was a problem that the calculation time was long.

An object of the present invention is to provide an error detecting apparatus which can solve such problems and shorten the error symbol detection time when the number of error symbols is large.

[Means for solving problems]

In order to achieve the above object, the error detecting device of the present invention is an error detecting device for detecting an error symbol by information composed of a data symbol and a check symbol generated from a generator polynomial by a Reed-Solomon code, A first conversion circuit (3) for converting the calculation data M1 from the microprocessor circuit (26) into matrix data.
2), a first multiplication circuit (34) for multiplying the calculation data M2 from the microprocessor circuit (26) by the output of the first conversion circuit (32), and a microprocessor circuit (2
A second conversion circuit (33) for converting the calculation data M3 from 6) into matrix data, and a microprocessor circuit (2)
A second multiplication circuit (35) for multiplying the calculation data M4 from 6) by the output of the second conversion circuit (33);
The exclusive OR of the outputs of the multiplication circuit (34) and the second multiplication circuit (35)
6) output to the EOR circuit (36), and the error syndrome (S _{0 to} S ₁₅ ) is input from the microprocessor circuit (26) as the calculation data M1 to M4 to obtain the coefficient of the error location polynomial. (Σ _{1 to} σ ₈ )
First calculation means (see FIG. 3) for calculating the calculation data
First conversion circuit for converting M1 to matrix data (32)
A first multiplication circuit (34) for multiplying the calculation data M2 by the output of the first conversion circuit (32), a second conversion circuit (33) for converting the calculation data M3 into matrix data,
A second multiplication circuit (35) for multiplying the calculation data M4 by the output of the second conversion circuit (33), an output of the first multiplication circuit (34) and an output of the second multiplication circuit (35). An EOR circuit (36) for exclusive OR, a zero check circuit (44) for zero-checking the output of the EOR circuit (36), a shift register (R1 to R7), the calculation data M1 and final execution Either the data from the compare check circuit (43) that determines the end of calculation by comparing the data M5 indicating the position and the data from the microprocessor circuit (26) or the output of the first conversion circuit (32) is calculated data. First to choose as M1
Second selector (S1) for selecting the data from the microprocessor circuit (26) or the output of the EOR circuit (36) as the calculation data M2.
2) and a third selector (S4) for selecting either the data from the microprocessor circuit (26) or the output of the shift register (R1 to R7) as the calculation data M4.
And a calculation control circuit (45) which inputs the outputs of the compare circuit (43) and the zero check circuit (44) and controls the selectors (S1 to S4) and the shift registers (R1 to R7).
And the error calculated by the first calculation means.
Second calculation for obtaining the actual error location value by inputting the error location parameter to the shift registers (R1 to R7) in the calculation data M1 to M3 using the coefficients (σ _{1 to} σ ₈ ) of the location polynomial Means (4th
(Refer to the figure).

[Action]

In the present invention, the error symbol calculation circuit is instructed by the microprocessor circuit on the calculation input data, and the microprocessor circuit can recognize the calculation result.

When the microprocessor circuit indicates the calculation range, the error symbol calculation circuit automatically switches the calculation input data in that range and continues the calculation.

Therefore, even when the number of error symbols is 3 symbols or more, the error information is calculated at high speed and the calculation time is shortened.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an error detecting device in an embodiment of the present invention.

The error detection device of this embodiment includes a drive device 21 and a demodulation circuit.
22, syndrome arithmetic circuit 23, data memory circuit 24,
A syndrome check circuit 25, a microprocessor circuit 26, and an error symbol calculation circuit 27 are provided,
Connected to host 28.

Further, the error symbol calculation circuit 27 includes a coefficient of an error location polynomial and an error pattern calculation circuit (see FIG. 3) and an error location calculation circuit (see FIG. 4). When the number of symbols is 3 or more, the calculation is performed using the error location calculation circuit.

In the error detection device of this embodiment, when error detection is performed, read data 1 sent via the drive device 21.
Is demodulated by the demodulation circuit 22 and converted into bytes.

Next, the byte-converted demodulated data 2 is sent to the data memory circuit 24 and the syndrome arithmetic circuit 23,
In the syndrome calculation circuit 23, calculation for finding the syndrome is performed.

FIG. 2 shows user data in one embodiment of the present invention,
3 is a data configuration diagram of ECC data. FIG.

The demodulated data 2 in the present embodiment is in byte units, and user data composed of n + 1 bytes of D _{0 to} D _n ,
Composed of the ECC data consisting of 16 bytes of C ₀ -C _15.

Therefore, the syndrome data 3 obtained by the calculation of the syndrome calculation circuit 23 has 16 bytes.

The ECC data is a code generated by the Reed-Solomon code, and the syndrome calculation for this decoding uses a general decoding method.

Further, the syndrome data 3 calculated by the syndrome calculation circuit 23 is stored in the data memory circuit 24 after the demodulation data 2 is stored in the data memory circuit 24. Also, during this storage, the syndrome
The syndrome check circuit 25 checks whether or not the data 3 is “00”.

The check data 6, which is the check result, is reported to the microprocessor circuit 26 after the syndrome data 3 is stored.

In this case, when all the check data 6 indicate "00", the microprocessor circuit 26 determines that the demodulated data 2 stored in the data memory circuit 24 has been normally read.

Further, when it is determined that all the syndrome data 3 are not “00”, the position of the error symbol and the error that is a value for correcting the error are based on the syndrome data 3 stored in the data memory circuit 24.・ The pattern and
Calculated by the microprocessor circuit 26.

In this calculation process, the Galois field multiplication is performed by the error symbol calculation circuit 27.

That is, the calculation input information 7 from the microprocessor circuit 26 is expanded into an 8-element matrix, multiplied by 1-byte data, and the calculation result is reported to the microprocessor circuit 26 as calculation output data 8.

The syndrome when the syndrome calculation results are not all 00, that is, 16 bytes (S _{0 to} S ₁₅ ) of the error syndrome are shown as follows when the error symbol is 8 bytes, for example.

(1) S ₀ = e _m0 + e _m1 + ... + e _m7 (2) S ₁ = e _m0 α ^m0 + e _m1 α ^m1 + ……… + e _m7 α ^m7 (3) S ₂ = e _m0 α ^{2 (m0)} + e _m1 α ^{2 (m1)} ＋ ・ ・ ・ ＋ e _m7 α ^{2 (m7)} (4) S ₃ ＝ e _m0 α ^{3 (m0)} ＋ e _m1 α ^{3 (m1)} ＋ ・ ・ ・ ＋ e _m7 α ^{3 (m7)} (5) S ₄ ＝ e _m0 α ^{4 (m0)} ＋ e _m1 α ^{4 (m1)} ＋ ・ ・ ・ ＋ e _m7 α ^{4 (m7)} (6) S ₅ ＝ e _m0 α ^{5 (m0)} ＋ e _m1 α ^{5 (m1)} ＋ ・ ・ ・ ＋ e _m7 α ^{5 ( m7)} (7) S ₆ = e _m0 α ^{6 (m0)} ＋ e _m1 α ^{6 (m1)} ＋… ＋ e _m7 α ^{6 (m7)} (8) S ₇ ＝ e _m0 α ^{7 (m0)} ＋ e _m1 α ^{7 (m1 )} +… ＋ e _m7 α ^{7 (m7)} (9) S ₈ ＝ e _m0 α ^{8 (m0)} ＋ e _m1 α ^{8 (m1)} ＋… ＋ e _m7 α ^{8 (m7)} (10) S ₉ ＝ e _m0 α ^{9 ( m0)} ＋ e _m1 α ^{9 (m1)} ＋ ・ ・ ・ ＋ e _m7 α ^{9 (m7)} (11) S ₁₀ ＝ e _m0 α ^{10 (m0)} ＋ e _m1 α ^{10 (m1)} ＋ ・ ・ ・ ＋ e _m7 α ^{10 (m7)} (12) S ₁₁ = e _m0 α ^{11 (m0)} ＋ e _m1 α ^{11 (m1)} ＋ ・ ・ ・ ＋ e _m7 α ^{11 (m7)} (13) S ₁₂ ＝ e _m0 α ^{12 (m0)} ＋ e _m1 α ^{12 (m1)} ＋ ・ ・ ・ ＋ e _m7 α ^{12 (m7)} (14) S ₁₃ = e _m0 α ^{13 (m0)} ＋ e _m1 α ^{13 (m1)} ＋… ＋ e _m7 α ^{13 (m7)} (15) S ₁₄ ＝ e _m0 α ^{14 (m0)} ＋ e _m1 α ^{14 (m1)} ＋ ・ ・ ・ ＋ e _m7 α ^{14 (m7)} (16) S ₁₅ ＝ e _m0 α ^{15 (m0)} ＋ e _m1 α ^{15 (m1)} ＋ ・ ・ ・ ＋ e _m7 α ^{15 (m7)} However, , 8 bytes error symbol In the above formulas (1) to (16), m0 to m7 indicate error positions,
e _{m0 to} e _m7 indicate the error pattern.

Regarding the error location polynomial σ (χ) in the Reed-Solomon codeword, (17) σ (χ) = χ ⁸ + σ ₁ χ ⁷ + σ ₂ χ ⁶ + σ ₃ χ ⁵ + σ ₄ χ ⁴ + σ ₅ χ ³ + σ ₆ χ ² + σ ₇ χ + σ ₈ = 0.

However, the number of error symbols is 8, and σ
The coefficients σ _{1 to} σ ₈ of (χ) have a relationship with the error syndromes S _{0 to} S _{15 in} this decoding as shown by the following equations (18) to (25).

(18) S ₈ + S ₇ σ ₁ + S ₆ σ ₂ + S ₅ σ ₃ + S ₄ σ ₄ + S ₃ σ ₅ + S ₂ σ ₆ + S ₁ σ ₇ + S ₀ σ ₈ = 0 (19) S ₉ + S ₈ σ ₁ + S ₇ σ ₂ + S ₆ σ ₃ + S ₅ σ ₄ + S ₄ σ ₅ + S ₃ σ ₆ + S ₂ σ ₇ + S ₁ σ ₈ = 0 (20) S ₁₀ + S ₉ σ ₁ + S ₈ σ ₂ + S ₇ σ ₃ + S ₆ σ ₄ + S ₅ σ ₅ + S ₄ σ ₆ + S ₃ σ ₇ + S ₁ σ ₈ = 0 (21) S ₁₁ + S ₁₀ σ ₁ + S ₉ σ ₂ + S ₈ σ ₃ + S ₇ σ ₄ + S ₆ σ ₅ + S ₅ σ ₆ + S ₄ σ ₇ + S ₃ σ ₈ = 0 (22) S ₁₂ + S ₁₁ σ ₁ + S ₁₀ σ ₂ + S ₉ σ ₃ + S ₈ σ ₄ + S ₇ σ ₅ + S ₆ σ ₆ + S ₅ σ ₇ + S ₄ σ ₈ = 0 (23) S ₁₃ + S ₁₂ σ ₁ + S ₁₁ σ ₂ + S ₁₀ σ ₃ + S ₉ σ ₄ + S ₈ σ ₅ + S ₇ σ ₆ + S ₆ σ ₇ + S ₅ σ ₈ = 0 (24) S ₁₄ + S ₁₃ σ ₁ + S ₁₂ σ ₂ + S ₁₁ σ _{3 + S 10 σ 4 + S} 9 σ 5 + S 8 σ 6 + S 7 σ 7 + S 6 σ 8 = 0 (25) S 15 + S 14 σ 1 + S 13 σ 2 + S 12 σ 3 In _{S 11 σ 4 + S 10 σ} 5 + S 9 σ 6 + S 8 σ 7 + S 7 σ error detecting apparatus ₈ = 0 This example micro-processor circuit 26, and the error symbol calculation circuit 27,
The error location and the error pattern are calculated from these relational expressions (1) to (25).

Regarding the calculation procedure, first, relational expressions (18) to (2
5) is used to calculate σ ₁ to σ ₈ , and then the error locations α ^{m0 to} α ^m7 are calculated from the relational expression (17).
Calculate error patterns e _{m0 to} e _m7 .

FIG. 3 is a configuration diagram of the error location polynomial coefficient and the error pattern calculation circuit in the error symbol calculation circuit according to the embodiment of the present invention.

Coefficients of the error location polynomial in the error symbol calculation circuit 27 of this embodiment, and calculation circuit error pattern calculation data M1~M4, α ^M1 → M ^M1 conversion circuit 32, α ^M3 → M ^M3 conversion circuit 33 , M ^M1 × α ^M2 multiplication circuit 34,
M ^M3 × α ^M4 multiplication circuit 35 and EOR circuit 36
_In order to calculate _{1 to} σ ₈ , from the relational expressions (1) to (25),
σ ₈ to σ ₂ are sequentially deleted, and σ ₁ is calculated. Similarly, σ ₂ to σ ₈ are calculated.

First, in order to calculate σ _{1 to} σ ₈ , the calculation data M1 and M2 and the calculation data M3 and M4 set through the calculation input data 7 by the microprocessor circuit 26 are respectively multiplied, and the respective calculation results are obtained. EOR is performed by the EOR circuit 36, and the calculated output data 8 is reported to the microprocessor circuit 26.

In this multiplication method, the contents of the calculation data M1 and M3 are the α ^M1 → M ^M1 conversion circuit 32 and the α ^M3 → M ^M3 conversion circuit.
At 33, the matrix data 9 are expanded respectively, and further multiplied by the M ^M1 × α ^M2 multiplication circuit 34 and the M ^M3 × α ^M4 multiplication circuit 35, respectively, and the multiplication data 10 are obtained by the EOR circuit 36. EORed.

Further, in this calculation circuit, for obtaining a first sigma _1, when erasing sigma _8, it sets the S ₈ that no takes σ ₁ ~σ ₈ relational expression (18) in the calculation data M1, equation (19 ), The coefficient S ₁ of σ ₈ is set to M2. Alternatively, S ₃ which is not multiplied by σ ₁ to σ ₈ of the relational expression (19) is set to the calculation data M3, and the coefficient S ₀ of σ ₈ of the relational expression (18) is set to the calculation data M4 to perform the calculation. .

The calculated result thus obtained is set as K ₀₀ , and
It is stored in the processor circuit 26.

Next, set the coefficient S ₇ of σ ₁ in relational expression (18) to M1,
The coefficient S ₈ of σ ₁ of the relational expression (19) is set in the calculation data M3 to perform the calculation. For the calculation data M2 and M4, S ₁ and S ₀ that have already been set in the previous calculation are used.

This calculation result is _designated as K ₀₁ , and the microprocessor circuit 2
Remember in 6. Further, the relation S ₆ of σ _{2 in} the relational expression (18) is set in the calculation data M1, and the coefficient S ₇ of σ ₂ in the relational expression (19) is set.
Is set in the calculation data M2, and the calculation result is set to K
Remember as ₀₂ . Thereafter, similarly, the coefficients of σ _{3 to} σ _{7 in} the relational expressions (18) and (19) are set, and the calculation results thereof are set to K _{03 to} K ₀₇ .

In this case, the relationship between the relations (18) and (19) is (26) K ₀₀ + K ₀₁ σ ₁ + K ₀₂ σ ₂ + K ₀₃ σ ₃ + K ₀₄ σ ₄ + K ₀₅ σ ₅ + K ₀₆ σ ₆ + K ₀₇ σ ₇ = 0.

The same calculation is performed between the relational expressions (19) and (20), and the calculation result is set to K _{10 to} K ₁₇ , (27) K ₁₀ + K ₁₁ σ ₁ + K ₁₂ σ ₂ + K ₁₃ σ ₃ + K The relational expression of ₁₄ σ ₄ + K ₁₅ σ ₅ + K ₁₆ σ ₆ + K ₁₇ σ ₇ = 0 is obtained.

In relational expressions (20) and (21), the calculation result is K ₂₀ to K.
_Assuming that ₂₇ , (28) K ₂₀ + K ₂₁ σ ₁ + K ₂₂ σ ₂ + K ₂₃ σ ₃ + K ₂₄ σ ₄ + K ₂₅ σ ₅ + K ₂₆ σ ₆ + K ₂₇ σ ₇ = 0.

In relational expressions (21) and (22), the calculation result is calculated as K ₃₀ to K.
_{Assuming 37} , (29) the relational expression of K ₃₀ + K ₃₁ σ ₁ + K ₃₂ σ ₂ + K ₃₃ σ ₃ + K ₃₄ σ ₄ + K ₃₅ σ ₅ + K ₃₆ σ ₆ + K ₃₇ σ ₇ = 0 is obtained.

With relational expressions (22) and (23), the calculation result is K ₄₀ to K.
_{Assuming 47} , (30) K ₄₀ + K ₄₁ σ ₁ + K ₄₂ σ ₂ + K ₄₃ σ ₃ + K ₄₄ σ ₄ + K ₄₅ σ ₅ + K ₄₆ σ ₆ + K ₄₇ σ ₇ = 0.

In relational expressions (23) and (24), the calculation result is calculated as K ₅₀ to K.
_Assuming that ₅₇ , (31) K ₅₀ + K ₅₁ σ ₁ + K ₅₂ σ ₂ + K ₅₃ σ ₃ + K ₅₄ σ ₄ + K ₅₅ σ ₅ + K ₅₆ σ ₆ + K ₅₇ σ ₇ = 0 is obtained.

In relational expressions (24) and (25), the calculation result is calculated as K ₆₀ to K.
_When it is set to ₆₇ , the relational expression of (32) K ₆₀ + K ₆₁ σ ₁ + K ₆₂ σ ₂ + K ₆₃ σ ₃ + K ₆₄ σ ₄ + K ₆₅ σ ₅ + K ₆₆ σ ₆ + K ₆₇ σ ₇ = 0 is obtained.

In these seven equations (26) to (32), σ ₈ is eliminated.

Thus, from relational expressions (26) to (32),
_{When 2 to} σ ₇ are deleted, a linear equation of σ ₁ is finally created, and σ ₁ can be calculated. Note that σ _{2 to} σ ₈ are calculated similarly.

Further, by using σ ₁ to σ ₈ thus obtained, it is substituted into the relational expression (17) to obtain χ at which the calculation result becomes 0. This χ is the error location.

FIG. 4 is a configuration diagram of an error location calculating circuit in the error symbol calculating circuit according to the embodiment of the present invention.

The error location calculation circuit in the error symbol calculation circuit 27 of the present embodiment includes selectors S1, S2, S4, shift registers R1 to R7, α ^M1 → M ^M1 conversion circuit 32, M ^M1 × α ^M2.
Multiplication circuit 34, EOR circuit 36, α ^M3 → M ^M3 conversion circuit 33, M ^M3
× alpha ^M4 multiplication circuit 35, and the compare check circuit 43, the zero check circuit 44, includes a calculation control circuit 45, thus using σ ₁ ~σ ₈ found obtaining the error location.

Note that α ^M1 → M ^M1 conversion circuit 32, M ^M1 × α ^M2 multiplication circuit 3
4, EOR circuit 36, α ^M3 → M ^M3 conversion circuit 33, and M ^M3 × α ^M4
The multiplication circuit 35 executes the same calculation as in FIG.

The selector S1 switches the calculation input data 7 and the data of α ^{M1 + 1} , and the selector S2 switches the calculation input data 7 and the calculation output data 8. Further, the selector S4 switches between the calculation input data 7 and the output of the register R7.

The compare check circuit 43 compares and checks the content of the calculation data M1 and the content of the calculation data M5.

The zero check circuit 44 checks whether or not the calculated output data 8 is zero.

The shift registers R1 to R7 sequentially shift the contents of the calculation data M4.

The calculation control circuit 45 performs select control of the selectors S1, S2, S4, determines the output of the conveyor check circuit 43, and the output of the zero check circuit 44, and determines whether or not the calculation is continuously performed. judge. It also outputs the set pulse of the shift registers R1 to R7.

FIG. 5 is a flowchart for solving an error location polynomial in one embodiment of the present invention.

In the error location calculation circuit configured as shown in FIG. 4, when σ _{1 to} σ ₈ are substituted into the error location polynomial σ (χ) to obtain χ that becomes 0, first,
Calculation data M1 to M3 by the microprocessor circuit 26,
And set α ⁰ .

Then, the shift register R1~R7 the sigma ₈ through calculation data _{M4, σ 7, σ 6,} σ 5, σ 4, σ 3, sequentially sets the sigma _2, the calculation data M4 sets sigma _1. Further, the value of χ at the end of the calculation is set in the calculation data M5.

Finally, the calculation start instruction is given to the calculation control circuit 45 through the control instruction signal 12.

Thus, when the calculation start instruction is received from the microprocessor circuit 26, the calculation is executed by the control of the calculation control circuit 45 by using the contents of the calculation data M1 to M4 currently set as shown in FIG. (501).

For this calculation, α ⁰ × α ⁰ + α ⁰ × σ ₁ = α ⁰
+ Σ ₁ . However, α ⁰ = 1.

Next, it is determined whether the calculation of σ (χ) is completed (502).

When the calculation is not completed, the calculation result is put in the calculation data M2, and the contents of the shift register R7 are moved to the calculation data M4. At the same time as the contents of the shift register R7 are transferred, M4 → R1, R1 → R2, R2 → R3, R3 → R4, R4 → R5, R5 → R6, R6 →
The calculation is executed by shifting the contents of each, such as R7 (503).

For this calculation, α ⁰ (α ⁰ + σ ₁ ) + σ ₂ .

In this way, when the calculation is executed until the end of calculation, α ⁰ (α ⁰
(Α ⁰ (α ⁰ (α ⁰ (α ⁰ (α ⁰ (α ⁰ + σ ₁ ) +
σ ₂ ) + σ ₃ ) + σ ₄ ) + σ ₅ ) + σ ₆ ) + σ ₇ ) + σ
₈ , which is the relational expression of σ (χ) in the relational expression (17).

When the calculation is completed in this way (502), the result of 0 check of the calculation result is determined (504).

If the calculation result is determined to be 0 (504), the status signal 14 reports to the microprocessor circuit 26 that the calculation result is 0.

By this report, the microprocessor circuit 26 takes the contents of the calculation data M1 and recognizes that the calculation data M1 shows a solution.

When the calculation result is not 0 (504), further, the microprocessor circuit 26 compares and checks the calculation data M1 and M5 to determine whether or not it is the final calculation position set in the calculation data M5 (505). .

If it is not the final calculation position (505), the microprocessor circuit 26 issues a restart instruction through the control instruction signal 12 as shown in FIG.

Upon receiving this restart instruction, the calculation control circuit 45 updates α ^M1 of the content of the calculation data ^M1 to α ^{M1 + 1} and continues the calculation (506).

Thus, the error locations α ^{m0 to} α ^m7 , which are the solutions of the relational expression (17), are calculated.

The error locations α ^{m0 to} α calculated in this way
The ^m7, are substituted into equation (2) to (9), the method of calculating the σ ₁ ~σ _8, calculates the error pattern e _m0 to e _m7.

〔The invention's effect〕

According to the present invention, when the number of error symbols is large, the simultaneous equations are solved by hardware, so that the error location and the error pattern can be calculated at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram of an error detection device in one embodiment of the present invention, FIG. 2 is a data configuration diagram of user data and ECC data in one embodiment of the present invention, and FIG. 3 is one embodiment of the present invention. Of the error location polynomial in the error symbol calculation circuit of FIG. 4 and the configuration diagram of the error pattern calculation circuit. FIG. 4 shows the configuration of the error location calculation circuit in the error symbol calculation circuit of one embodiment of the present invention. 5 and 5 are flowcharts for solving the error location polynomial in the embodiment of the present invention. 1: read data, 2: demodulation data, 3: syndrome data, 4: error information, 5: correction data, 6: check data, 7:
Calculation input data, 8: Calculation output data, 9: Matrix data, 10: Multiplication data, 11: Check result, 12: Control instruction signal, 13: α ^{m1 + 1} data, 14: Status signal, 15: Calculation data
M1, 21: Drive device, 22: Demodulation circuit, 23: Syndrome arithmetic circuit, 24: Data memory circuit, 25: Syndrome check circuit, 26: Microprocessor circuit, 27: Error symbol calculation circuit, 32: α ^M1 → M ^M1 conversion circuit, 33: α ^M3 → M ^M3 conversion circuit, 34: M ^M1 × α ^M2 multiplication circuit, 35: M ^M3 × α ^M4 multiplication circuit, 3
6: EOR circuit, 43: Compare check circuit, 44: Zero check circuit, 45: Calculation control circuit 45, M1 to M4: Calculation data, R1 to R
7: Shift register, S1, S2, S4: Selector.

Claims (1)

(57) [Claims] 1. An error detection device for detecting an error symbol based on information composed of a data symbol and a check symbol generated from a generator polynomial based on a Reed-Solomon code, and calculation data from a microprocessor circuit (26). A first conversion circuit (32) for converting M1 into matrix data, and a first multiplication circuit (34) for multiplying the calculation data M2 from the microprocessor circuit (26) and the output of the first conversion circuit (32). ), A second conversion circuit (33) for converting the calculation data M3 from the microprocessor circuit (26) into matrix data, the calculation data M4 from the microprocessor circuit (26) and the second conversion circuit (33). ) And a second multiplication circuit (35) for multiplying the output of the second multiplication circuit (35) and an exclusive OR of the outputs of the first multiplication circuit (34) and the second multiplication circuit (35). Output to Lee black processor circuit (26)
It is composed of an EOR circuit (36) and the calculation data M1 to M4.
Error by inputting the error syndrome (S _{0 to} S ₁₅ ) from the microprocessor circuit (26) as
First to obtain the coefficients (σ _{1 to} σ ₈ ) of the location polynomial
Calculation means, a first conversion circuit (32) for converting the calculation data M1 into matrix data, the calculation data M2 and the first conversion circuit (3).
A first multiplication circuit (34) for multiplying the output of 2), a second conversion circuit (33) for converting the calculation data M3 into matrix data, a calculation data M4 and the second conversion circuit (33).
A second multiplication circuit (35) that multiplies the outputs of the two, an EOR circuit (36) that takes the exclusive OR of the outputs of the first multiplication circuit (34) and the second multiplication circuit (35), A zero check circuit (44) for performing a zero check of the output of the EOR circuit (36), a shift register (R1 to R7), the calculated data M1 and the data M5 indicating the final execution position are compared to determine the end of calculation. A compare check circuit (43), and a first selector (S1) for selecting either the data from the microprocessor circuit (26) or the output of the first conversion circuit (32) as the calculation data M1. A second selector (S2) for selecting either the data from the microprocessor circuit (26) or the output of the EOR circuit (36) as the calculation data M2, and the data from the microprocessor circuit (26) or the shift register( R1 to R7) third selector (S4) for selecting one of the outputs as the calculation data M4, and the selector (S1 to S4) receiving the outputs of the compare circuit (43) and the zero check circuit (44). )
And a calculation control circuit (45) for controlling the shift registers (R1 to R7), and the coefficients (σ _{1 to} σ ₈ ) of the error location polynomial obtained by the first calculation means are transferred to the shift register (R1). To R7), the second processing means for obtaining an actual error location value by inputting the error location parameter to the calculation data M1 to M3.