JP2545077Y2 - Chip type resistor - Google Patents
Chip type resistorInfo
- Publication number
- JP2545077Y2 JP2545077Y2 JP1991063114U JP6311491U JP2545077Y2 JP 2545077 Y2 JP2545077 Y2 JP 2545077Y2 JP 1991063114 U JP1991063114 U JP 1991063114U JP 6311491 U JP6311491 U JP 6311491U JP 2545077 Y2 JP2545077 Y2 JP 2545077Y2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- resistor
- chip
- bonding
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Details Of Resistors (AREA)
Description
【0001】[0001]
【産業上の利用分野】本考案は少なくとも一方電極をワ
イヤーボンデイング等で基板導体パターンに接続可能な
チツプ形抵抗器に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type resistor in which at least one electrode can be connected to a substrate conductor pattern by wire bonding or the like.
【0002】[0002]
【従来の技術】近年の小型・軽量化の要請より、使用さ
れる電気部品も小型化してきている。特に抵抗器等は、
更なる小型・軽量化が図られ、チツプ形の抵抗器が数多
く使用されてきている。この従来のチツプ形抵抗器を図
5に、係る抵抗器の基板への実装状態を図6に示す。図
5において、(A)は平面図、(B)は側断面図であ
る。2. Description of the Related Art In response to recent demands for miniaturization and weight reduction, electric components used have been miniaturized. Especially resistors etc.
For further miniaturization and weight reduction, many chip-type resistors have been used. FIG. 5 shows this conventional chip-type resistor, and FIG. 6 shows a state where such a resistor is mounted on a substrate. 5A is a plan view and FIG. 5B is a side sectional view.
【0003】従来のチツプ形抵抗器は、図5に示す様
に、例えばアルミナ基板1の両側面に端面電極5を設け
るとともに、アルミナ基板1の両側面近傍上下面に上下
電極2を配設し、係る電極2,5の配設されたアルミナ
基板1の一方面の上下電極2間に抵抗膜3を形成し、更
に抵抗膜3を略覆うようにガラス又はプラスチツクス樹
脂等の絶縁性皮膜4を形成した構成であつた。そして、
上下電極2の両端部近傍は絶縁性皮膜4で覆うこと無
く、電極部2が露出した状態としておく。In a conventional chip resistor, as shown in FIG. 5, for example, end electrodes 5 are provided on both side surfaces of an alumina substrate 1, and upper and lower electrodes 2 are provided on upper and lower surfaces near both side surfaces of the alumina substrate 1, for example. A resistive film 3 is formed between the upper and lower electrodes 2 on one surface of the alumina substrate 1 on which the electrodes 2 and 5 are disposed, and an insulating film 4 such as glass or plastic resin is formed so as to substantially cover the resistive film 3. Was formed. And
The vicinity of both ends of the upper and lower electrodes 2 is not covered with the insulating film 4 and the electrode portion 2 is exposed.
【0004】この図5に示す従来のチツプ形抵抗器の基
板への実装状態を図6に示す。図6において、10はP
CB基板、11はPCB基板10に配設された例えば銅
製の導体配線パターンであり、従来のチツプ形抵抗器は
この配線パターン11間に半田12で固定実装される。FIG. 6 shows a state in which the conventional chip type resistor shown in FIG. 5 is mounted on a substrate. In FIG. 6, 10 is P
The CB boards 11 are, for example, copper conductor wiring patterns provided on the PCB board 10, and a conventional chip-type resistor is fixedly mounted between the wiring patterns 11 with solder 12.
【0005】[0005]
【考案が解決使用とする課題】しかしながら、チツプ形
の抵抗器は、小型であるため基板に他の電気部品を実装
したのちに人が個別に実装することは殆ど不可能であ
り、実装後の調整等で抵抗器を接続するべき導体パター
ンに相違がある場合などに対処することはできなかつ
た。[Problems to be Solved by the Invention] However, since chip-type resistors are small in size, it is almost impossible for a person to individually mount them after mounting other electrical components on the board. It is impossible to cope with a case where there is a difference in a conductor pattern to which a resistor is to be connected due to adjustment or the like.
【0006】[0006]
【課題を解決するための手段】本考案は、上述の課題を
解決することを目的としてなされたもので、上述の課題
を解決する一手段として以下の構成を備える。即ち、基
板上に実装可能なチツプ抵抗器であつて、チツプの一方
側面より上面の端部に電極の形成された第1の電極部
と、チツプの前記第1の電極部の対向側面より上面の端
部に電極の形成された第2の電極部と、前記第1の電極
部の上面電極と前記第2の電極の上面電極間に形成され
た抵抗層とを備え、前記第1の電極部は更に前記一方側
面電極より下面に延出する下部電極が形成され、前記第
2の電極部は更に前記上面電極より前記抵抗層上部にワ
イヤーボンデイング等で接続可能な面積分延出する上部
電極が形成されていることを特徴とする。SUMMARY OF THE INVENTION The present invention has been made for the purpose of solving the above-mentioned problems, and has the following arrangement as one means for solving the above-mentioned problems. That is, a chip resistor that can be mounted on a substrate, wherein a first electrode portion having an electrode formed at an end on the upper surface from one side surface of the chip and an upper surface from a side opposite to the first electrode portion on the chip. A second electrode portion having an electrode formed at an end of the first electrode portion, and a resistive layer formed between an upper electrode of the first electrode portion and an upper electrode of the second electrode; The portion further includes a lower electrode extending from the one side electrode to the lower surface, and the second electrode portion further extends from the upper electrode by an area connectable to the upper portion of the resistance layer by wire bonding or the like. Is formed.
【0007】そして、例えば、前記第1及び第2の電極
部の下部電極及び上部電極はチツプ表面積の略60%と
することを特徴とする。[0007] For example, the lower electrode and the upper electrode of the first and second electrode portions are characterized in that they make up about 60% of the chip surface area.
【0008】[0008]
【作用】以上の構成において、抵抗膜が形成された主平
面側にボンデイング用の上部電極を形成し、下部電極を
プリント基板上に配設された導体パターンに確実に固定
することにより、プリント基板への配線方向が自由に選
択可能で抵抗器の基板への実装後に抵抗器を接続すべき
導体パターンを選択することができると共にボンデイン
グ落差を少なく抑えて生産効率を向上させることができ
る。また、同時に下部電極や上部電極の面積を大きくで
きることより、熱放散が良くなり、抵抗器の表面温度上
昇を緩和することができる。In the above configuration, the upper electrode for bonding is formed on the main plane side on which the resistive film is formed, and the lower electrode is securely fixed to the conductor pattern disposed on the printed circuit board, thereby improving the printed circuit board. It is possible to select a conductor pattern to which the resistor is to be connected after the resistor is mounted on the substrate, and it is possible to improve the production efficiency by minimizing the bonding head drop. In addition, since the area of the lower electrode and the upper electrode can be increased at the same time, the heat dissipation is improved, and the rise in the surface temperature of the resistor can be reduced.
【0009】[0009]
【実施例】以下、図面を参照して本考案に係る一実施例
を詳細に説明する。図1乃至図4はは本考案に係る一実
施例を説明するための図であり、図1は本考案に係る一
実施例の構成を示す図、図2は本実施例の基板への実装
状態を示す平面図、図3は本実施例の配線方向の選択の
自由度を説明するための図、図4は本実施例の熱拡散効
果を示す図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below in detail with reference to the drawings. 1 to 4 are views for explaining an embodiment according to the present invention, FIG. 1 is a diagram showing a configuration of an embodiment according to the present invention, and FIG. 2 is a mounting of the embodiment on a substrate. FIG. 3 is a plan view showing the state, FIG. 3 is a diagram for explaining the degree of freedom in selecting the wiring direction of the present embodiment, and FIG. 4 is a diagram showing the heat diffusion effect of the present embodiment.
【0010】まず、図1を参照して本実施例の構造を説
明する。図1の(A)が本実施例の平面図、(B)が側
断面図である。図1において、上述した図5と同様構成
には同一番号を付し詳細説明を省略する。図1に示す本
実施例においては、図5に示す従来のチツプ形抵抗器の
両端部電極5よりアルミナ基板1の両側端部近傍の該ア
ルミナ基板1の両面に上下電極2を配設した構成に代
え、アルミナ基板1の図の上面の抵抗膜3の形成面にお
いては図5に示す従来の抵抗器の上下電極2と略同様の
上面電極部8,9を形成する。そして、アルミナ基板1
の下面部分については、一方の上面電極8形成面の端部
電極5より延びる広い面積の下部電極6を形成する。こ
れら各電極の形成は従来より一般的に用いられている方
法、例えば、印刷/エツチング等の方法で形成すること
ができる。First, the structure of this embodiment will be described with reference to FIG. FIG. 1A is a plan view of this embodiment, and FIG. 1B is a side sectional view. In FIG. 1, the same components as those in FIG. 5 described above are denoted by the same reference numerals, and detailed description is omitted. In the present embodiment shown in FIG. 1, the upper and lower electrodes 2 are arranged on both sides of the alumina substrate 1 near both ends of the alumina substrate 1 from the electrodes 5 at both ends of the conventional chip resistor shown in FIG. Instead, on the surface of the alumina substrate 1 where the resistive film 3 is formed on the upper surface of the drawing, upper surface electrode portions 8 and 9 substantially similar to the upper and lower electrodes 2 of the conventional resistor shown in FIG. 5 are formed. And the alumina substrate 1
The lower electrode 6 having a large area extending from the end electrode 5 on the surface on which one upper electrode 8 is formed is formed. Each of these electrodes can be formed by a method generally used conventionally, for example, a method such as printing / etching.
【0011】そして、アルミナ基板1の上面電極8,9
間に抵抗膜3を形成し、更に抵抗膜3を略覆うようにガ
ラス又はプラスチツクス樹脂等の絶縁性皮膜4を形成す
る。この時に、少なくとも下部電極6の形成されていな
い方の上面電極9の端部近傍は、絶縁性皮膜4で覆うこ
と無く電極部が露出した状態としておく。続いてこの様
にして抵抗皮膜3及び絶縁性皮膜4の形成された抵抗器
の下部電極の形成されていない方の上面電極9の端部露
出電極部より絶縁性皮膜4上部に渡り下部電極6と略同
様の面積のボンデイング電極7を形成する。The upper electrodes 8 and 9 of the alumina substrate 1
A resistive film 3 is formed therebetween, and an insulating film 4 such as glass or plastic resin is formed so as to substantially cover the resistive film 3. At this time, at least the vicinity of the end of the upper electrode 9 where the lower electrode 6 is not formed is not covered with the insulating film 4 so that the electrode portion is exposed. Subsequently, the lower electrode 6 extends over the insulating film 4 from the end exposed electrode portion of the upper electrode 9 where the lower electrode of the resistor having the resistive film 3 and the insulating film 4 is not formed. A bonding electrode 7 having substantially the same area as that described above is formed.
【0012】このボンデイング電極7は、上面電極9に
容易に剥離しないように固着できる方法であれば任意の
方法で固着してよい。例えば、ボンデイング電極となる
部分をパラジウム(Pb)等で活性化させ、この上に無
電解ニツケル(Ni)等をメツキして固着する無電解メ
ツキによる方法。あるいは、ボンデイング電極となる部
分に金(Au)、ニツケル(Ni)等をスパツタリング
または蒸着し、他の部分はマスキング等を行つて着膜し
ない様にするスパツタリング(蒸着)による方法。更
に、絶縁膜4がガラスの場合、ボンデイング電極となる
部分に、電極ペーストを印刷焼成して固着する方法など
任意の方法を採用できる。この様にして形成した下部電
極6及びボンデイング電極7は、チツプ形抵抗器の外形
が縦1.25mm〜2.5mmで横2.0mm〜5.0
mmの場合に、略その外形の60%である、縦は同じ
1.25mm〜2.5mmで横1.2mm〜3.0mm
程度に形成すればよい。なお、この両電極8,9は、下
部電極6が実装基板への固定を確実なものできる面積で
あれば足り、ボンデイング可能な広さを有していれば足
りる。電極面積は以上の例に限定されるものではない。The bonding electrode 7 may be fixed to the upper electrode 9 by any method as long as the bonding electrode 7 can be fixed so as not to be easily separated. For example, a method of activating a portion to be a bonding electrode with palladium (Pb) or the like and plating and fixing electroless nickel (Ni) or the like on the portion is a method using an electroless plating method. Alternatively, gold (Au), nickel (Ni), or the like is sputtered or vapor-deposited on a portion to be a bonding electrode, and the other portion is subjected to masking or the like to perform spattering (deposition) so as not to form a film. Further, when the insulating film 4 is made of glass, an arbitrary method such as a method of printing and firing an electrode paste on a portion to be a bonding electrode and fixing the same can be adopted. The lower electrode 6 and the bonding electrode 7 formed as described above have a chip type resistor having an outer shape of 1.25 mm to 2.5 mm in length and 2.0 mm to 5.0 mm in width.
mm, which is approximately 60% of the outer shape.
What is necessary is just to form it. The electrodes 8 and 9 only need to have an area that allows the lower electrode 6 to be securely fixed to the mounting substrate, and need only have an area that allows bonding. The electrode area is not limited to the above example.
【0013】以上の構成を備える本実施例のチツプ形抵
抗器の実装基板への実装状態を図2に示す。図2におい
て、20はPCB基板、21,22はPCB基板20に
配設された例えば銅製の導体配線パターンである。本実
施例のチツプ形抵抗器においては、PCB基板20への
固定は、配線パターン21,22の一方に、下部電極6
を図2に23で示す様に半田付け又は導電性接着剤で行
う。そして、他方の配線パターン21との電気的接続
は、ボンデイング電極7と配線パターン21とを導電性
ワイヤーで接続する。例えば、ボンデイングワイヤ25
を用い、ボンデイング電極7と配線パターン21間をボ
ンデイングにより接続する。FIG. 2 shows a state in which the chip type resistor of the present embodiment having the above configuration is mounted on a mounting board. In FIG. 2, reference numeral 20 denotes a PCB substrate, and reference numerals 22 and 22 denote, for example, copper conductor wiring patterns provided on the PCB substrate 20. In the chip-type resistor of this embodiment, the lower electrode 6 is fixed to one of the wiring patterns 21 and 22 on the PCB substrate 20.
Is performed by soldering or a conductive adhesive as shown by 23 in FIG. Then, for electrical connection with the other wiring pattern 21, the bonding electrode 7 and the wiring pattern 21 are connected by a conductive wire. For example, the bonding wire 25
Is used to connect the bonding electrode 7 and the wiring pattern 21 by bonding.
【0014】本実施例チツプ形抵抗器は、単に2つの配
線パターン間を接続できるばかりではなく、抵抗器を基
板に実装後に、接続する配線パターンを適時選択し、所
望の配線パターンと接続させることができる。このた
め、例えば、図3に示す様にPCB基板の配線パターン
を、31〜34に示すように4方向分配設し、配線パタ
ーン31に本実施例チツプ形抵抗器30の下部電極6が
電気的に接続状態となるように半田、又は導電性接着剤
で固定する。そして、その後、他の要因を考慮などし
て、配線パターン32〜34のいずれの配線パターンと
接続するかを決め、所望の配線パターンとボンデイング
電極7とを接続すればよい。The chip-type resistor of this embodiment can not only connect two wiring patterns, but also, after mounting the resistor on the substrate, appropriately select a wiring pattern to be connected and connect it to a desired wiring pattern. Can be. Therefore, for example, as shown in FIG. 3, the wiring pattern of the PCB substrate is distributed in four directions as shown at 31 to 34, and the lower electrode 6 of the chip type resistor 30 of this embodiment is electrically connected to the wiring pattern 31. Is fixed with solder or a conductive adhesive so as to be in a connected state. Then, it is only necessary to determine which of the wiring patterns 32 to 34 is to be connected in consideration of other factors, and to connect the desired wiring pattern to the bonding electrode 7.
【0015】たとえば、本実施例抵抗器を発振回路に用
いる場合には、発振させるべき周波数を接続すべき配線
パターンにより決定させることができる。また、同様
に、本実施例抵抗器を増幅回路や比較回路の閾値決定要
素とする場合には、回路での閾値に対応して所望の配線
パターンを選択してボンデイング等によりボンデイング
電極7と接続すればよい。For example, when the resistor of this embodiment is used in an oscillation circuit, the frequency to be oscillated can be determined by the wiring pattern to be connected. Similarly, when the resistor of the present embodiment is used as a threshold value determining element of an amplifier circuit or a comparison circuit, a desired wiring pattern is selected according to the threshold value of the circuit and connected to the bonding electrode 7 by bonding or the like. do it.
【0016】また、本実施例抵抗器は、下部電極6及び
ボンデイング電極7が共に広い面積を有しているため、
熱放散性能の向上をも同時に果たしている。定格電力
0.5Wの抵抗器とした場合の本実施例抵抗器と、図5
に示す従来タイプの抵抗器との熱放散特性の相違を図4
に示す。図4に示すように、本実施例の抵抗器には熱放
散性能の向上が認められる。In the resistor of this embodiment, since both the lower electrode 6 and the bonding electrode 7 have a large area,
The heat dissipation performance is also improved. FIG. 5 shows a resistor according to the present embodiment in which a resistor having a rated power of 0.5 W is used.
Fig. 4 shows the difference in heat dissipation characteristics from the conventional resistor shown in Fig. 4.
Shown in As shown in FIG. 4, the heat dissipation performance of the resistor according to the present embodiment is improved.
【0017】以上説明したように本実施例によれば、プ
リント基板への配線方向が自由に選択可能であり、抵抗
器の基板への実装後においても抵抗器を接続すべき一方
の導体パターンを選択することができる。また、同時に
電極部の面積を広くしたことより、熱放散性能が良くな
り、抵抗器の表面温度上昇を緩和することができる。As described above, according to the present embodiment, the wiring direction on the printed circuit board can be freely selected, and even after the resistor is mounted on the board, one of the conductor patterns to which the resistor is to be connected can be used. You can choose. At the same time, by increasing the area of the electrode portion, the heat dissipation performance is improved, and the rise in the surface temperature of the resistor can be reduced.
【0018】[0018]
【考案の効果】以上説明したように本考案によれば、抵
抗膜が形成された主平面側にボンデイング用の上部電極
を形成し、下部電極をプリント基板上に配設された導体
パターンに確実に固定することにより、プリント基板へ
の配線方向が自由に選択可能で抵抗器の基板への実装後
に抵抗器を接続すべき導体パターンを選択することがで
きると共にボンデイング落差を少なく抑えて生産効率を
向上させることができる。また、同時に下部電極や上部
電極の面積を大きくできることより、熱放散が良くな
り、抵抗器の表面温度上昇を抑えることができる。As described above, according to the present invention, the upper electrode for bonding is formed on the main plane side on which the resistive film is formed, and the lower electrode is securely connected to the conductor pattern provided on the printed circuit board. By fixing the wiring to the printed circuit board, the wiring direction to the printed circuit board can be freely selected, the conductor pattern to which the resistor should be connected after the resistor is mounted on the board can be selected, and the bonding head is reduced to reduce the production efficiency. Can be improved. In addition, since the area of the lower electrode and the upper electrode can be increased at the same time, heat dissipation is improved, and a rise in the surface temperature of the resistor can be suppressed.
【図1】本考案に係る一実施例の構成を示す図である。FIG. 1 is a diagram showing a configuration of an embodiment according to the present invention.
【図2】本実施例の基板への実装状態を示す平面図であ
る。FIG. 2 is a plan view showing a mounting state of the present embodiment on a substrate.
【図3】本実施例の配線方向の選択の自由度を説明する
ための図である。FIG. 3 is a diagram for explaining a degree of freedom in selecting a wiring direction according to the embodiment;
【図4】本実施例の熱拡散効果を示す図である。FIG. 4 is a diagram showing a heat diffusion effect of the present embodiment.
【図5】従来のチツプ形抵抗器の構成を示す図である。FIG. 5 is a diagram showing a configuration of a conventional chip resistor.
【図6】従来の抵抗器の基板への実装状態を示す平面図
である。FIG. 6 is a plan view showing a state in which a conventional resistor is mounted on a substrate.
1 アルミナ基板 2 上下電極 3 抵抗膜 4 絶縁性皮膜 5 端面電極 6 下部電極 7 ボンデイング電極 8,9 上部電極 10,20 PCB基板 11,12,21,22,31〜34 配線パター
ンである。1 Alumina substrate 2 Upper and lower electrodes 3 Resistive film 4 Insulating film 5 End face electrode 6 Lower electrode 7 Bonding electrode 8,9 Upper electrode 10,20 PCB substrate 11,12,21,22,31-34 Wiring pattern.
Claims (2)
て、 チツプの一方側面より上面の端部に電極の形成された第
1の電極部と、 チツプの前記第1の電極部の対向側面より上面の端部に
電極の形成された第2の電極部と、 前記第1の電極部の上面電極と前記第2の電極の上面電
極間に形成された抵抗層とを備え、 前記第1の電極部は更に前記一方側面電極より下面に延
出する下部電極が形成され、前記第2の電極部は更に前
記上面電極より前記抵抗層上部にワイヤーボンデイング
等で接続可能な面積分延出する上部電極が形成されてい
ることを特徴とするチツプ形抵抗器。1. A chip resistor mountable on a substrate, comprising: a first electrode portion having an electrode formed at an end of an upper surface from one side surface of the chip; and opposing the first electrode portion of the chip. A second electrode portion having an electrode formed at an end portion of the upper surface from the side surface; and a resistive layer formed between the upper electrode of the first electrode portion and the upper electrode of the second electrode. The first electrode portion further has a lower electrode extending from the one side electrode to the lower surface, and the second electrode portion further extends from the upper electrode by an area connectable to the upper portion of the resistance layer by wire bonding or the like. A chip-type resistor having an upper electrode formed thereon.
び上部電極はチツプ表面積の略60%とすることを特徴
とする請求項1記載のチツプ形抵抗。2. The chip-type resistor according to claim 1, wherein the lower electrode and the upper electrode of said first and second electrode portions make up about 60% of the chip surface area.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1991063114U JP2545077Y2 (en) | 1991-08-09 | 1991-08-09 | Chip type resistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1991063114U JP2545077Y2 (en) | 1991-08-09 | 1991-08-09 | Chip type resistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0518002U JPH0518002U (en) | 1993-03-05 |
JP2545077Y2 true JP2545077Y2 (en) | 1997-08-25 |
Family
ID=13219941
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1991063114U Expired - Fee Related JP2545077Y2 (en) | 1991-08-09 | 1991-08-09 | Chip type resistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2545077Y2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4707500B2 (en) * | 2005-08-18 | 2011-06-22 | ローム株式会社 | Chip resistor |
JPWO2013137338A1 (en) * | 2012-03-16 | 2015-08-03 | コーア株式会社 | Chip resistor for built-in substrate and manufacturing method thereof |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS578701U (en) * | 1980-06-13 | 1982-01-18 |
-
1991
- 1991-08-09 JP JP1991063114U patent/JP2545077Y2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0518002U (en) | 1993-03-05 |
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