JP2543554B2 - Dropout correction circuit - Google Patents

Description

The present invention relates to a dropout correction circuit in a video signal reproducing device or the like.

[Conventional technology]

In a video signal reproducing device for reproducing a video signal from a recording medium such as a video tape or a video disc, a dropout (hereinafter, referred to as
Write DO. ) A correction circuit is provided, and a time base collector (hereinafter referred to as TBC) is provided to correct the time base fluctuation of the reproduced video signal.

DO correction can be performed either before TBC or after TBC, but especially when directly processing a composite video signal such as NTSC, do it after TBC. Is preferred.
Therefore, as a configuration in such a case, for example, a configuration as shown in FIG. 5 has been proposed in Japanese Patent Laid-Open No. 61-69286.

In the circuit shown in FIG. 5, first, in the DO detector 50,
Detects the DO period of the playback video signal and corresponds to that period.
Output pulse. Next, in the DO mixer 51, the reproduced video signal and the DO pulse are mixed so that the DO period of the reproduced video signal becomes a predetermined level exceeding the white peak, for example. In TBC52, although the time base fluctuation of the reproduced video signal is removed, the video signal mixed with the DO pulse is input,
The same delay amount as the video signal delay generated by TBC52 is DO
Also given to pulse. Thereafter, the DO separation circuit 53 separates the mixed DO pulse by detecting the level difference, and the video signal is 1H (H is a horizontal cycle) in the DO correction switch 54 for a period corresponding to the DO pulse. )
It is replaced with the video signal delayed by 1H which is the output of the delay circuit 55.

[Problems to be Solved by the Invention]

In the above-mentioned conventional technique, a simple DO correction configuration is provided, but some points remain to be considered for welding. Hereinafter, this point will be described with reference to FIG.

First, as shown in FIG. 6A, when a color signal exists near the white level of the video signal, the first point is to separate the DO pulse mixed as a level higher than the white peak in the DO separation circuit 53. This is a point that the operation margin is insufficient when performing. Therefore, if the color signal level varies due to the transmission characteristics up to the DO separation circuit 53, the color signal may be erroneously separated from the DO pulse, resulting in an erroneous separation operation. There was also. Therefore, in order to solve this, when the level of the DO period is further increased, the dynamic range of transmission in the TBC52 is finite, so the level of the video signal must be reduced and the S / N ratio must be reduced. Leads to a decrease in
There was no adequate solution.

Next, the second point is that the switching timing of the DO correction switch 54 deviates from the true DO period due to a delay in the DO separation operation of the DO separation circuit 53, a transient response of the DO correction switch 54, and the like. , Fig. 6 (b)
As shown in, the uncorrected portion (hereinafter, referred to as a corrected scar) remains at one end or both ends of the DO portion, and the corrected scar greatly deteriorates the image quality.

Furthermore, the third point is that DO is added to the sync signal part of the video signal.
If a DO pulse (hereinafter, referred to as a DO flag) is mixed in the DO mixer 51 at a level higher than the white peak, the timing of the sync signal will be shifted as a result. This causes a malfunction in the TBC52 in the latter stage.

The present invention has been made in view of the above-mentioned problems to be considered in the conventional technology, and an object of the present invention is mainly to perform a stable operation without causing an erroneous operation such as an erroneous separation operation. To provide an out correction circuit.

[Means for solving the problem]

In order to achieve the above object, in the present invention, a first means for detecting a DO period of a reproduced video signal, the reproduced video signal is input, and the DO means is used by the first means. A second means for replacing the video signal with a DO flag fixed to a predetermined level and outputting the detected video signal during the detected period, and inputting the video signal output from the second means, the time axis of the video signal Third means for absorbing and outputting fluctuations, fourth means for inputting the video signal output from the third means, attenuating a color signal component of the video signal for output, and fourth means The DO flag of the video signal outputted from the third means by the DO flag.
Fifth means for detecting a period and the video signal output from the third means are input, and the video signal is correlated with the video signal during the period when the fifth means detects DO. And a sixth means for outputting the video signal after substituting it with a strong video signal.

[Action]

In the present invention, when the DO flag is separated from the video signal mixed with the DO flag in the fifth means, first, the color signal component in the video signal is attenuated in the fourth means, Since they are separated, the operation margin at the time of separation is expanded, and stable operation can be performed without causing an erroneous separation operation as in the past.

Further, in addition to the above configuration, the fifth means is provided.
The third means for expanding the period detected as DO (that is, the DO period indicated by the separated DO flag) and the third means and the sixth means are provided between the third means and the sixth means. And an eighth means for delaying the video signal output from the DO section, the rear end section of the DO section is widened by the seventh section, and the front section of the DO section is expanded by the eighth section. To spread the DO
Since the correction can be performed, a correction scar does not remain unlike the conventional case.

Furthermore, means for correcting DO generated in the synchronizing signal portion of the reproduced video signal is provided, a time axis error is detected from the signal corrected by the correction means, and TBC is detected based on the time axis error. In the case where the time axis fluctuation of the video signal output from the second means is absorbed by the third means which is, even if DO occurs in the sync signal portion, the TBC malfunctions as in the conventional case. There is no such thing as triggering.

〔Example〕

 Examples of the present invention will be described below.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, 1 is a DO detector, 2 is an FM demodulator, 3 is a clamp circuit, 4 is a DO flag switch, 5 is a reference voltage source, 6 is a variable delay element, 7 is a drive circuit, and 8 is a time axis error. Detector, 9 is a color subcarrier (hereinafter referred to as F _sc ) notch filter, 10 is a clamp circuit, 11 is a comparator, 12 is a reference voltage source, 13 is a pulse delay circuit, 14 is an OR circuit,
15 is a delay circuit, 16 is a DO correction switch, 17 is a 1H delay circuit,
Is. The variable delay element 6, the driving circuit 7, and the time axis error detector 8 form a TBC.

As shown in FIG. 1, the reproduced FM signal is transmitted to the DO detector 1 and
Input to FM demodulator 2. DO detector 1 is the DO of the playback FM signal
The period is detected and the detection result is sent to the DO flag switch 4. Further, the FM demodulator 2 restores the video signal from the reproduced FM signal. Then, the clamp circuit 3 gives a DC level to the video signal and sends it to one input of the DO flag switch 4. A constant voltage higher than the voltage value of the white level of the video signal (or lower than the voltage value of the sync tip) is applied to the other input of the DO flag switch 4 from the reference voltage source 5.

The DO flag switch 4 normally selects the input on the clamp circuit 3 side, and the video signal from the clamp circuit 3 is output as it is, but the period during which the DO detector 1 detects DO is the reference signal. By selecting the input on the voltage source 5 side, a constant voltage is output instead of the video signal. As a result, the video signal and the DO flag (that is, the DO pulse) indicating the DO period are mixed, and the video signal with the DO flag is input to the variable delay element 6.

On the other hand, the time axis error detector 8 detects the time axis error of the signal output from the DO correction switch 16. The drive circuit 7 changes the delay amount of the variable delay element 6 based on the detected time axis error. As a result, the variable delay element 6 corrects the time base fluctuation included in the input video signal with the DO flag. That is, at this time, the same delay amount is given to the DO flag and the video signal. A CCD is used as the variable delay element 6.

Next, the video signal output from the variable delay element 6 is F
It is supplied to the _sc notch filter 9 and the delay circuit 15. The F _sc notch filter 9 attenuates the chrominance signal component in the supplied video signal. After that, the clamp circuit 10 gives a DC level to the video signal and sends it to one input of the comparator 11. Further, the other input of the comparator 11 has a voltage value slightly lower than the level of the DO flag from the reference voltage source 12 (if the DO flag is mixed as a level lower than the voltage value of the synchronization tip, A voltage value slightly higher than the DO flag level) is given.

The comparator 11 compares the video signal from the clamp circuit 10 with the voltage value given by the reference voltage source 12, and separates the DO flag contained in the video signal. Where this separated
The DO flag is for the video signal output from the variable delay element 6.
Indicates the DO period. The pulse delay circuit 13 and the OR circuit 14 are
The pulse trailing edge of the DO flag (that is, the DO pulse) output from the comparator 11 is extended and the pulse width is enlarged.

In the delay circuit 15, the DO flag is F _sc notch filter 9
A fixed delay, which is the same as or slightly longer than the delay time from the time to the OR circuit 14 is given to the video signal output from the variable delay element 6. As a result, the DO period indicated by the DO flag whose pulse width has been expanded can wrap around the true DO period in the video signal. Also, the 1H delay circuit 17 has 1H
Create a delayed video signal.

The DO correction switch 16 normally outputs the video signal from the delay circuit 15 as it is, but the DO period indicated by the DO flag obtained by expanding the pulse width from the OR circuit 14 is replaced by the video signal from the delay circuit 15. Then, the 1H delay circuit 17 outputs the 1H delayed video signal to perform DO correction.

According to this embodiment, in the F _sc notch filter 9,
The DO flag is separated in the comparator 11 after the color signal component in the video signal is attenuated. Therefore, the operation margin for separating the DO flag in the comparator 11 is expanded, and the erroneous separation operation is performed. Stable operation can be performed without causing

Further, the pulse delay circuit 13, the OR circuit 14, and the delay circuit 15 allow the DO correction switch 16 to perform the DO correction so as to wrap the true DO period. Therefore, FIG. 6 (b)
There is no correction scar as shown in.

Furthermore, the DO correction switch 16 performs DO correction including the sync signal part of the video signal, and the TBC also obtains the time base error from the video signal for which DO correction has been performed for such sync signal part. Since the time base fluctuation is corrected, malfunction does not occur unlike the conventional case.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

In FIG. 2, components having the same functions as those of the components shown in FIG. 1 are designated by the same reference numerals.

In this embodiment, as shown in FIG. 2, a pulse delay circuit 18, an OR circuit 19, an analog-digital converter (hereinafter referred to as ADC) 20, a data selector 21 are added to the configuration of the embodiment shown in FIG. ,
A digital / analog converter (hereinafter referred to as a DAC) 22 and a field memory 23 are added.

The operation of the newly added portion in this embodiment will be described below.

The ADC 20 converts the video signal output from the DO correction switch 16 into digital data and sends it to one input of the data selector 21. Further, the field memory 23 creates a video signal delayed by a field (262 horizontal cycles) and sends it to the other input of the data selector 21. On the other hand, the pulse delay circuit 18 and the OR circuit 19 further expand the pulse width of the DO flag output from the OR circuit 14 so as to compensate for the delay in the ADC 20. The data selector 21 normally outputs the digital data (that is, the digitized video signal) from the ADC 20 as it is, but the pulse width from the OR circuit 19 is expanded.
During the DO period indicated by the DO flag, the field-delayed video signal from the field memory 23 is output to perform DO correction.
The DAC 22 converts the DO-corrected digital data into an analog video signal and outputs it.

According to the present embodiment, the video signal from the ADC 20 and the video signal from the field memory 23 delayed by the field (262 horizontal periods) have the same phase of the color signal, and therefore, when DO correction is performed in the data selector 21. It is possible to correct not only the luminance signal but also the color signal.

In the present embodiment, as described above, the DO correction is performed in the data selector 21 by replacement with the field-delayed video signal (field correction).
The DO correction switch 16 performs correction by replacing (line correction) with the video signal delayed by 1H, and when DO occurs in the synchronization signal part, the TBC causes a malfunction in the time axis error detection operation as in the past. It is done to prevent it from happening.

Therefore, the DO correction switch 16 and the 1H delay circuit 17 are deleted,
A modification in which the output of the delay circuit 15 is directly connected to the ADC 20 can be considered. In this case, a sync separation circuit and an inexpensive pulse delay circuit are provided, the sync signal is separated from the video signal output from the delay circuit 15 by the sync separation circuit, and the sync signal and the sync signal are separated. By the pulse delay circuit
It suffices to switch the 1H-delayed signal and output according to the separated DO flag, perform DO correction only on the synchronization signal portion, and input the corrected signal to the time axis error detector 8.

Further, in this embodiment, the DO flag is a pulse delay circuit.
If a correction scar remains on one end (leading edge) of the DO part due to the delay time from 18 to the OR circuit 19, insert a digital data delay circuit between the ADC 20 and data selector 21. You can do it.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

In FIG. 3, components having the same functions as those of the constituent elements shown in FIG. 1 or 2 are designated by the same reference numerals.

This embodiment is an example in which a digital memory is used for TBC, and as shown in FIG. 3, the TBC is converted by the digital memory 26 for TBC, the write control circuit 28, the read control circuit 29 and the time axis error detector 27. I am configuring. Further, 25 is a data selector, 30 is a digital data delay circuit, 31 is a digital data F _sc notch filter, and 32 is a digital data 255 level detector.

As shown in FIG. 3, the DO detector 1 detects the DO period of the reproduced FM signal and sends the detection result to the time axis error detector 27 and the data selector 25. The time axis error detector 27 detects a time axis error from the video signal demodulated by the FM demodulator 2. At this time, in the time axis error detector 27, in order to prevent the TBC from malfunctioning due to DO, the DO correction of the synchronization signal portion is performed based on the detection result from the DO detector 1 as described in the above embodiment. After that, the time axis error is detected, or the detected time axis error is invalidated during the DO period.

Further, the ADC 20 converts the video signal demodulated by the FM demodulator 2 into digital data and sends it to one input of the data selector 25. Although this digital data (that is, the digitized video signal) is treated as 8 bits in the following description, it is not limited to these. Data indicating "255" (maximum value data in 8-bit data) is supplied to the other input of the data selector 25 (note that the minimum value data in 8-bit data is "0").
May be supplied instead. ). The data selector 25 normally outputs the digital data from the ADC 20 as it is, but during the period when it is detected as DO by the DO detector 1, data indicating "255" is output instead of the digital data from the ADC 20. Output. As a result, the DO flag is mixed with the digital data (digitized video signal).

In the digital memory 26, the write control circuit 28 controls the write operation according to the time axis error detected by the time axis error detector 27, and the read control circuit
The read operation is controlled by 29. As a result, in the digital in which the DO flag is mixed, the time base fluctuation is absorbed in the digital memory 26.

In the digital data (digitized video signal) output from the digital memory 26, the color signal component is attenuated by the F _sc notch filter 31, and the data indicating “255” is detected by the 255 level detector 32 (“0 , A 0 level detector is used.) As a result, the DO flag is separated from the digital data.

The pulse delay circuit 18 and the OR circuit 19 extend the pulse trailing edge of the separated DO flag (that is, the DO pulse) to increase the pulse width. In addition, the delay circuit 30 includes a digital memory 26.
A fixed delay is given to the digital data (digitalized video signal) output from the. As a result, the data selector 21 replaces the digital data with the field-delayed video signal from the field memory 23 so as to wrap the true DO period, and performs DO correction. Then, the DO-corrected digital data is converted into an analog video signal in the DAC 22 and output.

Finally, FIG. 4 is a circuit diagram and a block diagram showing a specific example of the F _sc notch filter used in each of the above-described embodiments, and (a) is an analog used in the embodiments of FIGS. 1 and 2. _Shows the F _sc notch filter 9 of the circuit,
(B) shows the F _sc notch filter 31 of the digital circuit used in the embodiment of FIG.

In FIG. 4 (a), R1 and R2 are resistors, L is a coil,
C is a capacitor, and in FIG. 4B, 40 is a delay circuit, 41 and 42 are multipliers, and 43 is an adder.

It should be noted that FIG. 4B shows a circuit when sampling is performed at a clock rate which is four times as high as the frequency of the color subcarrier (F _sc ), and the delay circuit 40 is equivalent to two clocks of the above clock. A delay 2D (D is a unit clock delay) is given. Therefore, the phase of the chrominance signal is inverted between the digital data output from the delay circuit 40 and the digital data without delay, and this F _sc notch filter uses this fact to multiply both digital data by the multiplier 41. , 42 to make an appropriate ratio and add by the adder 43 to attenuate the color signal level.

〔The invention's effect〕

As described above, according to the present invention, when the DO flag is separated from the video signal in which the DO flag is mixed, the color signal component in the video signal is attenuated and then separated. The operation margin is expanded, the threshold value for separation can be easily determined, and stable operation can be performed without causing an erroneous separation operation as in the related art.

Further, when a means for expanding the DO period indicated by the separated DO flag is provided, the DO correction can be performed for a period wider than the true DO period, so that a correction scar remains as in the conventional case. Never.

Furthermore, when the time axis error used in the TBC is detected from the signal after the DO correction of the sync signal portion, the malfunction of the TBC can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention, and FIG.
FIG. 4 is a block diagram showing a second embodiment of the present invention, FIG. 3 is a block diagram showing a third embodiment of the present invention, and FIG. 4 (a).
1 is a circuit diagram showing a concrete example of the F _sc notch filter of FIGS. 1 and 2, FIG. 4 (b) is a block diagram showing a concrete example of the F _sc notch filter of FIG. 3, and FIG. FIG. 6 is a block diagram showing a conventional dropout correction circuit, and FIG. 6 is a waveform diagram showing signal waveforms of a signal before DO correction and a signal after DO correction in FIG. Explanation of symbols 1 ... DO detector, 4 ... DO flag switch, 6 ... variable delay element, 8,27 ... time axis error detector, 9,31 ... F _sc notch filter, 11 ... comparator , 13,18 …… Pulse delay circuit, 14,19 …… OR circuit, 15,30 …… Delay circuit, 16 …… 1H delay circuit, 17 …… DO correction switch, 21,25 …… Data selector, 23… … Field memory, 26 …… Digital memory, 32 …… 255 level detector.

Claims (4)

(57) [Claims] 1. A dropout correction circuit in an apparatus for recording and reproducing a video signal or for reproducing only a video signal,
First means for detecting a dropout period of a reproduced video signal, and inputting the reproduced video signal, and for a period of time when the first means detects a dropout, the video signal is kept at a predetermined level. Second means for replacing the dropout flag signal with a fixed value and outputting the same, and a third means for inputting the video signal output from the second means and absorbing and outputting the time-axis fluctuation of the video signal. Means for inputting the video signal output from the third means, attenuating the color signal component of the video signal for output, and the dropout from the output signal of the fourth means. Fifth means for separating a flag signal and detecting a dropout period of the video signal output from the third means by the dropout flag signal; and the video signal output from the third means. Enter A sixth means for time is detected to be dropout, to replace the video signal to a strong video signal correlated with the video signal output by means of the fifth,
A dropout correction circuit having: 2. A dropout correction circuit according to claim 1, wherein the fifth means extends a period in which the dropout is detected as a dropout, the third means and the sixth means. An eighth means for delaying the video signal output from the third means is provided between the dropout correction circuit. 3. The dropout correction circuit according to claim 1 or 2, further comprising means for correcting a dropout occurring in a sync signal portion of the reproduced video signal, and the dropout correction circuit corrected the dropout. A time axis error is detected from the signal, and the time axis fluctuation of the video signal output from the second means is absorbed by the third means based on the time axis error. Dropout correction circuit. 4. The dropout correction circuit according to any one of claims 1 to 3, wherein the video signal output from the third means is replaced by the sixth means. The dropout correction circuit, wherein the video signal having a strong correlation is a field-delayed signal or a frame-delayed signal of the video signal output from the sixth means.