JPH01180192A - Dropout correction circuit - Google Patents

Abstract

PURPOSE:To expand operating margin in case of separation, to facilitate the decision of a threshold value and to avoid mis-separation by attenuating a color signal component in a video signal when a dropout flag is separated from a video signal mixed with the flag while attenuating a color signal component in a video signal. CONSTITUTION:A dropout correction circuit receiving a reproduced FM signal and outputting it as a video signal is provided with a dropout(DO) detector 1, an FM demodulator 2, a clamp circuit 3, a DO flag switch 4, a variable delay element 6, a drive circuit 7, a time axis error detector 8, a color subcarrier (FSC) notch filter 9 added newly, a clamp circuit 10, a comparator 11, a pulse delay circuit 13, an OR circuit 14, a delay circuit 15, a DO correction switch 16, and a 1H delay circuit 17. The notch filter 9 is provided in this way, then it is possible to separate the DO flag by the comparator 11 after the color signal component is attenuated and the separation margin in the comparator 11 is increased and no mis-separation is caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dropout correction circuit in a video signal reproducing device or the like.

[Conventional technology]

In video signal reproducing devices that reproduce video signals from recording media such as video tapes and video disks, dropouts (hereinafter referred to as D
A correction circuit (denoted as O) and a time base collector (hereinafter referred to as TBC) are provided for correcting time axis fluctuations of the reproduced video signal.

There are two ways to perform Do correction: one is to perform the Do correction before the TBC, and the other is to perform it after the TBC. In particular, when directly processing composite video signals such as NTSC, it is best to perform the Do correction after the TBC. is suitable. Therefore, as a configuration for such a case, for example, a configuration as shown in FIG. 5 has been proposed in Japanese Patent Laid-Open No. 61-69286.

In the circuit shown in FIG. 5, first, the DO detector 50 detects the DO period of the reproduced video signal, and outputs a Do pulse corresponding to the period. Next, in the Do mixer 51, the reproduced video signal and the Do pulse are mixed, for example,
Playback video signal paste.

The period is set to a predetermined level exceeding the white peak.

TBC52 removes time axis fluctuations of the reproduced video signal (
inputs a video signal mixed with the Do pulse, and the same amount of delay as the video signal delay generated by the TBC 52 is given to the Do pulse. Thereafter, the DO separation circuit 53 separates the mixed Do pulses by detecting the level difference, and the DO correction switch 54 converts the video signal into IH (H) for a period corresponding to the DO pulse.
is the horizontal period. ) Replaced with the IH-delayed video signal that is the output of the delay circuit 55.

[Problem to be solved by the invention]

Although the conventional technology described above provides a simple configuration for o correction, there are still some points that need to be taken into consideration. This point will be explained below using FIG. 6.

The first point is that, as shown in FIG. 6(a), when a color signal exists near the white level of the video signal, the DO pulse mixed at a level higher than the white peak is transferred to the Do separation circuit 5.
The problem is that there is insufficient operating margin when separating in No. 3. Therefore, if variations occur in the level of the color signal due to the transmission characteristics up to the Do separation circuit 53, there is a possibility that an erroneous separation operation may occur, such as separating the color signal by mistake from the Do pulse. There was also. Therefore,
In order to solve this problem, if the level of the DO period is made higher, the dynamic range of transmission in the TBC 52 is finite, so the level of the video signal has to be lowered, and the S/N decreases. Therefore, a satisfactory solution could not be reached.

The second point is that the switching timing of the Do correction switch 54 deviates from the true DO period due to the delay in the separation operation of the DO pulse in the Do separation circuit 53, the transient response of the DO correction switch 54, etc. , as shown in FIG. 6(b), a portion that is not corrected (hereinafter referred to as a correction scar) remains at one or both ends of the 00 portion, and this correction scar greatly reduces the image quality. I had lost it.

Furthermore, the third point is that Do
If this occurs, the Do mixer 51 applies a Do pulse (hereinafter referred to as D
It is written as o flag. ), the timing of the synchronization signal will shift, which will cause the subsequent TB
The problem is that this will induce a malfunction in the C52.

The present invention has been made in view of the problems to be considered in the prior art described above, and the purpose of the present invention is mainly to:
It is an object of the present invention to provide a dropout correction circuit that can perform stable operations without causing erroneous operations such as erroneous separation operations.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a first means for detecting a Do period of a reproduced video signal, and inputs the reproduced video signal and determines that it is Do by the first means. a second means for replacing and outputting the video signal with a DO flag fixed at a predetermined level during the detected period; and inputting the video signal output from the second means, and adjusting the time axis of the video signal. a third means for absorbing and outputting fluctuations;
a fourth means for inputting the video signal output from the means and outputting the attenuated color signal component of the video signal;
The DO flag is separated from the output signal of the means of the D
a fifth means for detecting the DO period of the video signal output from the third means based on the O flag; and a fifth means for detecting the DO period of the video signal output from the third means; and sixth means for replacing the video signal with a video signal having a strong correlation with the video signal and outputting the video signal during a period in which it is detected that the video signal has a strong correlation with the video signal.

[Effect]

In the present invention, the fifth means is as described above.

When the DO flag is separated from the video signal in which the flags are mixed, the fourth means first attenuates the color signal component in the video signal and then separates it. is expanded, and stable operation can be performed without causing erroneous separation operations as in the conventional case.

In addition, in addition to the above-described configuration, D
a seventh means for expanding a period detected as O (that is, a Do period indicated by the separated DO flag); and a third means between the third means and the sixth means; and eighth means for delaying the video signal outputted from the video signal, the seventh means widens the rear end of the Do portion, and the eighth means widens the front end of the DO portion. Since the DO can be corrected widely, no correction scars remain as in the conventional case.

Furthermore, means for correcting DO occurring in the synchronization signal portion of the reproduced video signal is provided, a time axis error is detected from the signal corrected by the correction means, and TBC is determined based on the time axis error. When the third means absorbs the time axis fluctuation of the video signal output from the second means, even if a DO occurs in the synchronization signal part, it is not possible to There is no possibility of inducing malfunction.

〔Example〕

Examples of the present invention will be described below.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, 1 is a DO detector, 2 is an FM demodulator, and 3 is a DO detector.
is a clamp circuit, 4 is a DO flag switch, 5 is a reference voltage source, 6 is a variable delay element, 7 is a drive circuit, 8 is a time axis error detector, 9 is a color subcarrier (hereinafter referred to as F'sc) Notch filter, 10 is a clamp circuit, 11 is a comparator, 12 is a reference voltage source, 13 is a pulse delay circuit, 14 is an OR circuit, 15 is a delay circuit, 16 is a DO correction switch, 17 is an IH delay circuit, The variable delay element 6, drive circuit 71, and time axis error detector 8 constitute a TBC.

As shown in FIG. 1, the reproduced FM signal is input to a DO detector 1 and an FM demodulator 2. DO detector 1 plays FM
The Do period of the signal is detected and the detection result is sent to the DO flag switch 4. In addition, the FMfi adjuster 2 is a playback FM
Restore the video signal from the signal. And clamp circuit 3
gives a DC level to the video signal and sends it to one input of the Do flag switch 4. Further, to the other input of the Do flag switch 4, a constant voltage higher than the voltage value of the white level of the video signal (or lower than the voltage value of the synchronization leading edge) is applied from the reference voltage source 5.

The DO flag switch 4 normally selects the input on the clamp circuit 3 side, and the video signal from the clamp circuit 3 is output as is. By selecting the input on the voltage source 5 side, a constant voltage is output instead of the video signal. As a result,
The video signal and the DO flag (ie, Do pulse) indicating the DO period are mixed, and the video signal with the DO flag is input to the variable delay element 6.

On the other hand, the time axis error detector 8 detects the time axis error of the signal output from the Do correction switch 16. Drive circuit 7
changes the delay amount of the variable delay element 6 based on the detected time axis error. As a result, the variable delay element 6 corrects the time axis fluctuation contained in the inputted video signal with the DO flag. That is, at this time, the same amount of delay is given to the Do flag and the video signal. still,
A CCD is used as the variable delay element 6.

Next, the video signal output from the variable delay element 6 is F
6F supplied to the sc notch filter 9 and delay circuit 15
The IC notch filter 9 attenuates the color signal component in the supplied video signal. Thereafter, the clamp circuit 10 gives a DC level to the video signal and sends it to one input of the comparator 11. Further, the other input of the comparator 11 is supplied with a voltage value slightly lower than the level of the DO flag from the reference voltage source 12 (if the Do flag is mixed as a level lower than the voltage value of the synchronization tip, A voltage value slightly higher than the level of the DO flag is applied.

The comparator 11 compares the video signal from the clamp circuit 1o with the voltage value given from the reference voltage source 12, and separates the Do flag included in the video signal. Here, the separated Do flag indicates the Do period of the video signal output from the variable delay element 6. The pulse delay circuit 13 and the 0RDO path 14 stretch the trailing edge of the pulse of the DO flag (ie, Do buff L/X) output from the comparator 11, thereby expanding the pulse width.

The delay circuit 15 gives the video signal output from the variable delay element 6 a fixed delay that is equal to or slightly larger than the delay time during which the Do flag reaches the Fsc notch filter 9 to the OR circuit 14. As a result, the DO period indicated by the DO flag with expanded pulse width is the true D in the video signal.
It becomes possible to wrap the O period. Also,
The IH delay circuit 17 creates an IH delayed video signal.

The Do correction switch 16 normally outputs the video signal from the delay circuit 15 as is, but during the DO period indicated by the DO flag with an expanded pulse width from the OR circuit 14, the video signal from the delay circuit 15 is output in place of the video signal from the delay circuit 15. , IH delay circuit 1
Do correction is performed by outputting the IH-delayed video signal from 7.

According to this embodiment, the F'sc notch filter 9 attenuates the color signal component in the video signal, and then the comparator 1
1 separates the DO flag, therefore, the operation margin for separating the DO flag in the comparator 11 is expanded, and stable operation can be performed without causing erroneous separation operation. .

Further, the pulse delay circuit 13. OR circuit 14. Delay circuit 1
5, the Do correction switch 16 can perform DO correction so as to encompass the true Do period, and therefore no correction scars as shown in FIG. 6(b) remain.

Furthermore, the Do correction switch 16 performs Do correction including the synchronization signal portion of the video signal, and the TBC obtains the time axis error from the video signal that has undergone DO correction for such synchronization signal portion as well. Since the time axis fluctuation is corrected, malfunctions do not occur as in the conventional case.

FIG. 2 is a block diagram showing a second embodiment of the invention.

In FIG. 2, components having the same functions as those shown in FIG. 1 are given the same numbers.

As shown in FIG. 2, this embodiment has a pulse delay circuit 18. OR circuit 19, analog
Digital converter (hereinafter referred to as ADC) 20. Data selector 21. Digital to analog converter (hereinafter referred to as DA)
It is written as C. ) 22° field memory 23 is added to each.

The operation of the newly added portion in this embodiment will be explained below.

The ADC 20 converts the video signal output from the DO correction switch 16 into digital data and sends it to the data selector 21.
to one of the inputs. In addition, the field memory 23
creates a video signal delayed by a field (262 horizontal periods) and sends it to the other input of the data selector 21. On the other hand, the pulse delay circuit 18 and the OR circuit 19 change the pulse width of the Do flag output from the OR circuit 14 to the ADC2.
It is further expanded to compensate for the delay at 0. The data selector 21 normally uses digital data from the ADC 20 (
That is, the digitized video signal) is output as is, but during the Do period indicated by the DO flag with an expanded pulse width from the OR circuit 19, the field-delayed video signal from the field memory 23 is output and the DO correction is performed. I do. D
The AC 22 converts the Do-corrected digital data into an analog video signal and outputs it.

According to this embodiment, the video signal from the ADC 20 and the video signal delayed by a field (262 horizontal periods) from the field memory 23 have exactly the same color signal phase, so when Do correction is performed in the data selector 21, , it is possible to correct not only the luminance signal but also the color signal.

In this embodiment, as described above, DO correction is performed in the data selector 21 by replacing the field-delayed video signal (field correction), and therefore, in the DO correction switch 16, the IH-delayed video signal is The correction performed by signal replacement (line correction) is performed in order to prevent the conventional malfunction in the time axis error detection operation in the TBC when DO occurs in the synchronization signal part. .

Therefore, a modification may be considered in which the Do correction switch 16 and the IH delay circuit 17 are deleted and the output of the delay circuit 15 is directly connected to the ADC 20. In this case, a sync separation circuit and an inexpensive pulse delay circuit are provided, and the sync signal is separated from the video signal output from the delay circuit 15 by the sync separation circuit, and the sync signal and the sync signal are separated. The signal delayed by IH by the pulse delay circuit is separated from the DO signal.
Switch and output according to the flag, only the synchronization signal part is D
O correction may be performed and the corrected signal may be input to the time axis error detector 8.

In addition, in this embodiment, due to the delay time from the time when the DO flag reaches the OR circuit 19 from the pulse delay circuit 18,
If a correction scar remains on one end (front edge) of the DO part,
Digital data between DC 20 and data selector 21
All you have to do is insert an evening delay circuit.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

In FIG. 3, components having the same functions as those shown in FIG. 1 or 2 are given the same numbers.

This embodiment is an example in which a digital memory is used for the TBC, and as shown in FIG. 3, the digital memory 26.
Write control circuit 28. A readout control circuit 29 and a time axis error detector 27 constitute a TBC. Further, 25 is a data selector, 30 is a delay circuit for digital data, 31 is an FSC notch filter for digital data, and 32 is a 255 level detector for digital data.

As shown in FIG. 3, the Do detector 1 detects the Do of the reproduced FM signal.
The period is detected and the detection result is sent to the time axis error detector 27 and the data selector 25.

The time axis error detector 27 detects a time axis error from the video signal demodulated by the FM demodulator 2. At this time, in order to prevent malfunction of the TBC due to Do, the time axis error detector 27 detects the Do of the synchronizing signal part based on the detection result from the Do detector 1, as described in the above embodiment.
Perform time axis error detection after correction, or
During the DO period, the detected time axis error is invalidated.

Further, the ADC 20 converts the video signal demodulated by the FM demodulator 2 into digital data and sends it to one input of the data selector 25 . Note that this digital data (i.e., digitized video signal) will be referred to as 8b in the following explanation.
Although it is treated as "IT", it is not limited to this.

The other input of the data selector 25 is r255J.
(maximum value data in 8-bit data) is supplied (note that data indicating "0", which is the minimum value data in 8-bit data, may be supplied instead). The data selector 25 usually uses the ADC 20
I am outputting the digital data as it is from Do
During the period detected as DO by detector 1, the ADC
r255. instead of digital data from 20. Outputs data indicating.

As a result, the DO flag is mixed into the digital data (digitized video signal).

Further, in the digital memory 26, a write operation is controlled by a write control circuit 28 according to a time axis error detected by a time axis error detector 27, and a read operation is controlled by a read control circuit 29. . As a result,
The digital data mixed with the DO flag has time axis fluctuations absorbed in the digital memory 26.

The digital data (digitized video signal) output from the digital memory 26 is sent to the Esc notch filter 3.
1, the color signal component is attenuated, and the 255 level detector 32 detects data indicating "255"("0").
”, use a 0 level detector. ), this results in separation of the DO flag from the digital data.

The pulse delay circuit 18 and the OR circuit 19 are connected to a separate Do
The pulse trailing edge of the flag (ie, Do pulse) is stretched to increase the pulse width. Further, the delay circuit 30 applies a fixed delay to the digital data (digitized video signal) output from the digital memory 26. With these, the data selector 21 transfers the digital data to the field memory 2 so as to wrap around the true DO period.
Replaced with the field-delayed video signal from D.
The digital data subjected to o correction and Do correction is converted into an analog video signal by the DAC 22 and output.

Finally, FIG. 4 shows the F used in each of the above-mentioned embodiments.
2 is a circuit diagram and a block diagram showing a specific example of a 'sc notch filter, in which (a) shows an analog circuit F'sc notch filter 9 used in the embodiments of FIGS. 1 and 2, and (b) shows a 3 shows an F'se notch filter 31 of the digital circuit used in the embodiment of FIG. 3;

In FIG. 4(a), R1 and R2 are resistors, L is a coil, and C is a capacitor. In FIG. 4(b), 40 is a delay circuit, 41.42 is a multiplier, and 43 is an adder. It is a vessel.

Note that FIG. 4(b) shows a circuit when sampling is performed at a clock rate that is four times the frequency of the color subcarrier (Fsc), and the delay circuit 40 has a delay of two clocks of the above clock. 2D (where D is the unit clock delay). Therefore, the phase of the color signal of the digital data output from the delay circuit 40 and the digital data without delay are inverted, and this FSC notch filter utilizes this fact to combine both digital data into the multiplier 41. 42 and an adder 43 at an appropriate ratio to attenuate the color signal level.

〔Effect of the invention〕

As explained above, according to the present invention, when separating the DO flag from the video signal in which the Do flag is mixed, the color signal component in the video signal is attenuated before separation.
The operational margin for separation is expanded, the threshold value for separation becomes easier to determine, and stable operation can be performed without causing erroneous separation operations as in the conventional case.

Furthermore, if a means for expanding the Do period indicated by the separated DO flag is provided, DO correction can be performed for a period wider than the true DO period, so that correction scars remain as in the past. Never.

Furthermore, if the time base error used in the TBC is detected from the signal after DO correction of the synchronization signal portion, malfunctions of the TBC can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a block diagram showing a second embodiment of the invention, FIG. 3 is a block diagram showing a third embodiment of the invention, and FIG. 4(a)
is a circuit diagram showing a specific example of the Esc notch filter shown in FIGS. 1 and 2, FIG. 4(b) is a block diagram showing a specific example of the F'sc notch filter shown in FIG. 3, and FIG. A block diagram showing a conventional dropout correction circuit, FIG.
2 is a waveform diagram showing signal waveforms of a signal before Do correction and a signal after Do correction in the figure. FIG. Explanation of symbols 1...DO detector, 4...DO flag switch, 6
... variable delay element, 8.27 ... time axis error detector, 9.31 ... l"sc notch filter, 11 ...
Comparator, 13.18...Pulse delay circuit, 14.19
...OR circuit, 15.30...Delay circuit, 16...
- IH delay circuit, 17...DO correction switch, 21.
25...Data selector, 23...Field memory, 26...Digital memory, 32...255 level detector. Agent Patent Attorney Akio Namiki Figure 1g4 (b) 5th Inbin Figure 6

Claims (1)

[Scope of Claims] 1. In a dropout correction circuit in a device that records and reproduces a video signal or only reproduces a video signal, a first means for detecting a dropout period of a reproduced video signal; and a first means for detecting a dropout period of a reproduced video signal; a second means for inputting a signal and outputting the video signal by replacing it with a dropout flag signal fixed at a predetermined level during a period when a dropout is detected by the first means; a third means for inputting the video signal output from the means, absorbing the time axis fluctuation of the video signal and outputting the same; fourth means for attenuating and outputting the color signal component; and separating the dropout flag signal from the output signal of the fourth means and outputting the dropout flag signal from the third means according to the dropout flag signal. a fifth means for detecting a dropout period of a video signal; and a method for inputting the video signal output from the third means, and detecting a period during which a dropout is detected by the fifth means, the video signal. A dropout correction circuit comprising: sixth means for replacing the video signal with a video signal having a strong correlation with the video signal and outputting the resultant video signal. 2. In the dropout correction circuit according to claim 1,
a seventh means for expanding the period detected as a dropout by the fifth means; and a video output from the third means between the third means and the sixth means. A dropout correction circuit comprising: eighth means for delaying a signal. 3. The dropout correction circuit according to claim 1 or 2, further comprising means for correcting a dropout occurring in a synchronization signal portion of the reproduced video signal, and the dropout correction circuit comprises means for correcting a dropout occurring in a synchronization signal portion of the reproduced video signal, and Dropout correction characterized in that an axis error is detected, and based on the detected time axis error, the third means absorbs the time axis fluctuation of the video signal output from the second means. circuit. 4. In the dropout correction circuit according to any one of claims 1 to 3, the sixth means replaces the video signal output from the third means with a strong correlation. A dropout correction circuit characterized in that the video signal is a field-delayed signal or a frame-delayed signal of the video signal output from the sixth means.