JPH08116552A - Video signal reproducing device - Google Patents

Abstract

PURPOSE: To obtain the inexpensive video signal reproducing device in which dropout compensation, jitter suppression and Y/C separation are conducted with a 1-horizontal scanning time delay line and a variable delay element for one horizontal time. CONSTITUTION: An output of an A/D converter 4 is limited to prevent a value '0' from being outputted and a '0' outputted from a fixed value generating circuit 47 is given to a variable delay element 49 on the occurrence of a dropout, and a fixed value discrimination circuit 50 discriminates a dropout timing by detecting a '0' outputted from the variable delay element 49 and a 2nd switch is switched to compensate the dropout. Thus, a 1H delay element 53 is used in common for Y/C separation, dropout compensation and interpolation delay time matching for jitter suppression by a 1H latch 66.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal reproducing device such as a video disc player which requires time axis correction and processing when a signal is lost.

[0002]

2. Description of the Related Art Video signal reproducing apparatuses such as video disk players and video tape recorders, which have become widespread in recent years, need to remove disk eccentricity and high frequency jitter components generated in a tape running system by a time axis correction circuit. Colors may not appear on the playback screen, or uneven colors may occur. Therefore, introduction of a time axis correction circuit with higher performance and lower cost is desired. Recently, a time axis correction circuit using a digital variable element (FIFO) has been introduced because a digital element such as a memory can be obtained at low cost.

Further, in the video signal reproducing apparatus, it is also necessary to compensate for dropout of the read signal (loss of signal). In general, dropout compensation is possible by replacing with a video signal one horizontal scanning time (so-called 1H) before the dropout.

Further, in order to improve the image quality, the separation of the luminance signal and the color signal (Y / C separation) is actively carried out, and one horizontal scanning time (1H, hereinafter, the horizontal scanning time is abbreviated as H). The luminance signal and the chrominance signal are separated by adjusting the video signal before and after the time difference of.

At present, it is desired to realize a video signal reproducing apparatus capable of performing these time axis correction, dropout compensation, and Y / C separation at low cost.

The above-mentioned conventional video signal reproducing apparatus will be described below with reference to the drawings. FIG. 5 is a block diagram showing the configuration of a conventional video signal reproducing apparatus. In FIG. 5, reference numeral 2 denotes a pickup which detects information from the video disc 1 on which a composite video signal is recorded and converts it into an electric signal, the output of which is input to the video signal demodulation circuit 3. Four
Is a dropout detection circuit, which detects a dropout from the output of the pickup 2 and outputs the output of the video signal demodulation circuit 3 itself and the output of the video signal demodulation circuit 3 via the delay line 5 and the dropout compensation signal generation circuit 6. The signal is controlled by the switch 7 to be switched. Reference numeral 8 denotes an A / D converter which inputs the output of the switch 7, A / D converts it for subsequent digital processing, and passes 1H through a digital variable delay element 9 (detailed later) capable of changing the signal delay amount. It is input to the digital 1H delay element 10 which delays by an amount. 1
Reference numeral 1 is a Y / C separation circuit, which inputs and outputs signals of the digital 1H delay element 10, respectively, and performs Y / C separation by calculating the sum and difference thereof, and outputs the luminance signal and the color. The signals are respectively the first D / A converter 26 and the second D / A converter 26.
It is input to the A converter 27 and output from the first terminal 28 and the second terminal 29. Reference numeral 12 denotes a horizontal sync separation circuit, which inputs the output of the video signal demodulation circuit 3 to separate the horizontal sync signal, and the first phase comparator 14 separates the output signal and the reference sync signal from the reference sync generation circuit 13. Phase comparison, first
Via the loop filter 15 and the motor drive circuit 16 of
The rotation of the spindle motor 17 that rotates the video disk 1 is controlled. Reference numeral 18 is a color burst separation circuit, which receives the output of the A / D converter 8 and compares the output with the reference signal output from the reference color burst generation circuit 19 by the second phase comparator 20. 2 loop filter 21, VC
Control is input to the digital variable delay element 9 via an O (voltage control variable frequency oscillation circuit) 22. The output of the second phase comparator 20 is input to the interpolating circuit 24 as the output as it is and the output through the 1H latch 23 once, and the output of the interpolating circuit 24 is digitally changed via the variable phase oscillator 25. It is inputted to the delay element 9 and the digital 1H delay element 10 as a control signal.

The operation of the conventional video signal reproducing apparatus configured as described above will be described below.

In FIG. 5, the pickup 2 detects a signal recorded on the video disk 1 and converts it into an electric signal. The output of the pickup 2 is demodulated into a composite video signal by the video signal demodulation circuit 3 and output to the switch 7, the delay line 5 and the horizontal sync separation circuit 12. The dropout detection circuit 4 detects the dropout when the level or frequency of the input output of the pickup 2 is in a region other than the recording signal, and controls the switch 7 to switch. The delay line 5 gives a delay of about 1H to the input signal from the video signal demodulation circuit 3. The dropout compensation signal generation circuit 6 takes out only the luminance signal component from the output of the delay line 5 and inputs it to the other input terminal of the switch 7. This is because in the composite video signal, since the phase of the color signal is inverted every 1H, only the luminance is compensated.

The horizontal sync separation circuit 12 extracts only the horizontal sync signal from the input composite video signal and inputs it to the first phase comparator 14. First phase comparator 14
Inputs the output of the reference sync generation circuit 13 to the other input and compares the phase with the horizontal sync signal of the reproduced composite video signal. The output of the first phase comparator 14 is frequency-compensated by the first loop filter 15,
It is input to the motor drive circuit 16, and the spindle motor 17 is rotated by the output of the motor drive circuit 16. That is, the rotation speed of the spindle motor 17 is controlled so that the signal generated by the reference synchronization generation circuit 13 and the output of the first horizontal synchronization separation circuit 12 are in phase. Now, if the oscillation frequency of the reference synchronization generation circuit 13 is set to the horizontal scanning frequency of the regular video signal, the spindle motor 17 is controlled so that the output of the video signal demodulation circuit 3 becomes the frequency of the regular video signal. It
However, the output of the video signal demodulation circuit 3 contains a high-frequency jitter component that cannot be sufficiently removed only by the control of the spindle motor 17 due to the eccentricity of the video disk 1, and cannot be reproduced as it is on the television receiver. . Therefore, in order to remove the jitter component, it is necessary to use the digital variable delay element 9 to compensate the image signal itself.

The video signal dropout-compensated by switching the switch 7 is converted into an 8-bit digital signal by the A / D converter 8, and the output of the A / D converter 8 is a digital variable delay element 9 described later. And to the color burst separation circuit 18. The color burst separation circuit 18 extracts only the color burst signal from the input digital video signal and inputs it to the second phase comparator 20. The color burst reference signal output from the reference color burst generation circuit 19 is input to the other input of the second phase comparator 20,
The phase is compared by the phase comparator 20 of. The color burst separation circuit 18, the reference color burst generation circuit 19, and the second phase comparator 20 form a jitter detecting means, the output of which is frequency-compensated through the second loop filter 21 and then the VCO 22. It is input as a control input and changes the oscillation frequency of the VCO 22. VCO22
Is used as a write clock for the digital variable delay element 9 described later, and the second loop filter 21, V
The CO 22 serves as a writing means.

The output of the second phase comparator, which is the writing means, is input to the interpolation circuit 24 together with the signal input to the 1H latch 23 and delayed by 1H, and linearly interpolated within the 1H period. This is a color burst separation circuit 18-VC
This is a feedforward jitter suppressing means for removing residual jitter that cannot be removed by the PLL constituted by O22. That is, the second phase comparator 20 outputs 1
Since the phase comparison data is output once every H, the frequency characteristic of this PLL system is limited by the sample hold characteristic. Therefore, the data between the samples are interpolated and varied by the interpolated data. Phase oscillator 25
Change the phase of. As a result, the time axis of the signal read from the digital variable delay element 9 and the digital 1H delay element 10 is changed to suppress the jitter.

In order to interpolate the residual error signal of the PLL system, the output of the second phase comparator 20 is fed to the 1H latch 23.
Then, it is delayed by 1H, and the interpolation circuit 24 linearly interpolates and changes from the output value of the 1H latch 23 to the second phase comparator value at 1H. The variable phase oscillator 25, to which the output of the interpolation circuit 24 is input, outputs a phase signal under the control of the interpolation output and is used as a read clock of the digital variable delay element 9. The output of the interpolation circuit allows the variable phase oscillator 25 to suppress the residual jitter without being limited by the sample hold characteristic. Due to this interpolation operation, the signal for controlling the variable phase oscillator 25 is delayed by 1H. Therefore, the digital 1H delay element 10 described later is required to match the time.

Next, the structure and operation of the digital variable delay element 9 will be described with reference to FIGS. 6 and 7. FIG. 6 is a block diagram showing the configuration of the digital variable delay element 9 of the conventional video signal reproducing apparatus. FIG. 7 shows the address of the digital variable delay element 9 and the interpolation circuit 24 of the conventional video signal reproducing apparatus.
It is a figure which shows the timing of an output, Comprising: The phase error detection point of the 2nd phase comparator 20, the output of the interpolation circuit 24,
The time relationship of the output of the Y / C separation circuit 11 is shown.

In FIG. 6, reference numeral 30 is a write clock input terminal to which the output of the VCO 22 in FIG. 5 is input. Three
Reference numeral 1 is a read clock input terminal to which the output of the variable phase oscillator 25 in FIG. 5 is input. 34 is a memory array,
It has 8-bit input / output and can control write and read addresses independently. 33 is a write address pointer for the write control. It counts the write clock, increments it sequentially, and reaches a certain set value. Then, it is reset, and 35 is a read address pointer for reading,
The read clock is counted, incremented sequentially, and reset when a certain set value is reached. A data input terminal 32 is connected to the output of the A / D converter 8 in FIG. 5, and the signal is stored in the memory cell designated by the write address pointer 33 in the memory array 34.
36 is a data output terminal, which is a digital 1H in FIG.
It is connected to the input of a delay element 10 (described later), and its signal is read by the read address pointer 3 in the memory array 34.
The information stored in the memory cell designated by 5 is output.

Now, the reset set values of both the write address pointer 33 and the read address pointer 35 are equally set to values corresponding to 1H of the input video signal, and further,
In the initial setting, the read address pointer 3 is set after 0.5H has elapsed since the write address pointer 33 started to operate.
When 5 is started, the operation of each address pointer becomes as shown in FIG. In FIG. 7, a broken line shows a change in the value of the read address pointer 35, and a solid line shows a change in the value of the write address pointer 33. Since the actual values of both address pointers are digital values, they show a gradual change, but here they are shown continuously in consideration of legibility. The write clock is a clock generated by the VCO 22, which changes in frequency according to the phase error of the output of the color burst separation circuit 18 with respect to the reference color burst phase detected by the second phase comparator 20. ing. On the other hand, the read clock is the variable phase oscillator 25.
Since it is a clock having a constant frequency that oscillates, the delay time can be controlled in the digital variable delay element 9, and the jitter included in the input data can be removed and output. In the initial setting, the read address pointer 35 starts to operate after 0.5H has elapsed since the write address pointer 33 started to operate.
Data writing is always performed before reading.

As described above, in the digital variable delay element 9, the input signal is delayed by a time corresponding to the difference between the oscillation frequency of the VCO 22 and the oscillation frequency of the variable phase oscillator 25, and is output. Now, the oscillation frequency of the variable phase oscillator 25 is set to an integral multiple of the horizontal scanning frequency of the regular video signal,
The central value of the oscillation frequency of the VCO 22 is also the variable phase oscillator 25.
If the oscillation frequencies of the color burst separating circuit 18 and the output of the color burst separating circuit 18 are in phase with each other, the VCO 22 is set to have a substantially equal oscillation frequency.
Is controlled. Since the control characteristics of the VCO 22 can be determined purely and electrically, the VCO 22 can be controlled up to a high frequency range, and therefore, the high frequency jitter that cannot be completely controlled by the spindle motor 17 can be suppressed.

With this video signal reproducing apparatus, it is possible to suppress a jitter of ± 0.5H. Digital variable delay element 9
The digital composite video signal in which the jitter is suppressed by is input to the digital 1H delay element 10 and delayed by 1H, and the 1H latch 23 for linear interpolation is used.
The signal delay due to is adjusted. The Y / C separation circuit 11 inputs signals before and after the digital 1H delay element 10 and performs Y / C separation of the digital composite video signal. That is, 1/2 of the sum of the signals before and after the digital 1H delay element 10 is the luminance signal, and 1/2 of the difference between the signals before and after the digital 1H delay element 10 is the color signal. The luminance signal is converted into an analog signal by the first D / A converter 26 and output from the first terminal 28, and the chrominance signal is converted into the second D signal.
The second terminal 2 which is converted into an analog signal by the A / A converter 27
It is output from 9.

[0018]

However, in the video signal reproducing apparatus having such a structure, the signal for reproducing the jitter is
In addition to the H latch, a 1H variable delay element that also combines the time for Y / C separation and the jitter suppression by the 1H latch, a 1H delay line is required for dropout compensation, which complicates the circuit and makes the video inexpensive. There is a problem that a signal reproducing device cannot be provided.

The present invention solves the above-mentioned conventional problems by eliminating one delay line of 1H and eliminating 1H latch and 1H.
Variable delay element, dropout compensation, jitter suppression,
It is an object of the present invention to provide an inexpensive video signal reproducing device capable of Y / C separation.

[0020]

In order to achieve this object, a video signal reproducing apparatus of the present invention is a pickup for detecting information on a record carrier on which a composite video signal is recorded and converting it into an electric signal, and an output of the pickup. A demodulator that more demodulates the composite video signal, a dropout detector that detects that the pickup output is missing, an A / D converter that converts the demodulator output to digital information, and one horizontal scanning time Once the jitter detecting means detects the time base fluctuation of the A / D converter output with respect to the normal composite video signal, the writing means outputting the writing control clock according to the output of the jitter detecting means, and the jitter detecting means. Hold circuit that holds the output until the next jitter detection time, and the total horizontal scanning time by first-interpolating the hold circuit output and the output of the jitter detection circuit An interpolation circuit for determining the time base fluctuation, a jitter suppression means comprising a variable phase oscillator for outputting a read control clock phase in accordance with the output of the interpolation circuit,
A limiter that inputs the output of the A / D converter, outputs an alternative neighboring value when the input value is a preset specific value, and outputs the input value as it is when the input value is other than the specific value, and specifies the limiter A fixed value generator that produces the same digital value as the value, and a limiter output when the dropout detector does not detect a dropout,
A first switch for outputting the output of the fixed value generator when the dropout detector is detecting a dropout, and a first switch output are designated according to a write control clock output by the writing means. Entered in the address
A variable delay element output from an address specified according to the read control clock output by the jitter suppressing means, a discriminator that outputs a replacement signal when the output of the variable delay element is a specific value of the limiter, and two inputs When the discriminator does not output the replacement signal, it outputs the input from the variable delay element as it is, and when the discriminator outputs the replacement signal, the other input The second switch that outputs the input, the delay element that inputs the output of the second switch and delays the output by approximately one horizontal scanning time of the video signal, and output, and the compensation signal at the time of dropout from the output of the delay element. A compensating signal generating circuit that generates and outputs the signal to the other input of the second switch and a signal that is both input and output of the delay element are input to separate the luminance signal and the chrominance signal Y / It has been and a separation circuit configuration.

[0021]

With this configuration, the video signal demodulated from the pickup output is normally A / D converted and input to the digital variable delay element after the limiter is applied. However, if dropout is detected in the output of the pickup, The switch 1 is switched, and the specific value output from the fixed value generation circuit is input to the digital variable delay element. Then, after the jitter is corrected by the digital variable delay element, it is determined whether or not the output of the digital variable delay element is a specific value due to the dropout, and the output of the digital 1H delay element that also serves as the time adjustment of Y / C separation and error interpolation Input to the dropout compensation signal generation circuit. As a result, the delay required for dropout compensation and the delay required for time adjustment of Y / C separation and error interpolation can all be performed by one 1H delay element, and a cheaper video signal reproducing device is provided. can do.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a video signal reproducing apparatus of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a video signal reproducing apparatus of the present invention. In FIG. 1, 4
1 is a video disk as a record carrier, 42 is a pickup, 43 is a video signal demodulation circuit as a demodulator,
The above is the same as that shown in the conventional example. Reference numeral 45 is an A / D converter that outputs the output of the video signal demodulation circuit 43 to an A / D converter.
Convert. A limiter 46 inputs the output of the A / D converter 45, outputs a substitute neighboring value when it is a specific value, and outputs it as it is in other cases. A dropout detection circuit 44 detects the presence or absence of dropout in the output of the pickup 42 and switches the input to either the output of the limiter 46 or the output of the fixed value generation circuit 47.
Of the digital variable delay element 49 by controlling the switch 48 of
To enter. Reference numeral 50 denotes a fixed value determination circuit, which detects whether or not the output of the digital variable delay element 49 has a specific value. A second switch 51 receives the output of the digital variable delay element 49 as one input, controls the switching by the fixed value determination circuit 50, and outputs the output to the digital 1H delay element 53. A dropout compensation signal generating circuit 52 receives the output of the digital 1H delay element 53, extracts the luminance signal thereof, and outputs the luminance signal to the other input of the second switch 51. Reference numeral 54 denotes a Y / C separation circuit for inputting the input / output of the digital 1H delay element 53, which includes a first D / A converter 69, a second D / A converter 70, a first terminal 71, and a second terminal 71. Both terminals 72 are similar to the conventional example. Further, the horizontal sync separation circuit 55, the reference sync generation circuit 56, the first phase comparator 57, the first loop filter 58, the motor drive circuit 59, and the spindle motor 60, which receive the output of the video signal demodulation circuit 43, have the same configuration. The operation is the same as the conventional example.

Further, a color burst separation circuit 61 which receives an input from the A / D converter 45, a reference color burst generation circuit 62 at the subsequent stage, a second phase comparator 63, a second loop filter 64 and a VCO (voltage control). A variable frequency oscillator circuit 65, a 1H latch 66, an interpolation circuit 67, and a variable phase oscillator 68 which finally sends a control signal to the digital variable delay element 49 and the digital 1H delay element 53 have the same configuration and operation as the conventional example. And forms a jitter detecting means, a writing means, and a jitter suppressing means, respectively.

The operation of the video signal reproducing apparatus configured as described above will be described below.

In FIG. 1, the pickup 42 converts the signal recorded on the video disc 41 into an electric signal.
The output of the pickup 42 is demodulated into a composite video signal by the video signal demodulation circuit 43 and input to the A / D converter 45. The dropout detection circuit 44 detects as a dropout when the level or frequency of the output of the pickup 42 is in a region other than the recording signal, and detects the first dropout.
Control the switch 48 of the. The A / D converter 45 converts the input composite video signal into an 8-bit digital signal. FIG. 3 is a diagram showing conversion characteristics of the A / D converter of the embodiment of the video signal reproducing apparatus of the present invention.
As shown in FIG. 3, the sync chip level is set to "0", and the maximum 256 "255" digital values are output. The output of the A / D converter 45 is the limiter 4
6 is input. In the limiter 46, when the input value is "0", the output is "1", and the input value is "1" to "255".
Values up to are output as is. That is, the value of "0" cannot appear in the output of the limiter 46. The fixed value generation circuit 47 always generates the specific value "0". The output of the dropout detection circuit 44 is input to the first switch 48, and when a dropout occurs, the fixed value generation circuit 47
The output of is limited by the limiter 4 except when a dropout occurs.
6 outputs are selected respectively and digital variable delay element 4
9 is input. That is, the input value of the digital variable delay element 49 is "0" only during dropout, and takes a value of "1" to "255" at times other than dropout.

At the same time, the composite video signal output from the video signal demodulation circuit 43 is input to the horizontal sync separation circuit 55. The horizontal sync separation circuit 55 extracts only the horizontal sync signal from the input video signal and outputs the first phase comparator 5
7, and the rotation speed of the spindle motor 60 is controlled as in the conventional example.

The output of the A / D converter 45 is input to the color burst separation circuit 61 of the jitter detecting means as in the conventional example, and the output of the VCO 65 of the writing means is the write clock of the digital variable delay element 49. Used as.

The output of the second phase comparator 63 of the jitter detecting means is also 1H of the jitter suppressing means as in the conventional example.
It is input to the latch 66. The output of the variable phase oscillator 68 is used as a read clock for the digital variable delay element 49 and the digital 1H delay element 53, and performs the same jitter suppression as the conventional example.

The output of the digital variable delay element 49 is input to the fixed value discriminating circuit 50 and the second switch 51.
As described above, the input of the digital variable delay element 49 is
Since it is "0" at the time of dropout and "1" to "255" at other than the dropout, it can be determined that the output of the digital variable delay element 49 is a dropout when the output is "0". Fixed value determination circuit 50
Determines that the input is “0”, it is a dropout, and controls the second switch 51. The digital 1H delay element 53 gives a delay of about 1H to the input signal. The dropout compensation signal generation circuit 52 takes out only the luminance signal component from the output of the digital 1H delay element 53 and inputs it to the other input of the second switch 51. This is because in the composite video signal, since the phase of the chroma signal is inverted every 1H, only the luminance is compensated.

The video signal subjected to dropout compensation by the second switch 51 is input to the digital 1H delay element 53. The digital composite video signal whose jitter is suppressed by the digital variable delay element 49 in this manner is subjected to dropout compensation by the digital 1H delay element 53. The Y / C separation circuit 54 performs Y / C separation of the digital composite video signal from the signals before and after the digital 1H delay element 53. That is, 1/2 of the sum of the signals before and after the digital 1H delay element 53 is the luminance signal, and 1 of the difference between the signals before and after the digital 1H delay element 53.
/ 2 is a color signal. The luminance signal is converted into an analog signal by the first D / A converter 69 and output from the first terminal 71, and the chrominance signal is converted into an analog signal by the second D / A converter 70 and the second terminal. It is output from 72.

Next, the configuration of the digital variable delay element 49,
The operation will be described. FIG. 2 is a block diagram showing the configuration of the digital variable delay element of the video signal reproducing apparatus according to the embodiment of the present invention. FIG. 4 is a diagram showing the address of the digital variable element and the timing of the output of the interpolation circuit of the video signal reproducing apparatus of the embodiment of the present invention.

In FIG. 2, 73 is a write clock input terminal to which the output of the VCO 65 in FIG. 1 is input. 7
Reference numeral 4 is a read clock input terminal to which the output of the variable phase oscillator 68 in FIG. 1 is input. 77 is a memory array,
It has 8-bit input / output and can control write / read addresses independently. Reference numeral 76 is a write address pointer for writing, counting the write clock, incrementing sequentially, and resetting when a certain set value is reached.
On the contrary, 8 is a read address pointer for reading, which counts the read clock, increments sequentially, and is reset when a certain set value is reached. Reference numeral 75 is a data input terminal to which the output of the first switch 48 in FIG. 1 is connected, and its signal is stored in the memory cell designated by the write address pointer 76 in the memory array 77. Reference numeral 79 denotes a data output terminal, which is connected to the inputs of the fixed value determination circuit 50 and the second switch 51 in FIG. 1, and the signal thereof is a memory cell designated by the read address pointer 78 in the memory array 77. The information stored in is output.

Now, the reset set values of both the write address pointer 76 and the read address pointer 78 are made equal to a value corresponding to 1H of the input video signal, and further,
In the initial setting, the read address pointer 7 is set after 0.5H has elapsed since the write address pointer 76 started to operate.
When 8 starts to operate, the operation of each address pointer becomes as shown in FIG. In FIG. 4, a broken line shows a change in the value of the read address pointer 78, and a solid line shows a change in the value of the write address pointer 76. In this case as well, similar to FIG. 7, it is continuously shown in consideration of visibility. The write clock is a clock generated by the VCO 65, which changes in frequency according to the phase error of the output of the color burst separation circuit 61 with respect to the reference color burst phase detected by the second phase comparator 63. ing. On the other hand, the read clock is a clock having a constant frequency oscillated by the variable phase oscillator 68, so that the delay time can be controlled in the digital variable delay element 49, and the jitter included in the input data can be removed and output. . Write address pointer 7 in initialization
The reason why the read address pointer 78 starts to operate after 0.5H has elapsed since the start of operation of 6 is to ensure that data writing is performed before reading.

FIG. 4 shows the phase error detection points of the second phase comparator 63, the output of the interpolation circuit 67, and the Y / C separation circuit 5.
4 shows the time relationship of the outputs of FIG. Therefore, this video signal reproducing apparatus can suppress the jitter of up to ± 0.5H.

A limiter 46 outputs the output of the A / D converter 45.
By limiting the output from "1" to "255", the sync chip level of the output horizontal synchronizing signal is increased by "1", but this has no effect on the output to the television receiver.

As described above, according to one embodiment of the present invention, A
A limiter is applied to the / D-converted video signal, and when there is a dropout in the pickup output, the first switch writes a specific value out of the limiter output by the fixed value generation circuit to the digital variable delay element. ,
The fixed value determination circuit determines whether or not the output read out after the jitter correction is a specific value, the second switch is switched, and the output of the dropout compensation signal generation circuit is input to the digital 1H delay element. Dropout compensation, jitter suppression, Y / C with delay line and 1H variable delay element
It is possible to provide an inexpensive video signal reproducing device that can be separated.

In the embodiment of the present invention, the jitter suppression after the error interpolation is performed by changing the phase of the read clock, but as another method, for example, the phase of the clock is fixed and Y is set. The same effect can be obtained by digitally processing the / C separated output signal and changing the output delay.

Further, the dropout compensation signal generating circuit generates only the luminance signal, but this is because the signal 1H before is different in the chroma phase by 180 °, and only the chroma frequency band is generated by the digital signal processing. If the operation for rotating the phase by 180 ° is performed by the dropout compensation signal generation circuit, even the color signal can be compensated at the time of dropout.

Further, in the embodiment of the present invention, the specific value is set to "0", but if "255" is set to the specific value and the limiter is set from "0" to "254", the same effect can be obtained. To be

Further, although the dropout detection circuit 44 inputs the output of the pickup 42, it goes without saying that the same effect can be obtained even when the output of the video signal demodulation circuit 43 is input.

[0042]

As described above, according to the present invention, a pickup for detecting information on a record carrier on which a composite video signal is recorded and converting it into an electric signal, a demodulator for demodulating the composite video signal from the output of the pickup, and a pickup. Dropout detector that detects that there is a loss in the output of A, the A / D converter that converts the output of the demodulator into digital information, and the A / D conversion for the regular composite video signal once in one horizontal scanning time Detecting means for detecting the fluctuation of the output of the instrument on the time axis, a writing means for outputting a writing control clock according to the output of the jitter detecting means, and a hold circuit for holding the output of the jitter detecting means until the next jitter detection time. And an interpolation circuit for obtaining the time-axis variation of the total horizontal scanning time by linearly interpolating the output of the hold circuit and the output of the jitter detection circuit, and the output of the interpolation circuit. A jitter suppression means comprising a variable phase oscillator for outputting a read control clock phase corresponding to,
A limiter that inputs the output of the A / D converter, outputs an alternative neighboring value when the input value is a preset specific value, and outputs the input value as it is when the input value is other than the specific value, and specifies the limiter A fixed value generator that produces the same digital value as the value, and a limiter output when the dropout detector does not detect a dropout,
A first switch for outputting the output of the fixed value generator when the dropout detector is detecting a dropout, and a first switch output are designated according to a write control clock output by the writing means. Entered in the address
A variable delay element output from an address specified according to the read control clock output by the jitter suppressing means, a discriminator that outputs a replacement signal when the output of the variable delay element is a specific value of the limiter, and two inputs When the discriminator does not output the replacement signal, it outputs the input from the variable delay element as it is, and when the discriminator outputs the replacement signal, the other input The second switch that outputs the input, the delay element that inputs the output of the second switch and delays the output by approximately one horizontal scanning time of the video signal, and output, and the compensation signal at the time of dropout from the output of the delay element. A compensating signal generating circuit that generates and outputs the signal to the other input of the second switch and a signal that is both input and output of the delay element are input to separate the luminance signal and the chrominance signal Y / By including the separation circuit, the jitter is suppressed by the variable delay element, and then the dropout compensation and the Y / C separation are performed. Therefore, one 1H delay line and 1H variable delay element It is possible to provide an inexpensive and excellent video signal reproducing device capable of compensation, jitter suppression, and Y / C separation.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a video signal reproducing apparatus of the present invention.

FIG. 2 is a block diagram showing a configuration of a digital variable delay element of the same.

FIG. 3 is a diagram showing conversion characteristics of the A / D converter.

FIG. 4 is a diagram showing a timing of an address of a digital variable element and an output of an interpolation circuit.

FIG. 5 is a block diagram showing a configuration of a conventional video signal reproducing device.

FIG. 6 is a block diagram showing a configuration of a digital variable delay element of the same.

FIG. 7 is a diagram showing the address of the digital variable element and the timing of the output of the interpolation circuit.

[Explanation of symbols]

 41 Video Disc 42 Pickup 43 Video Signal Demodulation Circuit 44 Dropout Detection Circuit 45 A / D Converter 46 Limiter 47 Fixed Value Generation Circuit 48 First Switch 49 Digital Variable Delay Element 50 Fixed Value Discrimination Circuit 51 Second Switch 52 Drop Out compensation signal generation circuit 53 Digital 1H delay element 54 Y / C separation circuit 55 Horizontal synchronization separation circuit 56 Reference synchronization generation circuit 57 First phase comparator 58 First loop filter 59 Motor drive circuit 60 Spindle motor 61 Color burst separation Circuit 62 Reference color burst generation circuit 63 Second phase comparator 64 Second loop filter 65 VCO (voltage control variable frequency oscillation circuit) 66 1H latch 67 Interpolation circuit 68 Variable phase oscillator 69 First D / A converter 70 Second D / Converter 71 first terminal 72 second terminal

Claims (1)

[Claims] 1. A pickup for detecting information on a record carrier on which a composite video signal is recorded and converting it into an electric signal, a demodulator for demodulating the composite video signal from the output of the pickup, and a missing output of the pickup. A dropout detector for detecting the above, an A / D converter for converting the output of the demodulator into digital information,
Jitter detecting means for detecting the time base fluctuation of the A / D converter output with respect to the normal composite video signal once every one horizontal scanning time, and writing for outputting a write control clock according to the output of the jitter detecting means. Means, a hold circuit for holding the output of the jitter detection means until the next jitter detection time, and an interpolation for linearly interpolating the output of the hold circuit and the output of the jitter detection circuit to obtain a time-axis variation of the entire horizontal scanning time. Circuit and a variable phase oscillator that outputs a read control clock having a phase corresponding to the output of the interpolation circuit, and the output of the A / D converter, and the input value is a preset specific value. Outputs an alternative neighborhood value when
When the input value is not a specific value, a limiter that outputs the input value as it is, a fixed value generator that generates the same digital value as the specific value of the limiter, and when the dropout detector does not detect dropout A first switch that outputs the output of the limiter and outputs the output of the fixed value generator when the dropout detector detects a dropout, and an output of the first switch are The variable delay element which is input to the address designated by the write control clock output by the input means and is output from the address designated by the read control clock output by the jitter suppressing means, and the output of the variable delay element. A discriminator which outputs a replacement signal when it is discriminated that it is a specific value of the limiter, and the variable delay element as one of two inputs. When the discriminator does not output the replacement signal, it outputs the input from the variable delay element as it is, and when the discriminator outputs the replacement signal, it outputs the other input. A second switch, a delay element that inputs the output of the second switch, delays one horizontal scanning time of the video signal and outputs the delayed signal, and generates a compensation signal at the time of dropout from the output of the delay element. And a Y / C separation circuit for inputting both the input signal and the output signal of the delay element to separate into a luminance signal and a chrominance signal, and a compensating signal generating circuit for outputting to the other input of the second switch. A video signal reproducing device characterized in that