JP2000244943A - Device for recording and reproducing image information signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image information signal recording/reproducing device that can deal with both of analog and digital broadcasts and capable of digitally recording an analog broadcast signal by generating a chrominance subcarrier synchronized with the phase of a burst signal in an analog video signal, driving the chrominance subcarrier by a multiplied clock signal and demodulating the analog video signal to a base band signal. SOLUTION: A multiplying circuit 35 in a digital VTR block 31 multiplies a chrominance subcarrier (fsc) inputted from an analog VTR block 30 by N and an output clock CK1 from the circuit 34 becomes a system clock for a block 37. An output CK2 from a clock generation circuit 36 is synchronized with the phase of the clock CK1 and acts as a system clock for a block 38. Both of YC separated luminance signal and chrominance signal are demodulated to a base band signal by an NTSC decoder 19 based on the system clock CK1 and rate conversion or the like into the rate of the system clock CK2 for an MPEG2 encoder 21 is executed by an I/F circuit 28.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information signal recording / reproducing apparatus for recording / reproducing an image information signal on a recording medium, and more particularly to an image information signal recording / reproducing apparatus having an analog signal recording / reproducing section and a digital signal recording / reproducing section. The present invention relates to a signal processing technique in a device.

[0002]

2. Description of the Related Art Conventionally, most of home image information signal recording / reproducing apparatuses use an analog VTR for recording / reproducing an analog video signal on a 1/2 inch wide magnetic tape.
On the other hand, television broadcasting has been put into practical use from analog system to digital system mainly in North America, and digital broadcasting has been started in Japan by DIRECTV TV and Sky Perfect TV. Digital broadcasting for receiving this broadcasting has been started. A tuner has been commercialized.

In order to cope with such a situation, a digital VTR capable of directly recording a digital broadcast signal has been recently developed. This is a new standard VTR called digital VHS in which a digital recording mode is mounted on a conventional VHS standard VTR. It is characterized in that the digital broadcast is recorded in a bit stream while retaining the function of an analog VTR, and those having a built-in digital tuner have been commercialized. The present inventors have already filed a patent application (Japanese Unexamined Patent Application Publication No.
No. 194988) proposed a VTR in which a digital VTR function and an analog VTR function were combined, and showed techniques such as digital / analog discrimination and auto tracking means.

On the other hand, the world standard MPEG (Moving Pictu)
(Re Experts Group) A technique for digitally encoding a video signal by a compression / expansion technique has been put to practical use, and the above-mentioned digital broadcasting conforms to this. Initially, MPEG1 was the mainstream, but recently, MPEG2 with a high transmission rate and high image quality has been put to practical use. As an applied product, there is a DVD (Digital Video Disc) player.
The digital signal reproduced from the G2 recorded disc is decoded to obtain a reproduced image. The encoder has a larger circuit scale than the MPEG2 decoder, and its practical application to consumer equipment has been slightly delayed. However, in recent years, miniaturization techniques in semiconductor devices have been rapidly developed, LSIs capable of processing MPEG2 encoders in real time have been developed, and applications to consumer appliances are in a state of being developed.

[0005] As a signal processing technique of a recent home VTR, a three-dimensional YC separation circuit using a frame memory is used for separating a composite video signal into a luminance signal and a chrominance signal.

[0006]

Although digitalization is rapidly progressing due to the above-mentioned conventional technology, it is difficult to convert conventional analog devices to digital broadcast-compatible devices at a stretch. Equipment that can coexist and support both is required.

[0007] The digital VTR has an MP
A digital broadcast dedicated VTR that receives a digital broadcast signal transmitted after being EG compressed by a tuner, records the bit stream signal directly on a magnetic tape as it is, and converts it into a composite video signal with an MPEG decoder at the time of reproduction to obtain a reproduced image. It is. That is, it does not have a function of digitally recording an input composite video signal by MPEG compression.

[0008] As described above, in a VTR in which an analog VTR function and a digital VTR function are combined,
A product that incorporates an MPEG encoder to digitally record a composite video signal has not yet been announced. Further, when this is realized, the following problems are expected.

First, regarding the copy guard function for protecting the copyright of the soft video, an analog VTR /
The question is how to deal with the digital VTR.

Second, when a non-standard signal is input, such as a signal having a jitter such as a reproduced image of a VTR or a signal such as a burst image which is discontinuous between fields such as a still image of a laser disk. This causes problems such as malfunction of the MPEG encoder, and the effect on the MPEG encoder side due to the loss of vertical synchronization of the input screen caused by switching the input screen.

Third, an MPEG encoder and a three-dimensional YC
There is a problem when combining and configuring the separation circuits. The three-dimensional YC separation circuit separates color signals by using the correlation between one frame using a memory for one frame. In the conventional technology, processing with a clock synchronized with the color subcarrier fsc is performed. Was common. In contrast, MP
The EG encoder has a 13.5 MHz 4: 2: 2 signal format in accordance with the color difference signal standard (CCIR656). To connect the YC separation circuit and the MPEG encoder to transmit digital signals, it is necessary to optimize these clock rates.

An object of the present invention is to provide an easy-to-use image information signal recording / reproducing apparatus which supports both analog broadcasting and digital broadcasting and has a function of digitally recording a conventional analog broadcasting signal. .

[0013]

In order to achieve the above object, an image information signal recording / reproducing apparatus according to the present invention has an analog signal recording / reproducing section and a digital signal recording / reproducing section. The digital signal recording / reproducing unit includes a color subcarrier generation unit that generates a color subcarrier that is phase-synchronized with a burst signal of an input analog video signal.
Clock signal generating means for generating a clock signal multiplied by the color subcarrier frequency, and decoding means operating by the clock signal to demodulate the analog video signal into a baseband signal. Thus, the digital signal recording / reproducing unit can demodulate the analog video signal into a baseband signal without interference such as a beat due to the clock signal.

In the present invention, a multiplied clock generating means for synchronizing with and multiplying the color subcarrier generated by the analog signal recording / reproducing unit, and a fixed oscillation clock for generating an N-fold clock asynchronous with the color subcarrier frequency Generating means, and non-standard discriminating means for detecting a time axis fluctuation of an input analog video signal and discriminating whether the input signal is a standard signal or a non-standard signal, and in the case where the input signal is a standard signal, the multiplied clock. The decoding means is operated by a clock signal generated by the generating means, or when the input signal is a non-standard signal, by a clock signal generated by the fixed oscillation clock generating means. Thereby, the VT having the jitter component
For a non-standard signal such as a reproduction output signal of R, a clock signal generated by the fixed oscillation clock generating means of independent oscillation which substantially matches the clock signal generated by the multiplied clock generating means is used. Good demodulation for all external input signals.

Further, the present invention has a first clock generating means for operating the decoding means, and a second clock generating means for operating the MPEG encoding means and the digital recording means, wherein the decoding means and the MPEG encoding means are provided. An interface means for converting between a clock rate and a signal format is provided between them. As a result, all processes from demodulation of the input signal to a baseband signal, digital compression processing after MPEG compression, and recording on a recording medium can be directly connected with the digital signal.

Further, in the present invention, a YC separation circuit for separating an analog video signal into a luminance signal and a chrominance signal, a time base collector for correcting time axis fluctuation, and a YC separation circuit and a time base collector are commonly used. A field memory or a frame memory, and the YC separation circuit can be switched between a two-dimensional YC separation circuit and a three-dimensional YC separation circuit. When the input analog video signal is a standard signal, The separation circuit switches to a three-dimensional YC separation circuit, and turns off the time base collector. If the input analog video signal is a non-standard signal, the YC separation circuit switches to a two-dimensional YC separation circuit.
In addition, the time base collector is turned on.
As a result, digital recording with high image quality can be performed for both the standard signal and the non-standard signal.

In the present invention, the analog signal recording / reproducing unit and the digital signal recording / reproducing unit have a common YC separation circuit. Further, the digital signal recording / reproducing unit includes a time base collector for correcting a time axis fluctuation of an output of the YC separation circuit,
An MPEG encoding means for MPEG-compressing the correction signal and a digital recording means for recording the MPEG-compressed signal on a recording medium are provided. This provides a digital recording function with less malfunction for non-standard signals.

Further, in the present invention, the analog signal recording / reproducing unit and the digital signal recording / reproducing unit have a common or independent automatic gain control (AGC) circuit for controlling the input analog video signal amplitude to be constant. The automatic gain control circuit responds to a copy guard signal included in the input analog video signal during the recording operation by the analog signal recording / reproducing unit, and receives the analog video signal during the recording operation by the digital signal recording / reproducing unit. Is set so as not to respond to the copy guard signal included in. This makes it possible to provide an image information signal recording / reproducing apparatus which addresses the copyright problem.

Further, according to the present invention, when the Y color difference signal is directly input, the clock rate conversion of the interface means is made through, and the processing from signal fetching to MPEG compression is processed by the same clock. A digital recording function of image quality can be provided.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 1 shows a signal processing circuit of an analog / digital composite VTR. Reference numeral 30 denotes an analog VTR block and reference numeral 31 denotes a digital VTR block. First, the analog VTR block will be described. The composite video signal input from the input terminal 1 is controlled at a constant level by an automatic gain control (AGC) circuit 2 and then separated by a YC separation circuit 3 into a luminance signal and a chrominance signal. After being added by the adder 6 through the recording color signal processing circuit 5 and the adder 4, the signal is amplified by the recording amplifier 7 and supplied to the magnetic head 8. At the time of reproduction, a signal from the magnetic head 8 is sufficiently amplified by a reproduction head preamplifier 9 and then separated into a luminance signal and a chrominance signal by a separation filter 10. After being processed by the circuit 12, the switch circuit 13,
The luminance signal is output to an output terminal 16, the chrominance signal is output to an output terminal 18, and the composite video signal added by the addition circuit 15 is output to an output terminal 17 via 14. Here, reference numeral 33 denotes a chrominance subcarrier (fsc) generating circuit which is controlled via a switch 14 by a control signal from the recording chrominance signal processing circuit 5 so as to be phase-synchronized with a burst signal of a composite video signal input from the outside. Things. At the time of reproduction, the switch 14 is turned off, and the fsc generation circuit 33 performs fixed oscillation.

Next, the digital VTR block will be described. A multiplying circuit 35 multiplies the chrominance subcarrier fsc input from the analog VTR block by N. The output clock CK1 becomes a system clock of the block 37. Specifically, CK1 is set to 8 fsc, and it is desirable to use 4 fsc obtained by dividing the frequency by 1/2 as necessary. 1
The 3.5 MHz generator 36 has a PLL (Phase Locked Loop) structure to which the output of the multiplying circuit 35 is input, and its output CK2 is phase-synchronized with the clock CK1 and functions as a system clock of the block 38. The YC-separated luminance signal and chrominance signal are output from the system clock CK1.
Is demodulated into a baseband signal by the NTSC decoder 19, and the MPEG2
The rate conversion to the rate of the system clock CK2 on the encoder 21 side and the conversion of the signal format are performed. MPE
The input of the G2 encoder 21 is generally a 4: 2: 2 Y color difference signal (Y / RY / Y) conforming to the CCIR656 standard.
BY). This standard requires a clock rate of 13.5 MHz to be transmitted. M
The output of the PEG2 encoder 21 is the DVHS recording circuit 2
2 (here, a digital recording circuit conforming to the DVHS standard, hereinafter referred to as a DVHS recording circuit), is sent to a magnetic head 24 via a recording amplifier 23, and is recorded on a magnetic tape. At the time of reproduction, the signal from the magnetic tape is sufficiently amplified by the reproduction preamplifier 25, processed by the DVHS reproduction circuit 26, and restored to the baseband signal by the MPEG2 decoder 27. Further, the clock rate is converted from CK2 to CK1 by the interface circuit 28, is converted into an NTSC video signal by the NTSC encoder 29, and the luminance signal is output to the output terminal 16 and the chrominance signal is output to the output terminal 18 via the switch circuits 13 and 14. The composite video signal added by the circuit 15 is output to an output terminal 17.

As described above, in order to prevent clock interference, the NTSC decoder 19 controls the color subcarrier fs
c, and is processed by the clock CK1 synchronized with the clock CK2, and the rate of the clock CK2 (13.5M
Hz), and an interface circuit 28 is provided for these rate conversions. MPEG2
The conversion from the decoder 27 to the NTSC encoder 29 is also performed by the interface circuit 28.

Next, the AGC circuit 2 will be described. In a conventional analog VTR, copy guard (copy protection) is implemented from the standpoint of copyright protection. This is generally for the AGC operation proposed by Macrovision. Several pseudo sync pulses (hereinafter referred to as macrovision signals) are inserted in a 1H (H is a horizontal scanning period) period at a position of a vertical retrace period, and the compression ratio of the AGC circuit is increased in response to the pulses. Enhance
This causes an abnormality in the recording signal. Analog VTR unit 3
At 0, such copy guard support is continued as before. In contrast, digital VTRs use CGMS
A (Copy Guard Management System) signal is used to control whether recording is possible or not according to the type of copying, such as “impossible”, “possible”, and “copy once”. Therefore, even if a macrovision signal is inserted, recording is possible on a magnetic tape if "copy once" is possible by a CGMS signal. Therefore, when operating as a digital VTR, the AGC circuit 2 is set so as not to respond to the macrovision signal in order to make it easier to read the CGMS signal at the subsequent stage of the AGC circuit. That is, when the analog VTR and the digital VTR have independent AGC circuits, the AGC circuit on the analog VTR side responds to the macrovision signal, and the AGC circuit on the digital VTR side does not respond to the macrovision signal. On the other hand, as shown in FIG. 1, when the AGC circuit 2 is shared by the analog VTR 30 and the digital VTR unit 31, a control signal (Digital) is inputted from the terminal 70 and switched, and the signal is switched to "H".
If it is, control is performed to operate as a digital VTR in response to the macrovision signal, and if 'L', control is performed to operate as an analog VTR in response to the macrovision signal.

FIG. 2 shows an embodiment in which the configuration of the clock in FIG. 1 is slightly changed. The operation up to the interface circuit 28 is the same as before, and converts the rate from the clock CK1 to the clock CK2. Thereafter, the MPEG2 encoder 21 and the DVHS recording circuit 22 are configured to perform processing using a clock CK3 generated by an asynchronous fixed oscillator 51, which has substantially the same frequency as CK2. Since the clock CK2 is a clock synchronized with the color subcarrier, the clock CK2 is a clock whose phase has fluctuated to a considerable extent according to the state of the input color signal. Therefore, the MPEG2 encoder / decoder, D
By operating the VHS recording circuit / reproducing circuit, a more stable operation can be obtained irrespective of the input signal state.

FIG. 3 shows a case where the analog VTR section 30 and the digital VTR section 33 have the YC separation circuit in FIG. 1 independently. Figure 1 shows the clock configuration, etc.
Is the same as That is, Y is set on the digital VTR unit 33 side.
Although the C separation circuit 32 is added, the YC separation circuit 32 in this case is characterized by being constituted by a three-dimensional YC separation circuit. The three-dimensional YC separation circuit separates high-quality images by using the correlation between one frame of a color signal using a memory for one frame, and usually operates with a clock synchronized with the color subcarrier fsc. I do. On the other hand, as described above, the MPEG encoder uses the Y color difference signal standard (CCI).
R656) operates at a clock rate of 13.5 MHz, so that the interface circuit 28 converts the clock rate in order to directly connect these signals.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 shows a signal processing circuit of an analog / digital composite VTR. The difference from the embodiment of FIG. 1 is the portion of the digital VTR section 33. The block 43 is a YC separation circuit 32, an NTSC decoder 19, a time base collector 40, a switch circuit 42, an interface circuit 28, an NTSC encoder 29, a non-standard discrimination. Circuit 4
1 The YC separation here is a high quality MP
In accordance with EG2 recording, high-quality YC separation is performed as three-dimensional YC separation using the frame memory 59. If the input signal is a standard signal, it operates as a three-dimensional YC separation, but if it is a non-standard signal, a malfunction occurs, so that it is switched to the two-dimensional YC separation using a line memory.

The reason why three-dimensional YC separation cannot be performed when a non-standard signal is input will be described with reference to FIG. In the case where there is a fluctuation in the time axis due to jitter like a reproduced signal from a VTR, a signal (×) of one frame after a frame shown by a dotted line 75 with respect to a signal of the current field (black circle) shown by a solid line 74.
Mark) indicates that the sampling phase is shifted due to jitter.
Accurate YC separation cannot be performed by the calculation before and after one frame. On the other hand, the signal before and after 1H (H is the horizontal scanning period) is not particularly affected by the jitter, and the YC separation can be performed with a certain degree of accuracy. Thus, it is preferable to switch to the two-dimensional YC separation for the non-standard signal.

Also, the non-standard signal input can be
In the case of compression, fluctuations between frames cause problems in the compression operation itself, resulting in image quality deterioration. Therefore, the YC-separated signal is demodulated into a baseband signal by the NTSC decoder 19 and then input to the time base collector 40. The time base collector 40 has a configuration using a frame memory, and detects and corrects the fluctuation of the time axis in units of frames. As described above, when a non-standard signal is input, the YC separation circuit performs two-dimensional YC separation and does not require a frame memory. By using this as a time base collector, the memory can be used effectively. As is well known, MPEG compression is performed on the basis of a plurality of field information. For a non-standard signal having a jitter component such as a VTR output, information fluctuates on a time axis between fields, so that MPEG performance is improved. It is difficult to compress, and it is necessary to once convert it to a standard signal through a time base collector. As shown in FIG. 6, since the sampling phase of the signal (marked by “x”) after one frame indicated by the dotted line 75 is shifted from the signal (black circle) of the current field due to jitter, the calculation accuracy is also high in the MPEG compression operation. This is because it falls and high-quality compression cannot be performed. As a time base collector, the performance using a line memory can be improved. However, by performing correction in units of fields or frames, M
More stable image quality can be secured for PEG compression. Also, if the input suddenly switches,
In the time base collector in the line processing, page turning and the like occur, and when MPEG compression is performed, several fields are affected, which causes a large deterioration in image quality. Therefore, by using the time base collector of the frame processing, the page is not turned even if the screen is suddenly switched, and the MPE is used.
Even when G compression is performed, the image quality is not disturbed. Since there is no need to apply a time base collector to the standard signal,
The non-standard signal discriminating circuit 4 is turned off by the switch 42.
The output of 1 controls the switch 42.

Regarding the system clock, the chrominance subcarrier fsc is stable when the standard signal is input.
In addition to operating the block 43, the clock CK2 for operating the subsequent block 38 is also generated based on the multiplied clock. When a non-standard signal is input, the switch 52 is connected to the black circle side, the output clock of the fixed oscillator 53 is used as CK1, and CK2 is
Generating based on the clock of No. 3 enables a stable operation which is not affected by the jitter of the non-standard signal.

Next, a specific example of switching between the YC separation circuit and the time base collector based on the result of the non-standard signal determination will be described with reference to FIG. FIG. 5 is a system diagram from the YC separation circuit to the time base collector. The three-dimensional YC separation circuit 56 and the time base collector 40
9 is also used, and is switched by the switch 60. The two-dimensional YC separation circuit 57 realizes YC separation using the line memory 58. The luminance signal and the chrominance signal from the three-dimensional YC separation circuit 56 and the two-dimensional YC separation circuit 57 are switched by switch circuits 61 and 62, respectively, and the time base collector 40 is switched on / off by the switch circuit 42. Configuration. If the non-standard discriminating circuit 41 determines that the signal is non-standard, the switch circuits 42, 60,
61 and 62 are connected to the black circle side, and the YC separation circuit is operated to perform two-dimensional processing and turn on the time base collector. If it is determined that the signal is a standard signal, the four switch circuits are connected to the white circle side, the YC separation circuit is operated to perform three-dimensional processing, and the time base collector is turned off. Here, the non-standard discriminating circuit 41 determines whether or not the relationship between the color subcarrier frequency (fsc), the horizontal synchronization frequency (fH), and the vertical synchronization frequency (fV) of the input signal satisfies a predetermined relationship. Can be determined.

Next, a third embodiment will be described with reference to FIG. FIG. 7 shows a signal processing circuit of an analog / digital composite VTR. 4 is different from the second embodiment in FIG. 4 in that the YC separation circuit of the analog VTR section 30 is deleted and the high-performance YC separation circuit 32 provided in the digital VTR section 33 is shared. The analog VTR unit 30 converts the luminance signal and the chrominance signal from the YC separation circuit 32 into DA converters 77 and 78.
After returning to the analog signal in the above, the recording luminance signal processing circuit 4,
It is input to the recording color signal processing circuit 5. Where analog VT
As shown in FIG. 7, a YC separation signal before passing through the time base collector 40 is returned to the R unit 30,
The color subcarrier from the fsc generation circuit 33 was stabilized.

This will be described with reference to FIG. A
The video signal output from the GC circuit is output to the YC separation circuit 3
After being separated by 2, the signals are sent to the color signal processing circuit 80 and the luminance signal processing circuit 81 via the DA converters 77 and 78. With respect to the color signal, the output of the fsc generation circuit 33 and the output of the color signal processing circuit 80 are compared by the phase comparator 82, and the error signal is returned to the fsc generation circuit via the LPF 83. YC
The color subcarrier phase-locked to the separated color signal is multiplied by the multiplier 35 and used as a clock for the YC separation circuit 32, so that high-performance YC separation can be realized. On the other hand, when a signal that has passed through the time base collector 40 is sent, this stability is impaired. The time base collector 40 includes a memory control and arithmetic circuit 84 and a timing generator 85. After performing time axis correction using a memory, the time base collector 40 replaces a burst signal with a synchronization signal. Therefore, even if this output is returned to the phase comparator 82, a color subcarrier phase-locked to the input color signal cannot be obtained, and the separation performance of the YC separation circuit 32 will be deteriorated. As described above, when a non-standard signal is input, the color signal returned to the phase comparator 82 is not subjected to the time base collector,
The stability of the loop indicated by the thick arrow is ensured, and the YC separation performance is secured. On the other hand, the signal sent to the MPEG encoder is passed through a time base collector to be a standard signal with no fluctuation in the time axis, thereby achieving a digital VTR. Performance can be improved.

Next, a fourth embodiment will be described with reference to FIGS. Recently, the number of video devices that transmit and receive a baseband signal, that is, a Y color difference (Y / Cr / Cb signal) has been increasing for the purpose of improving the performance. This shows a configuration for receiving a signal. FIG. 9 shows an analog / digital composite V
2 shows a signal processing circuit of a TR. In this embodiment,
FIG. 4 is a configuration diagram in a case where Y color difference signal input terminals 91, 92, and 93 are provided in the digital VTR section 33 in the embodiment of FIG. When recording the Y color difference input on the magnetic tape, the switching circuit 94 controls the terminal 9 according to the control signal from the terminal 95.
1, 92, and 93 are selected and input to the interface circuit 96, and the MPEG2 encoder 2
1 is converted into a signal conforming to the input signal format. At this time, since the Y color difference signal is not modulated by the color subcarrier fsc, it is not necessary to process the Y color difference signal with a clock synchronized with fsc. Further, by switching the clock from CK1 to CK2, the rate conversion process in the interface circuit 96 becomes unnecessary, and the signal can be sent to the MPEG2 encoder 21 without image quality deterioration.

Next, a series of processes including the clock switching will be described in detail with reference to FIG. A composite video signal is input from an input terminal 101 and is supplied to an AD converter 10.
7 through the YC separation circuit 108 (YC separation circuit in FIG. 9).
The separation circuit 32 includes an AD converter 107), and is decoded by the decoder circuit 19 into a Y color difference signal,
09 to the terminal A side (A0, A1, A2). On the other hand, the Y color difference signal directly input to the set is supplied to terminals 91 and 9.
After being converted from 2 and 93 into digital signals by AD converters 104, 105 and 106, they are inputted to the terminal B side (B0, B1, B2) of the multiplexer 109.

When a composite video signal is input, fs
The clock CK1 obtained by multiplying c by N is selected by the switch circuit 97, AD conversion 107, YC separation 108, and decoding processing 19 are performed, and the terminal A of the multiplexer 109 is selected. In the interface circuit 96,
The rate converted to a 13.5 MHz signal by the rate converter 98 is selected by the multiplexer 99, converted by the signal converter 100 into a signal conforming to the input signal format of the MPEG2 encoder, and transmitted via the terminal 102 to the MPEG.
A signal is sent to two encoders.

At the time of inputting the Y color difference signal, the clock CK2 of the 13.5 MHz system is selected by the switch circuit 97, and AD
Conversions 104, 105, and 106 are performed, and the multiplexer 109 selects the terminal B side. In the interface circuit 96, a signal that is not rate-converted is selected by the multiplexer 99, and the signal
The signal is converted into a signal conforming to the input signal format of the EG2 encoder, and the signal is sent to the MPEG2 encoder via the terminal 102.

As described above, since the Y chrominance signal directly input can be transmitted to the MPEG encoder without performing the processing of the rate conversion circuit or the like, the image quality does not deteriorate in the middle process. Although not shown, the time base collector is also set to 13.
By performing processing with a 5 MHz clock, the rate conversion processing can be avoided.

In the above description of this embodiment, NTSC
VTR and MPEG2 encoder / decoder, D
VHS standard VTR has been described as an example.
The same applies to signals of other broadcast systems such as the AL system and the SECAM system.
The same applies to digital VTRs other than S, and is within the scope of the present invention. As a recording medium, in addition to a magnetic tape, a magnetic disk, an optical disk, a magneto-optical disk, and a semiconductor memory can be similarly applied, and a plurality of these recording media may be combined. At that time, the clock processing technique of the present invention can be applied even if the compression method differs depending on the recording medium.

[0040]

According to the present invention, the system clock on the digital processing side is generated by using the phase synchronization means of the color subcarrier of the analog VTR, so that there is no interference such as beat and the like, and the low-cost analog / Digital composite VTR can be realized.

By using a clock synchronized with the chrominance subcarrier for a standard signal input and using a fixed oscillation clock for a non-standard signal input, the performance for all external input signals can be ensured.

Demodulated signals with different clock rates and MPE
By providing an interface circuit that matches the clock rate and signal format with the G encoder, demodulation processing,
It is possible to provide a system that can directly connect all the MPEG compression processing and digital recording processing with digital, and to realize an LSI and promote a low cost analog / digital composite VTR.

Further, even when a YC separation circuit that performs clock processing by using the phase synchronization means of the color subcarrier of the analog VTR is also used, the signal before the time base collector is applied to the analog VTR and the signal before the MPEG encoder is applied. By inputting the signal after the time base collector and turning off the signal at the time of the standard signal and turning on the signal at the time of the non-standard signal, it is possible to provide a digital VTR with less malfunction even for the non-standard signal.

A signal applied to the analog VTR
By combining the GC circuit with the YC separation and the video output terminal, a low-cost analog / digital combined VTR can be provided.

Further, by switching between the digital recording and the analog recording to determine whether or not the AGC circuit supports the copy guard, it is possible to provide a composite VTR that addresses the copyright problem.

Further, for a device with a Y color difference signal input, a series of processes are performed with a 13.5 MHz system clock, so that MPEG compression can be performed without image quality deterioration, and image quality during recording and reproduction can be improved. Can be.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a signal processing system according to a first embodiment of an analog / digital combined VTR according to the present invention.

FIG. 2 is a modified example of the first embodiment of the combined analog / digital VTR according to the present invention.

FIG. 3 is a modification example of the first embodiment of the analog / digital combined VTR according to the present invention.

FIG. 4 is a configuration diagram of a signal processing system according to a second embodiment of the analog / digital combined VTR according to the present invention.

FIG. 5 is a diagram showing a configuration of a baseband demodulation process of a digital VTR unit in FIG. 4;

FIG. 6 is a schematic diagram showing time axis fluctuation of a non-standard signal on the television screen in FIG. 4;

FIG. 7 is a configuration diagram of a signal processing system according to a third embodiment of the analog / digital combined VTR according to the present invention.

FIG. 8 is a diagram illustrating a feedback loop for generating a chrominance subcarrier in FIG. 7;

FIG. 9 is a block diagram of a signal processing system according to a fourth embodiment of the analog / digital combined VTR according to the present invention.

FIG. 10 is a diagram showing a specific example of input and signal processing switching in FIG. 9;

[Explanation of symbols]

3, 32: YC separation circuit, 19: NTSC decoder, 21: MPEG2 encoder, 22: DVHS recording circuit, 26: DVHS reproduction circuit 27: MPEG2 decoder, 28: interface circuit, 30: analog VTR block, 31: digital VTR block 35, a multiplying circuit, 36, 51, 53, a clock generating circuit, 37, 39, a baseband modulation / demodulation processing circuit, 38, 50, a digital recording / reproducing processing circuit including an MPEG processing circuit, 98, a rate conversion circuit, 100, a signal Conversion circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideo Nishijima 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Multimedia Systems Development Division of Hitachi, Ltd. (72) Inventor Nao Horiuchi Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa No.292 Hitachi, Ltd. Multimedia System Development Headquarters (72) Inventor Tomoyuki Nonaka 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Multimedia System Development Headquarters (72) Inventor Hiroaki Suzuki Kanagawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi F-term in Hitachi Image Information System Co., Ltd. (reference) BA03 DA04 DA06 EA02 EA07 EA08 EA40 FA31 GA01

Claims (14)

[Claims] 1. An image information signal recording / reproducing apparatus having an analog signal recording / reproducing section and a digital signal recording / reproducing section, wherein the analog signal recording / reproducing section is provided with a color sub phase synchronized with a burst signal of an input analog video signal. A digital signal recording / reproducing unit for generating a clock signal obtained by multiplying the color subcarrier frequency; and the analog video signal operating by the clock signal. An image information signal recording / reproducing apparatus, comprising: decoding means for demodulating a signal into a baseband signal. 2. An image information signal recording / reproducing apparatus having an analog signal recording / reproducing section and a digital signal recording / reproducing section, wherein the analog signal recording / reproducing section is provided with a color sub phase synchronized with a burst signal of an input analog video signal. The digital signal recording / reproducing unit has a color sub-carrier generating unit for generating a carrier wave, the digital signal recording / reproducing unit includes a decoding unit for demodulating the analog video signal into a baseband signal, and a color sub-carrier generated by the analog signal recording / reproducing unit. A multiplied clock generating means for synchronizing and multiplying the same, a fixed oscillation clock generating means for generating an N-fold clock asynchronous to the color subcarrier frequency, and detecting a time axis fluctuation of the analog video signal to determine whether the signal is a standard signal. A non-standard discriminating means for discriminating whether the analog video signal is a standard signal or not. Wherein the clock signal generated by the clock generation means causes the decoding means to operate by the clock signal generated by the fixed oscillation clock generation means when the analog video signal is a non-standard signal. apparatus. 3. An analog video signal to be inputted is MPEG
An image information signal recording / reproducing apparatus for compressing and recording / reproducing on a recording medium, decoding means for demodulating the analog video signal to a baseband signal, and MP for compressing the demodulated baseband signal to MPEG.
EG encoding means, digital recording means for recording an MPEG-compressed signal on the recording medium, first clock generation means for operating the decoding means, MPEG encoding means and digital recording means An image information signal recording / reproducing apparatus comprising: a second clock generating means for operating; and an interface means for converting a clock rate and a signal format between the decoding means and the MPEG encoding means. . 4. An image information signal recording / reproducing apparatus for digitally compressing an input analog video signal and recording / reproducing the information on a plurality of recording media, decoding means for demodulating the analog video signal into a baseband signal, A plurality of encoding means for digitally compressing the baseband signal in accordance with the plurality of recording media; a plurality of digital recording means for recording the digitally compressed signal on the plurality of recording media; A first clock generating means for operating; a plurality of encoding means; and a second clock generating means for operating the plurality of digital recording means in accordance with the plurality of digital recording means. Characterized in that an interface means for converting between a clock rate and a signal format is provided between Broadcast signal recording and reproducing apparatus. 5. The image information signal recording / reproducing apparatus according to claim 4, wherein the plurality of recording media are selected from a magnetic tape, a magnetic disk, an optical disk, a magneto-optical disk, and a semiconductor memory. An image information signal recording / reproducing device characterized by the above-mentioned. 6. An analog video signal input to an MPEG
An image information signal recording / reproducing apparatus for compressing and recording / reproducing, a YC separation circuit for separating the analog video signal into a luminance signal and a chrominance signal, a time base collector for correcting a time axis variation, the YC separation circuit, A field memory or a frame memory commonly used for a time base collector, and non-standard discriminating means for detecting a time axis fluctuation of the analog video signal and discriminating whether the signal is a standard signal or a non-standard signal, The YC separation circuit has a two-dimensional YC separation circuit and a three-dimensional YC separation circuit.
When the analog video signal to be input is a standard signal, the YC separation circuit switches to the three-dimensional YC separation circuit.
And, when the time base collector is turned off and the input analog video signal is a non-standard signal, the YC separation circuit switches to the two-dimensional YC separation circuit,
And an image information signal recording / reproducing apparatus characterized in that the time base collector is turned on. 7. An image information signal recording / reproducing device having an analog signal recording / reproducing section and a digital signal recording / reproducing section, wherein the analog signal recording / reproducing section and the digital signal recording / reproducing section convert an input analog video signal into a luminance signal. An image information signal recording / reproducing apparatus comprising a common YC separation circuit for separating a signal and a color signal. 8. The image information signal recording / reproducing apparatus according to claim 7, wherein the digital signal recording / reproducing section is configured to correct a time base variation of an output of the YC separation circuit, and to convert the correction signal into an MPEG signal. MPEG encoding means for compression;
Digital information recording means for recording the MPEG-compressed signal on a recording medium. 9. An image information signal recording / reproducing apparatus having an analog signal recording / reproducing section and a digital signal recording / reproducing section, wherein the analog signal recording / reproducing section and the digital signal recording / reproducing section convert an input analog video signal into a luminance signal. The digital signal recording / reproducing unit has a three-dimensional YC separation circuit, which independently has a YC separation circuit for separating a signal and a color signal.
An image information signal recording / reproducing device comprising a C separation circuit. 10. An image information signal recording / reproducing apparatus having an analog signal recording / reproducing section and a digital signal recording / reproducing section, wherein the analog signal recording / reproducing section and the digital signal recording / reproducing section adjust an input analog video signal amplitude. A common automatic gain control circuit that controls the digital signal to be constant; during a recording operation performed by the analog signal recording / reproducing unit, the automatic gain control circuit responds to a copy guard signal included in the input analog video signal; An image information signal recording / reproducing apparatus, wherein the automatic gain control circuit is set not to respond to a copy guard signal included in the input analog video signal during a recording operation by the signal recording / reproducing unit. 11. The automatic gain control circuit according to claim 1, wherein said automatic gain control circuit is provided on said analog signal recording / reproducing unit side.
0. An image information signal recording / reproducing apparatus according to 0. 12. An image information signal recording / reproducing apparatus having an analog signal recording / reproducing section and a digital signal recording / reproducing section, wherein the analog signal recording / reproducing section and the digital signal recording / reproducing section adjust an input analog video signal amplitude. The analog signal recording / reproducing section has an automatic gain control circuit for controlling the analog signal independently. The automatic gain control circuit of the analog signal recording / reproducing section responds to a copy guard signal included in the input analog video signal. Wherein the automatic gain control circuit is set so as not to respond to a copy guard signal included in the input analog video signal. 13. An image information signal recording / reproducing apparatus having an analog signal recording / reproducing section and a digital signal recording / reproducing section, wherein a video signal reproduced by the analog signal recording / reproducing section and the digital signal recording / reproducing section is output. An image information signal recording / reproducing device having a common video output terminal. 14. An analog video signal input to an MPE
An image information signal recording / reproducing apparatus for recording / reproducing a G-compressed data on a recording medium, comprising: an input terminal for inputting a composite video signal and a Y color difference signal; an AD converter for converting each of the input signals into a digital signal; Decoding means for demodulating a video signal into a baseband signal; MPEG encoding means for MPEG-compressing the baseband signal; digital recording means for recording the MPEG-compressed signal on a recording medium; and generating clock signals having mutually different frequencies. A first clock generation unit, a second clock generation unit, and an interface unit for performing clock rate conversion and signal format conversion between the decoding unit and the MPEG encoding unit; the MPEG encoding unit and the digital recording Means for generating the second clock With operating at stage, when the input signal is a composite video signal, the A
The D converter is operated by the first clock generating means. When the input signal is a Y color difference signal, the AD converter is operated by the second clock generating means, and the clock rate of the interface means is changed. An image information signal recording / reproducing apparatus characterized in that conversion is made through.