JP2541251B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device having a complementary MIS transistor having an LDD structure.

[Outline of Invention]

According to the present invention, in the method for manufacturing a semiconductor device as described above, the impurity is introduced into a portion of the semiconductor substrate having a relatively high impurity concentration by diffusion from the semiconductor layer,
In addition, by compensating impurities when introducing impurities of relatively low concentration and relatively high concentration, a high quality semiconductor device can be manufactured without complicating the process.

[Conventional technology]

In order to manufacture a semiconductor device having a complementary MIS transistor such as CMOS, for example, by covering the p-type region with a mask and performing ion implantation, the source / drain regions of the p-channel MOS transistor are formed in the n-type region. It is generally considered that the source / drain regions of the n-channel MOS transistor are formed in the p-type region by forming the n-type region, and then performing ion implantation while covering the n-type region with a mask.

Then, in order to make the transistor have an LDD structure, it is necessary to perform ion implantation of a low-concentration impurity and a high-concentration impurity twice for each type of region.

[Problems to be solved by the invention]

However, if the semiconductor substrate is ion-implanted a number of times, particularly if a high-concentration impurity is ion-implanted with high energy, the semiconductor substrate is greatly damaged. Therefore, the quality of the semiconductor device formed on such a semiconductor substrate is low.

On the other hand, Japanese Unexamined Patent Publication No. 61-123181 discloses a method of forming a semiconductor layer on a semiconductor substrate and diffusing high-concentration impurities from the semiconductor layer into the solid phase. In this method, since a high concentration impurity is not ion-implanted into the semiconductor substrate, the semiconductor substrate is not damaged.

However, if this method is applied to manufacture of a CMOS having an LDD structure, two masks are required for the semiconductor layer, and a total of four masks are required in addition to the above two masks. Therefore, this method complicates the manufacturing process.

[Means for solving problems]

The method for manufacturing a semiconductor layer according to the present invention includes an insulating film 1 on the upper surface.
Forming gate electrodes 21 and 22 having 7 and 18 on the semiconductor regions 13 and 14 of the first and second conductivity types, respectively, and using the gate electrodes 21 and 22 as a mask, the first and second conductivity types The relatively low concentration of the impurity 23 of the first conductivity type into the semiconductor regions 13 and 14, and the semiconductor region 14 of the second conductivity type.
Forming a first mask 24 thereon, and using the first mask 24 and the gate electrode 21 as a mask, a semiconductor layer 13 of a second conductivity type having a relatively low concentration is applied to the semiconductor region 13 of the first conductivity type. A step of introducing impurities 25 to compensate the impurities; a step of removing the first mask 24 to form insulating films 26 and 27 on the side surfaces of the gate electrodes 21 and 22; A step of stacking the semiconductor layer 28 on at least the portions where the impurities 23 and 24 are introduced, and introducing one of the relatively high concentration first and second conductivity type impurities 31 and 33 into the semiconductor layer 28. And a step of forming a second mask 32 on the semiconductor region 14 having a conductivity type different from that of the impurities 31 introduced in this step, and a relatively high concentration of the first and second conductivity types. The other one of the impurities 31, 33 is covered with the second mask 32 of the semiconductor layer 28. A step of introducing impurities into a non-existing portion to compensate impurities, and a relatively high concentration of impurities of the first and second conductivity type introduced into the semiconductor layer 28.
Impurity diffusion regions 3 are formed by diffusing 1, 33 into the semiconductor substrate 11.
6 and 37 are formed, respectively.

[Action]

In the method of manufacturing a semiconductor device according to the present invention, in the source / drain regions 34 to 37 of the MIS transistor, the impurity concentration in the portions 34 and 35 below the insulating films 17 and 18 on the side surfaces of the gate electrodes 21 and 22 is relatively low. The impurity concentration in the other portions 36 and 37 is relatively high, but the impurities 31 and 33 are introduced into the portions 36 and 37 in which the impurity concentration is relatively high by diffusion from the semiconductor layer 28. Therefore, the semiconductor substrate 11 is less damaged than the case where only ion implantation is performed.

In addition, the impurities 23 and 25 having a relatively low concentration are added to the semiconductor substrate 11.
In both the case of introducing impurities into the semiconductor layer 28 and the case of introducing impurities 31 and 33 having a relatively high concentration into the semiconductor layer 28, it is necessary even though the impurities are diffused from the semiconductor layer 28. The number of masks 24 and 32 does not increase.

〔Example〕

An embodiment of the present invention applied to a LDD structure CMOS structure will be described below with reference to FIG.

In this embodiment, as shown in FIG. 1A, a field oxide film 12 is first formed on the surface of an n-type si substrate 11, and an n-type region 13 and a p-well are divided along the field oxide film 12. Forming 14 and.

Next, on the gate oxide film 15 in the n-type region 13 and the gate oxide film 16 in the p well 14, gate electrodes 21 and 22 having insulating films 17 and 18 on the upper surfaces are formed, respectively.

Then, using these gate electrodes 21 and 22 as a mask,
Ion implantation of low-concentration n-type impurity 23 is performed on the entire surface of the Si substrate 11. Therefore, this low-concentration n-type impurity 23 is implanted into both the n-type region 13 and the p-well 14.

Next, as shown in FIG. 1B, only the p well 14 is covered with a resist mask 24, and the resist mask 24 and the electrode 21 are used as a mask to ion-implant a low concentration p-type impurity 25.

The p-type impurity 25 has a low concentration but a higher concentration than the n-type impurity 23. Therefore, in the n-type region 13, the n-type impurity 23 implanted in the step of FIG. 1A is compensated, and it becomes substantially the same as the state where only the low-concentration p-type impurity 25 is implanted.

Next, as shown in FIG. 1C, the resist mask 24 is removed, and insulating films 26 and 27 are formed also on the side surfaces of the gate electrodes 21 and 22. The insulating films 26 and 27 can be formed by a conventionally known method such as RIE.

Then, in this state, a polycrystalline Si layer 28 is formed on the entire surface of the Si substrate 11, and a high-concentration n-type impurity is formed on the entire surface of the polycrystalline Si layer 28.
31 is ion-implanted.

Next, as shown in FIG. 1D, only a portion of the polycrystalline Si layer 28 corresponding to the p well 14 is covered with a resist mask 32,
In this state, high concentration p-type impurity 33 is ion-implanted.

The p-type impurity 33 has a higher concentration than the n-type impurity 31. Therefore, in the portion of the polycrystalline Si layer 28 corresponding to the n-type region 13, the n-type impurity 31 implanted in the step of FIG. 1D is used.
Is compensated, and the state becomes substantially equivalent to the state in which only the high-concentration p-type impurity 33 is implanted.

Next, when the resist mask 32 is removed and the Si substrate 11 is heat treated, as shown in FIG. ^- region 34 and n ^- with region 35 is formed from the polycrystalline Si layer 28 to the n-type region 13 and p-well 14 a high concentration of p-type impurities 33
And the n-type impurity 31 diffuses into the solid-solid phase to form the p ^- region 34 and
Between the n ⁻ region 35 and the field oxide film 12, the p ⁺ region 36 and the n ⁺
Regions 37 are formed respectively.

After that, the polycrystalline Si layer 28 is patterned to form contact layers 38 and 39 for the p ⁺ region 36 and the n ⁺ region. The CMOS manufactured according to this embodiment is
As is clear from FIG. 1E, it has an LDD structure.

In this example, the high-concentration impurities 31 and 33 are mixed with polycrystalline Si.
The polycrystalline Si layer 28 is patterned into the contact layers 38 and 39 after the ion implantation into the layer 28.However, after the polycrystalline Si layer 28 is patterned, the high-concentration impurities 31 and 33 are ion-implanted. Good.

〔The invention's effect〕

In the method for manufacturing a semiconductor device according to the present invention, since the number of required masks does not increase and the process is not complicated, the semiconductor substrate can be manufactured with high quality because damage to the semiconductor substrate is small.

[Brief description of drawings]

FIG. 1 is a side sectional view sequentially showing an embodiment of the present invention. In the reference numerals used in the drawings, 11 ... Si substrate 13 ... n-type region 14 ... p-well 17,18 ... insulating film 21,22 ... gate electrode 23 ... low-concentration n-type impurity 24 ... Resist mask 25 …… Low-concentration p-type impurities 26,27 …… Insulating film 28 …… Polycrystalline Si layer 31 …… High-concentration n-type impurities 32 …… Resist mask 33 …… High-concentration p-type impurities 34… … P ^- region 35 …… n ^- region 36 …… p ⁺ region 37 …… n ⁺ region.

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a second conductivity type MIS transistor in a first conductivity type semiconductor region of a semiconductor substrate, and a first conductivity type MIS transistor in a second conductivity type semiconductor region. A step of forming a gate electrode having an insulating film on an upper surface thereof on each of the first and second conductive type semiconductor regions, and using the gate electrode as a mask, relative to the first and second conductive type semiconductor regions. A step of introducing a low-concentration first-conductivity-type impurity into the substrate, a step of forming a first mask on the second-conductivity-type semiconductor region, and a step of using the first mask and the gate electrode as masks. A step of introducing a relatively low concentration second-conductivity-type impurity into the first-conductivity-type semiconductor region to compensate for the impurity; and removing the first mask to form an insulating film on a side surface of the gate electrode. And forming the semiconductor Stacking a semiconductor layer on at least the portion of the base body into which the impurities are introduced; and introducing one of relatively high-concentration impurities of the first and second conductivity types into the semiconductor layer, A step of forming a second mask on the semiconductor region having a conductivity type different from that of the impurities introduced in the step, and the other of the impurities of the first and second conductivity types having a relatively high concentration A step of introducing into a portion of the layer not covered by the second mask to compensate impurities, and a relatively high concentration of the impurities of the first and second conductivity types introduced into the semiconductor layer. And a step of forming an impurity diffusion region by diffusing into the semiconductor substrate.