JP2530916B2 - Arithmetic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] An arithmetic circuit for fetching input data and performing a cumulative addition operation of a predetermined arithmetic operation, in order to reliably perform a cumulative addition operation of a predetermined arithmetic operation with a simple hardware configuration, , A cumulative adder that receives the output of the computing unit and cumulatively adds the computation results of N samples, a first register that holds the cumulative addition result of one sample before, and the computing unit Second register for receiving the operation result of the input data at the present time and the third register for receiving the operation result N + 1 samples before in response to the output of the operation unit, the first register and the first register An adder for adding the outputs of the two registers, a subtractor for subtracting the output of the third register from the output of the adder, and usually the output of the subtractor is connected to the first register, and 1 is connected to N samples. Cumulative addition only once Switching means for connecting the output of the subtracter to the first register and clearing the cumulative adder, and is configured to use the output of the subtractor as its output.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic circuit which takes in input data and performs cumulative addition operation of sum of squares.

Various devices require a process of holding input data up to N samples before the present input data in a memory and performing an iterative operation using the N data within one sampling period. For example, in order to obtain the power up to N samples before, Σxi ² (xi represents the input data before the time point i. The same applies below), or when obtaining the first-order correlation between N samples, Σxi · x There are cases where _i-1 is calculated.

[Prior Art] FIG. 3 is a configuration block diagram of a conventional circuit, which is a circuit for performing cumulative addition of sums of squares. In the figure, 1 is a shift register that holds N pieces of data, which is the data currently fetched.
N pieces of data from x ₀ to data _N times before N samples are stored. This shift register 1 shifts data one by one by a shift clock, and every time one data is input, overflow data is discarded. The data input to the shift register 1 is stored in the register 2
The outputs xi of the registers 2A and 2B are held in A and 2B and enter the multiplier 3 to be squared. Output xi ^{2 of} multiplier 3
Enters the adder 4, and is added to the cumulative addition value Σxi ² up to that point to become the output 5.

In the circuit shown in the figure, N pieces of input data are held in the shift register 1, the held input data are sequentially stored in the registers 2A and 2B from the shift register 1 (), and xi ² Is performed (), the multiplication result is put into the adder 4, and the cumulative addition value up to that time is added () is repeated N times. As a result, the adder 4 obtains a cumulative addition value Σxi ² of N pieces of data.

This method requires a memory (here, the shift register 1) for holding N pieces of data, and requires the number of calculations according to N. Therefore, in this method, particularly when N becomes large, the hardware scale increases and the calculation speed decreases. For example, even if each of the above-mentioned three steps can be performed in one machine cycle, an operation time of three machine cycles is required for one data. Therefore, 3N machine cycles are required for N data, which requires a long calculation time.

In order to eliminate such a defect, an arithmetic circuit as shown in FIG. 4 has been devised. This circuit adds only the difference between the value of the incoming data and the value of the discarded data to the cumulative addition value, eliminating the inconvenience shown in FIG. The same parts as those in FIG. 3 are designated by the same reference numerals. In the figure, 10 is a register that holds N cumulative addition values, 11 is a register that holds the square xo ² of the current input data, and 12 is a register that holds the square x _N ² of the input data N + 1 samples before. Is. 13 is register 10
Reference numeral 14 is an adder for performing an addition operation on the outputs of 11 and 11, and 14 is a subtractor for subtracting the output of the register 12 from the output of the adder 13.
The output 15 of the subtractor 14 is the output of the circuit.

In the circuit configured as described above, the register 2A holds the current input data xo, and the register 2B holds the input data x _N before N + 1 samples, which are respectively squared by the multiplier 3 Held at 11,12. The register 10 holds the cumulative addition value Σ of one sample before. When one new data is input, the oldest data is discarded. Therefore, if only the difference between them is added to the cumulative addition value, the cumulative addition value after new data is input can be obtained. Here, if the cumulative addition value of the register 10 is Σ and the output of the register 11 is xo ² , the output Out1 of the adder 13 is expressed by the following equation.

Out1 = Σ + xo ² (1) Next, the output O of the subtractor 14 which receives the output of the adder 13 at one of its + inputs and the output x _N ² of the register 12 at the other − input
ut2 is expressed by the following equation.

^{_{Out2 = Out1-x N 2 =}} Σ + xo 2 -x N 2 (2) (2) equation represents the accumulated value of the current. As described above, a register for holding three data of Σ, xo ² and x _N ² is provided and these data are held, and the current input data xo ² is input to the cumulative adder Σ one sample before. By adding and subtracting the squared value x _N ² of the input data N + 1 samples before can have the same function as the arithmetic circuit shown in FIG. 3 (however, until N samples after the start of the first arithmetic operation) except).

In the circuit shown in FIG. 4, regardless of the value of N, the register (memory) needs to have three words, so that the scale of hardware is significantly reduced as compared with the configuration of the circuit shown in FIG. Next, consider the calculation speed. xo, x _N is stored in registers 2A and 2B (), the square value of these data is obtained by the multiplier 3 (), each square value is stored in the registers 11 and 12 (), and the adder 13 Add xo ² to Σ with () and subtracter 1
In step 4, x _N ² is subtracted from the adder output (), and the result is stored again in the register 10 ().

Assuming that perform each operation sequence in each machine cycle, - the two data xo respectively, considering that performed on x _N, it is possible operations in nine machine cycles. In the circuit shown in FIG. 4, regardless of the value of N,
Since the calculation can be performed in 9 cycles, the processing time has been greatly shortened.

[Problems to be Solved by the Invention] However, since the circuit shown in FIG. 4 does not have a memory (or register) for holding N pieces of input data, the power supply voltage fluctuates due to a lightning strike, etc. If the contents are destroyed, there is a problem that a normal addition operation cannot be performed thereafter. For example, considering the example of FIG. 3, when xo and x _N are destroyed, the effect remains only for N samples, and correct operation values can be obtained after N + 1 samples. On the other hand, in the case of the circuit shown in FIG. 4, if the register 10 holding Σ is destroyed, the influence of Σ cannot be permanently removed.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an arithmetic circuit capable of reliably performing the cumulative addition operation of the sum of squares with a simple hardware configuration.

[Means for Solving the Problems] FIG. 1 is a block diagram showing the principle of the present invention. The same parts as those in FIG. 4 are designated by the same reference numerals. In the figure,
Reference numeral 3'denotes an arithmetic unit for computing the input data, 20 denotes a cumulative adder for receiving the output of the arithmetic unit 3'and performing cumulative addition of the calculation results of N samples, and 10 holds the cumulative addition result of one sample before. A first register 11 is a second register which receives the output of the arithmetic unit 3'and holds the arithmetic result of the current input data, and 12 is an arithmetic result N + 1 samples before the output of the arithmetic unit 3 '. Is a third register for holding, 13 is the first
Of the register 10 and the second register 11, the adder 14 subtracts the output of the third register 12 from the output of the adder 13, and the output 21 of the subtractor 14 is usually the output of the subtracter 14. 1
The register 10 is connected to the register 10, the output of the cumulative adder 20 is connected to the first register 10 only once every N samples, and the switch is a switch means for clearing the cumulative adder 20.

[Operation] In the normal arithmetic operation, the operation according to the equation (2) is performed from the data held in the first to third registers 10 to 12, and the operation of storing the result in the first register 10 again is repeated. , Operates in the same way as the circuit shown in FIG. On the other hand, the cumulative adder 20 is performing cumulative addition of the input data, and N
Only once in the sample, the switch 21 is switched to the cumulative adder 20 side and the result is stored again in the first register 10. Therefore, according to the present invention, even if the first register 10 is destroyed, its effect remains for a maximum of N samples, and N +
Correct accumulative addition operation values can be obtained after 1 sample. Moreover, since a memory for holding N pieces of input data is not required, the hardware configuration is simple.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a configuration block diagram showing an embodiment of the present invention. The same parts as those in FIGS. 1 and 4 are designated by the same reference numerals. In the figure, 30A is a register for holding the input data xo at the present time, and 30B is a register for holding the input data x _N N + 1 samples before. 2A and 2B are registers that hold the same data for the square operation.

The cumulative adder 20 is composed of an adder 20a and a register 20b, and the output of the register 20b is fed back to one input of the adder 20a. To the other input of the adder 20a,
The squared output of the multiplier 3'as an arithmetic unit is input. Reference numeral 31 denotes an N sample counter, which controls the switch 21 to switch from the subtractor 14 side to the cumulative adder 20 side only once every N samples. The operation of the circuit thus configured will be described below.

Of the input data held in the registers 30A and 30B, the data x _N before N + 1 samples are read from the register 30B and held in the registers 2A and 2B. Multiplier 3 '
Performs multiplication of the same data held in these registers 2A and 2B. Then, the multiplication result x _N ² is held in the third register 12 (hereinafter referred to as register 3). In this case, the multiplication result x _N ² is not input to the adder 20a. Next, the current input data xo is read from the register 30A and held in the registers 2A and 2B. The multiplier 3'multiplies the same data held in the registers 2A and 2B. The multiplication result xo ² is held in the second register 11 (hereinafter referred to as register 2).

On the other hand, the cumulative value Σ of the sum of squares is held in the first register 10 (hereinafter referred to as register 1). While the switch 21 is connected to the subtractor 14 side, the arithmetic circuit shown in the figure performs the operation represented by the equation (2), and the latest N samples are accumulated from the subtractor 14 every time new data is input. The added value is output and held in the register 10.

Also, on the cumulative adder 20 side, every time the square data of the input data xi is output from the multiplier 3 ', it is added to the addition value up to that point. Specifically, the operation in which the adder 20a adds the cumulative addition value held in the register 20b and the input squared data and adds the result to the register 20b again is repeated. Therefore, when the operation of both circuits is normal, the cumulative addition result of N samples is equal to the output value of the register 20b and the output value of the subtractor 14.

On the other hand, the N sample counter 31 counts up by +1 each time new data is input, and when the count value reaches N, the switch 21 is moved from the subtractor 14 side up to that time to the cumulative adder 20 side. Switching is performed, and the calculation result of the cumulative adder 20 is stored in the register 10. At this time, the accumulator 20
The content of is cleared. This is to prepare for the next cumulative addition. If both arithmetic circuits are operating normally, register 10
Even if the data of is replaced by the output of the cumulative operation circuit 20, the result does not change.

However, if the contents of register 10 are lost due to a lightning strike,
After that, the circuit portion shown in FIG. 4 cannot perform a normal operation. However, according to the present invention, if N samples are waited, the correct cumulative value of the cumulative adder 20 is set in the register 10.
Is set to, the accurate cumulative addition operation can be performed after N + 1 samples.

Next, consider the processing speed of the present invention. The present invention includes, in addition to the operation of the circuit shown in FIG. 4, a sequence () for counting N samples, a sequence () for adding the contents of the register 20b and the square of the input data by the adder 20a, and an addition result. The sequence () that stores the value in the register 20b and the register when the Nth sample is reached
The content of 20b is controlled to be stored in the register 1, the content of the register 20b is cleared after the storage, and the sequence () for storing the conventional output value in the register 1 is added in other sequences.

, Is 1 machine cycle, is about 10 machine cycles, is about 7 machine cycles, which is a total increase of about 19 cycles. In consideration of the case where the conventional process is executed in about 9 machine cycles, the number of machine cycles is 28 machine cycles in the present invention. In the case of the conventional circuit shown in FIG. 3, the number of machine cycles increases in proportion to N, and 3N machine cycles are required, but in the present invention, regardless of the value of N,
It can be processed in 28 machine cycles. In the present invention, N
Even if is large, the calculation speed can be significantly improved.

On the other hand, in terms of hardware, the number of registers is increased from three registers 1, 2, and 3 to one register 20b as compared with the circuit of FIG. 4, and there is almost no increase compared with the conventional circuit. By reducing the memory, even if the power supply voltage fluctuates due to lightning, it is possible to reduce the probability of being affected to 4 / N, and even if the memory (register) is destroyed, it will be correct within a certain time. Can work again.

In the above description, the case where the combination of the adder 20a and the register 20b is used as the cumulative adder 20 is taken as an example, but the present invention is not limited to this, and the cumulative addition result can be obtained by iterative calculation. If it is, it may be anything. Further, the arithmetic unit 3'is not limited to the multiplier, but may be any unit as long as it performs a certain arithmetic operation on a plurality of data.

EFFECTS OF THE INVENTION As described in detail above, according to the present invention (2)
While obtaining the cumulative calculation result by the formula, the cumulative addition of the input data is obtained by the cumulative adder that performs the cumulative addition of the data of N samples, and the calculation result of the calculation formula (2) is obtained only once every N samples. By configuring the register to be set in the register, the cumulative addition operation of the sum of squares can be reliably performed with a simple hardware configuration.

[Brief description of drawings]

 1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 3 is a block diagram showing a conventional circuit, and FIG. 4 is a block diagram showing another configuration of the conventional circuit. Is. In FIG. 1, 3'is an arithmetic unit, 10,11,12 are registers, 13 is an adder, 14 is a subtractor, 20 is a cumulative adder, and 21 is a switch.

Claims (1)

(57) [Claims] 1. A computing unit for computing input data, a cumulative adder for receiving the output of the computing unit and cumulatively adding the computation results of N samples, and a first holding unit for holding the cumulative addition result of one sample before. A second register for receiving the output of the arithmetic unit and holding the arithmetic result of the current input data; and a third register for receiving the output of the arithmetic unit and holding the arithmetic result N + 1 samples before. , An adder for adding the outputs of the first register and the second register, a subtractor for subtracting the output of the third register from the output of the adder, and usually the output of the subtractor for the first register Arithmetic circuit which connects the output of the cumulative adder to the first register once every N samples and clears the cumulative adder, and uses the output of the subtractor as its output.