JP2525668B2 - How to configure the electrode extraction part - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method of configuring an electrode lead-out portion in a semiconductor integrated circuit device.

(Prior Art) With the recent progress in high density and high integration of semiconductor integrated circuit devices, ultra-miniaturization of integrated elements and multi-layering of wiring layers have become major problems to be solved. Above all, it is difficult to miniaturize metal wiring, and there are many technical problems to be solved in order to make commonly used aluminum wiring fine wiring of 1 μm or less. Connection to a contact hole with a high aspect ratio due to contact hole formation, instability of connection due to deterioration of aluminum vapor deposition coating in the contact hole, or variation in depth of contact hole at electrode extraction part due to multilayer wiring. And the like.

FIG. 3 is a sectional view for explaining the above-mentioned problems by taking an NMOS type transistor as an example. FIG. 3A is a plan view.
(B) is a sectional view taken along the line AA ', and (c) is an equivalent circuit (see "Electronic Materials", June 1986, published by the Industrial Research Institute, P.22 to P.27).

In the figure, 1 is a P-type silicon substrate, 2 is an element isolation region made of silicon dioxide, 3 is a gate insulating film, 4 is a polycrystalline silicon film having N-type conductivity, and constitutes a gate electrode.
Reference numerals 5a and 5b are N-type diffusion regions as sources and drains, 6 is an interlayer insulating film made of flow glass, 7 is a contact hole, and 8a and 8b are aluminum alloy electrodes from the N-type diffusion regions 5a and 5b, respectively. The protective film on the surface is omitted in the description.

In the above configuration, the opening of the contact hole 7 is y = 0.8 μm, the cross-sectional area is 0.8 μm ² , the film thickness of the interlayer insulating film 6 is 0.6 μm, and the aspect ratio of the contact hole 7 is 0.7 μm.
It will be 5. It is technically difficult to form an electrode by vapor-depositing an aluminum alloy on such a minute hole portion having a high aspect ratio, and the success or failure thereof greatly affects the reliability of the semiconductor integrated circuit device. .

The distance x from the polycrystalline silicon film 4 of the gate electrode is 0.5
Since it is as small as μm, the contact hole 7 cannot be formed large, and eventually aluminum will be vapor-deposited in the contact hole 7 having a high aspect ratio as in the present case. In that case,
The uniform deposition cannot be performed, the deposited film on the inner wall of the contact hole becomes thin, and microrack is likely to occur at the bottom corner.

From the above, the diameter of the contact hole is 1.
When the size is reduced to 0 μm, aluminum atoms cannot sufficiently enter the inside by vapor deposition, so that it is impossible to form an electrode having a stable connection with a uniform aluminum coating.

(Problems to be Solved by the Invention) In view of the above-mentioned problems in the structure of the electrode portion of the invention, the present invention is applicable to the extraction of electrodes having a fine structure of a high-density semiconductor integrated circuit device and maintains the stability of connection. It is an object of the present invention to provide a method of forming an electrode structure that can be easily formed.

(Means for Solving the Problems) The present invention is directed to solving the above problems by forming a polycrystalline silicon film on the surface of an impurity diffusion layer formed on the main surface of a semiconductor substrate during formation of a semiconductor integrated circuit device, A selective etching step of leaving it in an area where contact holes are to be formed in an island shape; a selective etching step of removing the interlayer insulating film above the island-shaped portion after covering the interlayer insulating film; and an opening of the interlayer insulating film. Part of the polycrystalline silicon film in the island shape is selectively removed by using the mask as a mask, and a contact hole having a stepwise inner wall is formed, and a conductive film is deposited on the upper surface of the main surface to form an electrode pattern. This is achieved by the forming process.

(Operation) According to the present invention having the above electrode configuration, the electrode can be stably taken out from the fine contact hole, and the reliability of the semiconductor integrated circuit device can be improved.

(Example) The present invention will be described below by way of an example with reference to the drawings.

FIG. 1 is a diagram for explaining the first embodiment of the present invention.
In the manufacturing process cross-sectional view in which the electrodes are taken out from the source and drain diffusion regions of the type transistor, the same reference numerals are used for the functional portions that are the same as or equivalent to those in FIG.

First, in FIG. 1A, an element isolation region 2 made of silicon dioxide is formed on a P-type silicon substrate 1,
Reference numeral 3 is a gate insulating film, 4 is an N-type conductive polycrystalline silicon film, and 5a and 5b are N-type diffusion regions as a source and a drain, respectively. Further, 11 is a thin silicon dioxide film having a thickness of about 200 Å, 12 is a first polycrystalline silicon film involved in the formation of contact holes, and the film thickness is 0.5 μm.

Next, as shown in FIG. 6B, the first polycrystalline silicon film 12 is formed on the island-shaped portion 121 by selective photoetching in the region where the contact hole is to be formed. In this case, the etching is completed by the underlying silicon dioxide film 11. To make the contact hole 0.8 μm on each side, an etching pattern of 0.7 μm to 0.8 μm is formed. Since this is a pattern that remains like islands, it is easy to form.

Next, as shown in Figure (c), BPSG film (Borophosphosilic
ate Glass film: Phosphorus borosilicate glass film) is covered with the interlayer insulating film 13 on the island-like portion 121 of the first polycrystalline silicon film, 0.5 μm is deposited, and reflow is performed at 900 ° C.

Next, as shown in FIG. 3D, the interlayer insulating film 13 is selectively photo-etched to form an opening 71 which becomes a part of the contact hole, and then the second polycrystalline silicon film 14 is removed to 0. .
Deposit 3 μm. The optimum film thickness is determined from the total interlayer insulating film thickness (= total thickness of the above-mentioned and later-described interlayer insulating films 13 and 15).

Next, as shown in FIG. 2E, the second polycrystalline silicon film 14 is formed.
Is selectively photo-etched to form a portion 141 of the second polycrystalline silicon film which overlaps the island-shaped portion 121 of the first polycrystalline silicon film at the portion of the hole opening 71. Next, the second interlayer insulating film 15 made of the BPSG film is formed into a thin film.
After depositing 6 μm and reflowing at 900 ° C., it is selectively photoetched so as to cover the portion 141 of the second polycrystalline silicon film to open a part 72 of the contact hole, and
The upper surface of the portion 141 of the polycrystalline silicon film is exposed. Next, using the photomask 21 at that time, the portion 141 of the second polycrystalline silicon film and the island-shaped portion 121 of the first polycrystalline silicon film are removed by selective plasma etching of the polycrystalline silicon film, Further, by etching the thin silicon dioxide film 11 with an oxide film, the source and drain N
The electrode forming portions of the type diffusion layer regions 5a and 5b are exposed.

Next, as shown in FIG. 6F, an aluminum alloy film is deposited on the contact hole opened as described above, and the aluminum alloy film is selectively etched to form aluminum alloy electrodes 8a and 8b, and after sintering, a plasma nitride film is formed. Depending on the device surface protection film
Forming 16.

The side wall of the contact hole of the present invention formed as described above has, as highlighted, the island-like portion 121 of the two-layer polycrystalline silicon film, the same portion 141, and the two-layer interlayer insulating film 1.
Although it looks like a staircase due to 3,15, it actually has an extremely gentle taper shape, and the opening of the surface of the contact hole is quite large and seems to overlap the polycrystalline silicon film 4, but the interlayer insulating film 13, Since it is insulated by 15, it does not affect the operation of the device.

According to this embodiment, the island-shaped portion 12 of the polycrystalline silicon film is formed.
If the size of 1 is 0.8 μm, the surface opening of the contact hole can be formed to 2.0 μm, which is sufficient for aluminum atoms to evenly penetrate into the interior during aluminum vapor deposition, resulting in stable electrode connection. In addition, the surface protection film 16 of the element,
By improving the shape of the contact hole, the inside of the contact hole can be protected uniformly.

In general, in a contact hole with a diameter of 1 μm or less, if an aluminum / silicon alloy is used for electrode connection, silicon is likely to precipitate and a connection failure easily occurs, but in order to avoid it, a heat-resistant alloy such as molybdenum silicide and an aluminum By growing a double-structured film of a silicon alloy, stable electrode connection is possible and an improvement effect of connection can be obtained. Even if there is a thin insulating film between the island-shaped portion 121 and the portion 141 of the polycrystalline silicon film, by repeating the etching of the interlayer insulating film, the polycrystalline silicon film, the insulating film, etc.,
The contact hole of the present invention can be formed. Furthermore, in a semiconductor integrated circuit device using a wiring of a polycrystalline silicon film or a wiring structure of a double structure with a tungsten silicide film, a polycrystalline silicon film or a metal silicide forming a wiring or the like is formed in an island shape in a contact hole region. If left untouched, the present invention can be implemented without requiring additional steps.

FIG. 2 is a sectional view showing the steps of forming an electrode portion in an N-channel MOS transistor for explaining another embodiment of the present invention.

In FIG. 1A, 51a and 51b are N-type diffusion regions for forming the source and drain of the N-channel MOS transistor, and the polycrystalline silicon film 4 is formed in the region where the contact hole is to be formed at the same time when the gate electrode is formed. Part of island
Leave 41 to form.

Next, as shown in FIG. 3B, an interlayer insulating film made of a BPSG film
After depositing 131 μm of 0.5 μm and performing reflow at 900 ° C., a photomask 21 overlapping the island-shaped portion 41 of the selectively left first polycrystalline silicon film is formed,
By selective plasma etching, as shown in FIG.
A part 171 of the contact hole region 17 is formed on the upper surface of the island-shaped portion 41 of the first polycrystalline silicon film, and the island-shaped portion 41 is removed by using the photomask at that time, and the gate insulating film 3 is formed. Is oxidized and etched to expose the electrode forming portions of the N-type diffusion regions 51a and 51b as the source and drain.

Next, since the contact hole bottom region opened as described above is not implanted with impurities as an N-type diffusion region, arsenic is ion-implanted from the opening to form the N-type impurity layer 52a,
Forming 52b. Next, an aluminum alloy film is vapor-deposited, a wiring pattern of the aluminum alloy electrodes 8a and 8b is formed by photoetching as shown in FIG. 7D, and the surface protection film 16 made of a plasma nitride film is formed after sintering.
(Not shown) is formed to complete the formation of the device. The surface protective film is omitted in the above.

Also in this embodiment, the side wall of the contact hole is likely to have a stepped shape as shown in an emphasized manner, but in an actual device, the side wall of the contact hole is formed in a rather gentle taper shape. The size on the surface of the contact hole is the first
Although it is not as large as that of the example, the electrode connection effect is sufficient. In particular, when this method is applied to an N-channel MOS device, there is an advantage that it can be implemented without increasing the number of times of forming a polycrystalline silicon film.

In this embodiment, after forming the contact holes, a double-structure electrode of a polycrystalline silicon film containing phosphorus and a tungsten silicide film may be formed instead of the aluminum alloy electrodes 8a and 8b. In this case, the stress of the tungsten silicide film is relieved due to the gentle slope in the contact hole, and the reliability of the wiring can be improved.

(Effects of the Invention) As is apparent from the above description, according to the present invention, in forming an electrode having a fine structure of a high-density semiconductor device,
For example, even if a contact hole with a high aspect ratio of 0.8 μm square and a depth of 1.0 μm is formed, the opening area of the contact hole is substantially expanded, the coverage of aluminum alloy vapor deposition is improved, and a stable electrode is provided. Since the aluminum wiring and the polycrystalline silicon film can have a sufficient withstand voltage of 30 V or more due to the multi-layer interlayer insulating film, and the interlayer withstand voltage has little dependence on the mask alignment accuracy, This has the effect of improving the reliability of the device.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are process sectional views of a first and a second embodiments of the present invention respectively, and FIGS. 3 (a), (b) and (c) are conventional semiconductor integrated circuits. It is a top view, a sectional view, and an equivalent circuit diagram explaining an electrode extraction part of a circuit device. 1 ... P-type silicon substrate, 2 ... Element isolation region, 3 ...
Gate insulating film, 4,12,14 …… Polycrystalline silicon film, 5a, 5b…
… N-type diffusion region, 8a, 8b …… Aluminum alloy electrode, 13,15 ……
Interlayer insulation film.

Claims (4)

(57) [Claims] 1. When forming a semiconductor integrated circuit device, a polycrystalline silicon film is formed on a surface of an impurity diffusion layer formed on a main surface of a semiconductor substrate, and the polycrystalline silicon film is formed into islands in a region where a contact hole is to be formed. A selective etching step of leaving the interlayer insulating film, a selective etching step of removing the interlayer insulating film above the island-shaped portion after covering the interlayer insulating film, and a polycrystalline silicon of the island-shaped portion using the opening of the interlayer insulating film as a mask. An electrode comprising: a step of selectively removing the film to form a contact hole having a stepwise inner wall; and a step of depositing a conductive film on the upper surface of the main surface and forming the conductive film in an electrode pattern. How to configure the take-out section. 2. The method for constructing an electrode lead-out portion according to claim 1, wherein the electrode pattern is composed of a multilayer film of aluminum alloy and heat resistant alloy. 3. When the semiconductor integrated circuit device is formed, the first surface is formed on the surface of the impurity diffusion layer formed on the main surface of the semiconductor substrate.
Forming a polycrystal silicon film and leaving the polycrystal silicon film in a region where a contact hole is to be formed in an island shape, and after covering the first polycrystal silicon film with a first insulating film, the island portion Selective etching process for removing the upper insulating film, stacking a second polycrystalline silicon film on the first polycrystalline silicon film, and overlapping it with the first polycrystalline silicon film in an island shape Let's leave selectively,
A step of repeating selective etching to cover it with a second insulating film and removing the insulating film in a region covering the upper portion of the polycrystalline silicon film; and removing the island-shaped polycrystalline silicon film to form a stepwise inner wall A selective etching step to form
A method for constructing an electrode lead-out portion, comprising a step of depositing a conductive film on a main surface to form an electrode pattern. 4. The method for constructing an electrode lead-out portion according to claim 3, wherein the electrode pattern is composed of a multilayer film of an aluminum alloy and a heat resistant alloy.