JP2522832Y2 - Thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial application field) The present invention relates to a thin film transistor for driving a flat panel display, an image sensor, and the like, and more particularly to a thin film transistor having a good structure in which characteristics of the thin film transistor have little change with time.

(Prior Art) As shown in the cross-sectional view of FIG. 4, a conventional thin film transistor has a chromium (Cr) layer as a gate electrode 2 and a lower insulating layer 3 on a glass or ceramic insulating substrate 1. Silicon nitride (SiNx) as the active layer and intrinsic amorphous silicon (ia-
Si) layer 4, a silicon nitride film (SiNx) as an upper insulating layer 5 provided to face the gate electrode 3, and n ⁺ amorphous silicon (n ⁺ aS) as an ohmic contact layer.
i) The transistor has an inverted staggered structure in which a layer 6, a drain electrode 11 portion and an aluminum (A1) metal layer 7 as a source electrode 12 portion are sequentially laminated.
9672).

In a conventional method of manufacturing a thin film transistor, chromium (Cr) as a gate electrode 2 is deposited on an insulating substrate 1 and patterned into a predetermined shape by a photolithography method to form the gate electrode 2. Next, a silicon nitride film (SiNx) as an insulating layer (lower insulating layer 3) of the gate electrode 2, an intrinsic amorphous silicon (ia-Si) layer 4 as a semiconductor active layer, and a silicon nitride film as an upper insulating layer 5 A film (SiNx) is continuously deposited by a plasma CVD (P-CVD) method.

Then, the insulating film on the silicon nitride film (SiNx) is patterned by photolithography to form the shape of the upper insulating layer 5.

An n ⁺ amorphous silicon (n ⁺ a-Si) layer 6 as an ohmic contact layer is deposited on the upper portion by a P-CVD method. A photoresist is applied thereon, and the ia-Si layer 4 and
A resist pattern is formed so as to form the outer periphery of the n ⁺ a-Si layer 6, and etching is performed.

A metal layer 7 of aluminum (A1) to be the drain electrode 11 and the source electrode 12 of the thin film transistor is deposited thereon by DC magnetron sputtering, and a photoresist is applied thereon. The metal layer 7 is patterned and etched by a photolithography step and an etching step so as to open an upper central portion of the upper insulating layer 5 to form shapes of the drain electrode 11 and the source electrode 12.

Next, when etching is performed using a mixed gas of CF ₄ and O ₂ , the n ⁺ a-Si layer 6 on the gate electrode 2 is removed, and n ⁺ a-Si
The pattern of layer 6 is formed. In this way, a conventional thin film transistor is manufactured.

(Problems to be Solved by the Invention) However, in the above-mentioned conventional thin film transistor, no study has been made to suppress the phenomenon that the value of the threshold voltage shifts due to stress such as voltage as low as possible for practical use. However, there is a problem that the characteristics cannot be stabilized, that is, high reliability cannot be obtained.

Here, in order to stabilize the characteristics of the thin film transistor, in addition to the lower insulating layer, the film quality of the intrinsic amorphous silicon (ia-Si) layer, which is the semiconductor active layer, and the upper insulating layer on the surface is important. know.

In particular, how the upper insulating layer affects the reliability of the thin film transistor will be described with reference to a partial cross-sectional view of the thin film transistor for explaining the electron path in FIG.

In the overlapping portion between the gate electrode 2 and the drain electrode 11, the electrons travel along the interface between the upper insulating layer 5 and the ia-Si layer 4 under the influence of the electric field formed by the drain electrode 11, and the electrons traveling in this portion Is because the electric field in the vertical direction from the drain electrode 11 is trapped in the upper insulating layer 5 and the electric field due to the trapped electrons is very small in the ia-Si layer 4 at about 50 nm, (A channel portion), which reduces the free electron density and causes a shift in threshold voltage.

More specifically, the film forming conditions at the interface between the ia-Si layer 4 and the lower insulating layer 3 of SiNx and at the interface between the ia-Si layer 4 and the upper insulating layer 5 of SiNx are set so as to reduce the electron trap level. Optimized.

However, there is a limit in reducing the interface state density with the ia-Si layer 4, and the lower insulating layer 3 is heated at a high temperature and the upper insulating layer 5 is Since the interface is formed at a lower temperature than that, the interface between the ia-Si layer 4 and the upper insulating layer 5 has more traps than the interface with the lower insulating layer 3. As a result, electrons are likely to be trapped at the interface between the ia-Si layer 4 and the upper insulating layer 5 on the drain electrode 11 side, and this is one of the causes of the aging of the thin film transistor, making it difficult for the current to flow. This is a problem that high reliability cannot be obtained.

The present invention has been made in view of the above circumstances, as a configuration of a thin film transistor such that electrons serving as conductive carriers are not trapped at the interface between the ia-Si layer and the upper insulating layer.
It is an object of the present invention to provide a favorable thin film transistor whose characteristics have little change over time.

(Means) In order to solve the problems of the above conventional example, the present invention is directed to forming a gate electrode on a substrate, a lower insulating layer covering the gate electrode, and an upper insulating layer formed on the gate electrode via the lower insulating layer. An intrinsic amorphous silicon layer,
A thin film transistor having an upper insulating layer formed on the intrinsic amorphous silicon layer, an n ⁺ amorphous silicon layer divided and formed with the upper insulating layer interposed therebetween, and a metal layer covering the n ⁺ amorphous silicon layer. Providing a p-type amorphous silicon layer at a boundary between the intrinsic amorphous silicon layer and the upper insulating layer, and providing an n-type amorphous silicon layer at a boundary between the intrinsic amorphous silicon layer and the n ⁺ amorphous silicon layer. It is characterized by.

(Operation) According to the present invention, the contact between the intrinsic amorphous silicon (ia-Si) layer and the upper insulating layer is p
Ia-type amorphous silicon (pa-Si) layer
Since an n-type amorphous silicon (na-Si) layer is interposed at a portion where the Si layer and the n ⁺ amorphous silicon (n ⁺ a-Si) layer are in contact, the n ⁺ a-Si layer Electrons traveling in the ia-Si layer through the Si layer cannot reach the interface of the upper insulating layer at the overlapping portion of the drain electrode because of the pa-Si layer formed under the upper insulating layer, It is not trapped by traps in the upper insulating layer.

(Embodiment) An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is an explanatory sectional view of a thin film transistor according to an embodiment of the present invention. Portions having the same configuration as in FIG. 4 are described with the same reference numerals.

As shown in FIG. 1, the structure of the thin film transistor of this embodiment is such that a chromium (Cr) layer as a gate electrode 2 on a substrate 1 made of glass or the like, and a silicon nitride film as a lower insulating layer 3 covering the gate electrode 2. (SiNx), an intrinsic amorphous silicon (ia-Si) layer 4 as a semiconductor active layer formed on the gate electrode 2 via the lower insulating layer 3,
A p-type amorphous silicon (pa-Si) layer 8 and a pa-Si layer 8 are formed on the upper surface of the ia-Si layer 4 where the upper insulating layer 5 is formed.
A silicon nitride film (SiNx) as an upper insulating layer 5 formed so as to face the gate electrode 3 is sequentially stacked on the layer 8, and the ia-Si layer 4 divided by the upper insulating layer 5 and the upper
n-type amorphous silicon (na-Si) layer 9 formed between n ⁺ amorphous silicon (n ⁺ a-Si) layer 6;
An n ⁺ a-Si layer 6 containing phosphorus (P) as an ohmic contact layer formed so as to overlap an end of the upper insulating layer 5 on the upper portion of the layer 9, and covers the n ⁺ a-Si layer 6. An inverted staggered transistor in which an aluminum (A1) layer as the metal layer 7 formed as described above is laminated.

Then, the na-Si layer 9 divided by the upper insulating layer 5
, N ⁺ a-Si layer 6 and metal layer 7 form drain electrode 11 and source electrode 12.

Next, a method of manufacturing the thin film transistor according to the present embodiment will be described with reference to FIGS. 3 (a) to 3 (c).

First, chromium (Cr) as a gate electrode 2 on a substrate 1
Is deposited to a thickness of about 500 °, and is patterned into a predetermined shape by a photolithography method to form a pattern of the gate electrode 2.

Next, on the gate electrode 2, SiNx is used as the lower insulating layer 3.
The thickness of the layer is about 3000mm.
The layer 4 is about 500 mm thick and the pa-Si layer 8 is about 50-1000
Approximately 1500 thick SiNx layer as upper insulating layer 5
These four layers are deposited to a thickness of about the same.

Then, the SiNx of the upper insulating layer 5 is patterned so as to face the gate electrode 2 to form a pattern of the upper insulating layer 5 (see FIG. 3A).

Next, n ⁺ a- containing phosphorus (P) of ohmic contact layer
The Si layer 6 is deposited to a thickness of about 1000 ° (FIG. 3 (b)
reference). Then, annealing is performed to change the pa-Si layer 8 in contact with the n ⁺ a-Si layer 6 into a na-Si layer 9. As a result, electrons can pass from the n ⁺ a-Si layer 6 to the ia-Si layer 4 through the na-Si layer 9. However, since the pa-Si layer 8 under the upper insulating layer 5 does not contact the n ⁺ a-Si layer 6, it does not change to na-Si by annealing, and the pa-Si layer 8 does not change.
Will remain as.

Next, the n ⁺ a-Si layer 6, the na-Si layer 9, and the ia-Si layer 4 are patterned to form a pattern in which the n ⁺ a-Si layer 6 overlaps the edge of the upper insulating layer 5. And a pattern of the na-Si layer 9 and a pattern of the ia-Si layer 4 (FIG. 3C)
reference).

Then, aluminum (A1) is deposited to a thickness of about 1 μm by DC magnetron sputtering so as to cover the whole, and patterned in such a shape as to cover the divided n ⁺ a-Si layers 6 respectively. A pattern of the metal layer 7 is formed, and a drain electrode 11 and a source electrode 12 are formed.

As described above, the thin film transistor of this example is manufactured.

Next, a current path in the thin film transistor of this embodiment will be described with reference to a partial cross-sectional view of the thin film transistor shown in FIG.

In this case, the electrons (e ⁻ ) that have entered the ia-Si layer 4 from the n ⁺ a-Si layer 6 on the source electrode 12 side through the na-Si layer 9 are p-
The presence of the a-Si layer 8 makes it difficult for electrons (e ⁻ ) to enter the pa-Si layer 8 even at the overlapping portion of the drain electrode 11 and reaches the interface of the upper insulating layer 5. It cannot be trapped by the trap of the upper insulating layer 5.

The interface state density between the ia-Si layer 4 and the pa-Si layer 8 is
Therefore, unlike the conventional thin film transistor, electrons are not trapped in the trap of the upper insulating layer 5, and a thin film transistor having less change with time than the conventional example can be obtained.

Here, the thickness of the pa-Si layer 8 is 50 to 1000 °. p-
Since the a-Si layer 8 is for preventing electrons from entering the interface of the upper insulating layer 5, if the film thickness is too small, electrons will pass through and the film thickness will be too large. Since only the surface portion of the pa-Si layer 8 can be changed to the na-Si layer 9 when the annealing process is performed, a film thickness of 50 to 1000 ° is appropriate.

According to the thin film transistor of the present embodiment, the pa-Si layer 8 is interposed at the portion where the ia-Si layer 4 and the upper insulating layer 5 are in contact, and the ia-Si layer 4 and the n ⁺ a-Si layer 6 are in contact with each other. Na-Si on the part
Since the layer 9 is interposed, the drain electrode 11
Low interface state density in the overlap region of
The electrons run at the interface between the a-Si layer 4 and the pa-Si layer 8,
Electrons are not captured at the interface of the upper insulating layer 5, and there is an effect that a thin film transistor with little change over time can be obtained.

(Effects of the Invention) According to the present invention, the portion where the intrinsic amorphous silicon (ia-Si) layer and the upper insulating layer are in contact with each other has p
Ia-type amorphous silicon (pa-Si) layer
Since an n-type amorphous silicon (na-Si) layer is interposed at a portion where the Si layer and the n ⁺ amorphous silicon (n ⁺ a-Si) layer are in contact, the n ⁺ a-Si layer Electrons traveling in the ia-Si layer through the Si layer cannot reach the interface of the upper insulating layer at the overlapping portion of the drain electrode because of the pa-Si layer formed under the upper insulating layer,
There is an effect that the characteristics of the thin film transistor can be less changed over time without being captured by traps in the upper insulating layer, and a highly reliable thin film transistor can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a thin film transistor according to an embodiment of the present invention, FIG. 2 is a partial cross-sectional view of a thin film transistor for explaining an electron path, and FIGS.
(C) is a cross-sectional explanatory view of the manufacturing process, FIG. 4 is a cross-sectional explanatory view of a conventional thin film transistor, and FIG. 5 is a partial cross-sectional explanatory view of a conventional thin film transistor for explaining an electron path. DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Gate electrode 3 ... Lower insulating layer 4 ... Intrinsic amorphous silicon layer 5 ... Upper insulating layer 6 ... n ⁺ amorphous silicon layer 7 ... Metal layer 8 ... p-type amorphous silicon layer 9 n-type amorphous silicon layer 11 drain electrode 12 source electrode

Claims (1)

(57) [Scope of request for utility model registration] A gate electrode on a substrate; a lower insulating layer covering the gate electrode; an intrinsic amorphous silicon layer formed on the gate electrode via the lower insulating layer; A thin film transistor having an upper insulating layer formed above the layer, an n ⁺ amorphous silicon layer dividedly formed with the upper insulating layer interposed therebetween, and a metal layer covering the n ⁺ amorphous silicon layer, wherein the intrinsic amorphous A thin film transistor comprising: a p-type amorphous silicon layer provided at a boundary between a silicon layer and the upper insulating layer; and an n-type amorphous silicon layer provided at a boundary between the intrinsic amorphous silicon layer and the n ⁺ amorphous silicon layer. .