JP2516390Y2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2516390Y2
JP2516390Y2 JP1987195253U JP19525387U JP2516390Y2 JP 2516390 Y2 JP2516390 Y2 JP 2516390Y2 JP 1987195253 U JP1987195253 U JP 1987195253U JP 19525387 U JP19525387 U JP 19525387U JP 2516390 Y2 JP2516390 Y2 JP 2516390Y2
Authority
JP
Japan
Prior art keywords
lead
semiconductor chip
outer frame
leads
metal foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1987195253U
Other languages
English (en)
Japanese (ja)
Other versions
JPH01100457U (th
Inventor
武久 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1987195253U priority Critical patent/JP2516390Y2/ja
Publication of JPH01100457U publication Critical patent/JPH01100457U/ja
Application granted granted Critical
Publication of JP2516390Y2 publication Critical patent/JP2516390Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1987195253U 1987-12-23 1987-12-23 半導体装置 Expired - Lifetime JP2516390Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987195253U JP2516390Y2 (ja) 1987-12-23 1987-12-23 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987195253U JP2516390Y2 (ja) 1987-12-23 1987-12-23 半導体装置

Publications (2)

Publication Number Publication Date
JPH01100457U JPH01100457U (th) 1989-07-05
JP2516390Y2 true JP2516390Y2 (ja) 1996-11-06

Family

ID=31485939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987195253U Expired - Lifetime JP2516390Y2 (ja) 1987-12-23 1987-12-23 半導体装置

Country Status (1)

Country Link
JP (1) JP2516390Y2 (th)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010097511A (ko) * 2000-04-24 2001-11-08 이중구 이층형 칩 스케일 반도체 팩키지 및, 그것의 제조 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010097511A (ko) * 2000-04-24 2001-11-08 이중구 이층형 칩 스케일 반도체 팩키지 및, 그것의 제조 방법

Also Published As

Publication number Publication date
JPH01100457U (th) 1989-07-05

Similar Documents

Publication Publication Date Title
US7208826B2 (en) Semiconductor device and method of manufacturing the same
EP0680086B1 (en) Semiconductor device and method of producing said semiconductor device
JPH11312706A (ja) 樹脂封止型半導体装置及びその製造方法、リードフレーム
JP4417150B2 (ja) 半導体装置
US6291262B1 (en) Surface mount TO-220 package and process for the manufacture thereof
US20130200507A1 (en) Two-sided die in a four-sided leadframe based package
JP2516390Y2 (ja) 半導体装置
JP4987041B2 (ja) 半導体装置の製造方法
JPH11330314A (ja) 半導体装置の製造方法及びその構造、該方法に用いるリードフレーム
KR20060039869A (ko) 마이크로 리드프레임패키지 및 마이크로 리드프레임패키지제조방법
US8349655B2 (en) Method of fabricating a two-sided die in a four-sided leadframe based package
JP2515406B2 (ja) 樹脂封止型半導体装置
JPH06302638A (ja) 半導体装置
JPH06232315A (ja) 半導体装置用リードフレーム
JP2529366Y2 (ja) 半導体装置
JP2629853B2 (ja) 半導体装置
JP2507852B2 (ja) 半導体装置
US6794745B1 (en) Lead on chip type semiconductor package
JPH06507276A (ja) リードフレームに接合された介在ダイ取付基板を有する集積回路パッケージ設計
JP2678696B2 (ja) 半導体装置の製造方法
JP2001177007A (ja) 半導体装置及びその製造方法
JP2004281486A (ja) 半導体パッケージ及び同パッケージを用いた半導体装置
JP2667901B2 (ja) 半導体装置の製造方法
WO1997027627A1 (en) Lead frame with circular lead tip layout and improved assembly
JPH023622Y2 (th)